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Viewing changes to drivers/scsi/pm8001/pm8001_hwi.c

  • Committer: Package Import Robot
  • Author(s): Michael Casadevall, Bryan Wu, Dann Frazier, Michael Casadeall
  • Date: 2012-03-10 15:00:54 UTC
  • mfrom: (1.1.1)
  • Revision ID: package-import@ubuntu.com-20120310150054-flugb39zon8vvgwe
Tags: 3.2.0-1600.1
[ Bryan Wu ]
* UBUNTU: import debian/debian.env and debian.armadaxp

[ Dann Frazier ]
* ARM: Armada XP: remove trailing '/' in dirnames in mvRules.mk

[ Michael Casadeall ]
* tools: add some tools for Marvell Armada XP processor
* kernel: timer tick hacking from Marvell
* kernel: Sheeva Errata: add delay on Sheeva when powering down
* net: add Marvell NFP netfilter
* net: socket and skb modifications made by Marvell
* miscdevice: add minor IDs for some Marvell Armada drivers
* fs: introduce memory pool for splice()
* video: EDID detection updates from Marvell Armada XP patchset
* video: backlight: add Marvell Dove LCD backlight driver
* video: display: add THS8200 display driver
* video: framebuffer: add Marvell Dove and Armada XP processor onchip LCD controller driver
* usbtest: add Interrupt transfer testing by Marvell Armada XP code
* usb: ehci: add support for Marvell EHCI controler
* tty/serial: 8250: add support for Marvell Armada XP processor and DeviceTree work
* rtc: add support for Marvell Armada XP onchip RTC controller
* net: pppoe: add Marvell ethernet NFP hook in PPPoE networking driver
* mtd: nand: add support for Marvell Armada XP Nand Flash Controller
* mtd: maps: add Marvell Armada XP specific map driver
* mmc: add support for Marvell Armada XP MMC/SD host controller
* i2c: add support for Marvell Armada XP onchip i2c bus controller
* hwmon: add Kconfig option for Armada XP onchip thermal sensor driver
* dmaengine: add Net DMA support for splice and update Marvell XOR DMA engine driver
* ata: add support for Marvell Armada XP SATA controller and update some quirks
* ARM: add Marvell Armada XP machine to mach-types
* ARM: oprofile: add support for Marvell PJ4B core
* ARM: mm: more ARMv6 switches for Marvell Armada XP
* ARM: remove static declaration to allow compilation
* ARM: alignment access fault trick
* ARM: mm: skip some fault fixing when run on NONE SMP ARMv6 mode during early abort event
* ARM: mm: add Marvell Sheeva CPU Architecture for PJ4B
* ARM: introduce optimized copy operation for Marvell Armada XP
* ARM: SAUCE: hardware breakpoint trick for Marvell Armada XP
* ARM: big endian and little endian tricks for Marvell Armada XP
* ARM: SAUCE: Add Marvell Armada XP build rules to arch/arm/kernel/Makefile
* ARM: vfp: add special handling for Marvell Armada XP
* ARM: add support for Marvell U-Boot
* ARM: add mv_controller_num for ARM PCI drivers
* ARM: add support for local PMUs, general SMP tweaks and cache flushing
* ARM: add Marvell device identifies in glue-proc.h
* ARM: add IPC driver support for Marvell platforms
* ARM: add DMA mapping for Marvell platforms
* ARM: add Sheeva errata and PJ4B code for booting
* ARM: update Kconfig and Makefile to include Marvell Armada XP platforms
* ARM: Armada XP: import LSP from Marvell for Armada XP 3.2 kernel enablement

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Lines of Context:
drivers/scsi/pm8001/pm8001_hwi.c
567
567
        value = pm8001_cr32(pm8001_ha, 0, 0x44);
568
568
        offset = value & 0x03FFFFFF;
569
569
        PM8001_INIT_DBG(pm8001_ha,
570
 
                pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
 
570
                pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
571
571
        pcilogic = (value & 0xFC000000) >> 26;
572
572
        pcibar = get_pci_bar_index(pcilogic);
573
573
        PM8001_INIT_DBG(pm8001_ha,
574
 
                pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
 
574
                pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
575
575
        pm8001_ha->main_cfg_tbl_addr = base_addr =
576
576
                pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
577
577
        pm8001_ha->general_stat_tbl_addr =
1245
1245
 
1246
1246
        if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1247
1247
                PM8001_IO_DBG(pm8001_ha,
1248
 
                        pm8001_printk("No free mpi buffer \n"));
 
1248
                        pm8001_printk("No free mpi buffer\n"));
1249
1249
                return -1;
1250
1250
        }
1251
1251
        BUG_ON(!payload);
1262
1262
        pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1263
1263
                circularQ->pi_offset, circularQ->producer_idx);
1264
1264
        PM8001_IO_DBG(pm8001_ha,
1265
 
                pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
 
1265
                pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1266
1266
                circularQ->consumer_index));
1267
1267
        return 0;
1268
1268
}
1474
1474
        switch (status) {
1475
1475
        case IO_SUCCESS:
1476
1476
                PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1477
 
                        ",param = %d \n", param));
 
1477
                        ",param = %d\n", param));
1478
1478
                if (param == 0) {
1479
1479
                        ts->resp = SAS_TASK_COMPLETE;
1480
1480
                        ts->stat = SAM_STAT_GOOD;
1490
1490
                break;
1491
1491
        case IO_ABORTED:
1492
1492
                PM8001_IO_DBG(pm8001_ha,
1493
 
                        pm8001_printk("IO_ABORTED IOMB Tag \n"));
 
1493
                        pm8001_printk("IO_ABORTED IOMB Tag\n"));
1494
1494
                ts->resp = SAS_TASK_COMPLETE;
1495
1495
                ts->stat = SAS_ABORTED_TASK;
1496
1496
                break;
1497
1497
        case IO_UNDERFLOW:
1498
1498
                /* SSP Completion with error */
1499
1499
                PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1500
 
                        ",param = %d \n", param));
 
1500
                        ",param = %d\n", param));
1501
1501
                ts->resp = SAS_TASK_COMPLETE;
1502
1502
                ts->stat = SAS_DATA_UNDERRUN;
1503
1503
                ts->residual = param;
1649
1649
                ts->resp = SAS_TASK_COMPLETE;
1650
1650
                ts->stat = SAS_OPEN_REJECT;
1651
1651
                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
 
1652
                break;
1652
1653
        default:
1653
1654
                PM8001_IO_DBG(pm8001_ha,
1654
1655
                        pm8001_printk("Unknown status 0x%x\n", status));
1937
1938
                                ts->buf_valid_size = sizeof(*resp);
1938
1939
                        } else
1939
1940
                                PM8001_IO_DBG(pm8001_ha,
1940
 
                                        pm8001_printk("response to large \n"));
 
1941
                                        pm8001_printk("response to large\n"));
1941
1942
                }
1942
1943
                if (pm8001_dev)
1943
1944
                        pm8001_dev->running_req--;
1944
1945
                break;
1945
1946
        case IO_ABORTED:
1946
1947
                PM8001_IO_DBG(pm8001_ha,
1947
 
                        pm8001_printk("IO_ABORTED IOMB Tag \n"));
 
1948
                        pm8001_printk("IO_ABORTED IOMB Tag\n"));
1948
1949
                ts->resp = SAS_TASK_COMPLETE;
1949
1950
                ts->stat = SAS_ABORTED_TASK;
1950
1951
                if (pm8001_dev)
2728
2729
        u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2729
2730
        if (status != 0) {
2730
2731
                PM8001_MSG_DBG(pm8001_ha,
2731
 
                        pm8001_printk("%x phy execute %x phy op failed! \n",
 
2732
                        pm8001_printk("%x phy execute %x phy op failed!\n",
2732
2733
                        phy_id, phy_op));
2733
2734
        } else
2734
2735
                PM8001_MSG_DBG(pm8001_ha,
2735
 
                        pm8001_printk("%x phy execute %x phy op success! \n",
 
2736
                        pm8001_printk("%x phy execute %x phy op success!\n",
2736
2737
                        phy_id, phy_op));
2737
2738
        return 0;
2738
2739
}
3018
3019
                break;
3019
3020
        case PORT_INVALID:
3020
3021
                PM8001_MSG_DBG(pm8001_ha,
3021
 
                        pm8001_printk(" PortInvalid portID %d \n", port_id));
 
3022
                        pm8001_printk(" PortInvalid portID %d\n", port_id));
3022
3023
                PM8001_MSG_DBG(pm8001_ha,
3023
3024
                        pm8001_printk(" Last phy Down and port invalid\n"));
3024
3025
                port->port_attached = 0;
3027
3028
                break;
3028
3029
        case PORT_IN_RESET:
3029
3030
                PM8001_MSG_DBG(pm8001_ha,
3030
 
                        pm8001_printk(" Port In Reset portID %d \n", port_id));
 
3031
                        pm8001_printk(" Port In Reset portID %d\n", port_id));
3031
3032
                break;
3032
3033
        case PORT_NOT_ESTABLISHED:
3033
3034
                PM8001_MSG_DBG(pm8001_ha,
3220
3221
                pm8001_printk(" status = 0x%x\n", status));
3221
3222
        for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3222
3223
                PM8001_MSG_DBG(pm8001_ha,
3223
 
                        pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
 
3224
                        pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3224
3225
                        pPayload->inb_IOMB_payload[i]));
3225
3226
        return 0;
3226
3227
}
3312
3313
                break;
3313
3314
        case HW_EVENT_SAS_PHY_UP:
3314
3315
                PM8001_MSG_DBG(pm8001_ha,
3315
 
                        pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
 
3316
                        pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3316
3317
                hw_event_sas_phy_up(pm8001_ha, piomb);
3317
3318
                break;
3318
3319
        case HW_EVENT_SATA_PHY_UP:
3319
3320
                PM8001_MSG_DBG(pm8001_ha,
3320
 
                        pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
 
3321
                        pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3321
3322
                hw_event_sata_phy_up(pm8001_ha, piomb);
3322
3323
                break;
3323
3324
        case HW_EVENT_PHY_STOP_STATUS:
3329
3330
                break;
3330
3331
        case HW_EVENT_SATA_SPINUP_HOLD:
3331
3332
                PM8001_MSG_DBG(pm8001_ha,
3332
 
                        pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
 
3333
                        pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3333
3334
                sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3334
3335
                break;
3335
3336
        case HW_EVENT_PHY_DOWN:
3336
3337
                PM8001_MSG_DBG(pm8001_ha,
3337
 
                        pm8001_printk("HW_EVENT_PHY_DOWN \n"));
 
3338
                        pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3338
3339
                sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3339
3340
                phy->phy_attached = 0;
3340
3341
                phy->phy_state = 0;
3446
3447
                break;
3447
3448
        case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3448
3449
                PM8001_MSG_DBG(pm8001_ha,
3449
 
                        pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
 
3450
                        pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3450
3451
                pm8001_hw_event_ack_req(pm8001_ha, 0,
3451
3452
                        HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3452
3453
                        port_id, phy_id, 0, 0);
3456
3457
                break;
3457
3458
        case HW_EVENT_PORT_RESET_TIMER_TMO:
3458
3459
                PM8001_MSG_DBG(pm8001_ha,
3459
 
                        pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
 
3460
                        pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3460
3461
                sas_phy_disconnected(sas_phy);
3461
3462
                phy->phy_attached = 0;
3462
3463
                sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3463
3464
                break;
3464
3465
        case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3465
3466
                PM8001_MSG_DBG(pm8001_ha,
3466
 
                        pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
 
3467
                        pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3467
3468
                sas_phy_disconnected(sas_phy);
3468
3469
                phy->phy_attached = 0;
3469
3470
                sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3470
3471
                break;
3471
3472
        case HW_EVENT_PORT_RECOVER:
3472
3473
                PM8001_MSG_DBG(pm8001_ha,
3473
 
                        pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
 
3474
                        pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3474
3475
                break;
3475
3476
        case HW_EVENT_PORT_RESET_COMPLETE:
3476
3477
                PM8001_MSG_DBG(pm8001_ha,
3477
 
                        pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
 
3478
                        pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3478
3479
                break;
3479
3480
        case EVENT_BROADCAST_ASYNCH_EVENT:
3480
3481
                PM8001_MSG_DBG(pm8001_ha,
3502
3503
 
3503
3504
        switch (opc) {
3504
3505
        case OPC_OUB_ECHO:
3505
 
                PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
 
3506
                PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3506
3507
                break;
3507
3508
        case OPC_OUB_HW_EVENT:
3508
3509
                PM8001_MSG_DBG(pm8001_ha,
3509
 
                        pm8001_printk("OPC_OUB_HW_EVENT \n"));
 
3510
                        pm8001_printk("OPC_OUB_HW_EVENT\n"));
3510
3511
                mpi_hw_event(pm8001_ha, piomb);
3511
3512
                break;
3512
3513
        case OPC_OUB_SSP_COMP:
3513
3514
                PM8001_MSG_DBG(pm8001_ha,
3514
 
                        pm8001_printk("OPC_OUB_SSP_COMP \n"));
 
3515
                        pm8001_printk("OPC_OUB_SSP_COMP\n"));
3515
3516
                mpi_ssp_completion(pm8001_ha, piomb);
3516
3517
                break;
3517
3518
        case OPC_OUB_SMP_COMP:
3518
3519
                PM8001_MSG_DBG(pm8001_ha,
3519
 
                        pm8001_printk("OPC_OUB_SMP_COMP \n"));
 
3520
                        pm8001_printk("OPC_OUB_SMP_COMP\n"));
3520
3521
                mpi_smp_completion(pm8001_ha, piomb);
3521
3522
                break;
3522
3523
        case OPC_OUB_LOCAL_PHY_CNTRL:
3526
3527
                break;
3527
3528
        case OPC_OUB_DEV_REGIST:
3528
3529
                PM8001_MSG_DBG(pm8001_ha,
3529
 
                        pm8001_printk("OPC_OUB_DEV_REGIST \n"));
 
3530
                        pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3530
3531
                mpi_reg_resp(pm8001_ha, piomb);
3531
3532
                break;
3532
3533
        case OPC_OUB_DEREG_DEV:
3533
3534
                PM8001_MSG_DBG(pm8001_ha,
3534
 
                        pm8001_printk("unresgister the deviece \n"));
 
3535
                        pm8001_printk("unresgister the deviece\n"));
3535
3536
                mpi_dereg_resp(pm8001_ha, piomb);
3536
3537
                break;
3537
3538
        case OPC_OUB_GET_DEV_HANDLE:
3538
3539
                PM8001_MSG_DBG(pm8001_ha,
3539
 
                        pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
 
3540
                        pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3540
3541
                break;
3541
3542
        case OPC_OUB_SATA_COMP:
3542
3543
                PM8001_MSG_DBG(pm8001_ha,
3543
 
                        pm8001_printk("OPC_OUB_SATA_COMP \n"));
 
3544
                        pm8001_printk("OPC_OUB_SATA_COMP\n"));
3544
3545
                mpi_sata_completion(pm8001_ha, piomb);
3545
3546
                break;
3546
3547
        case OPC_OUB_SATA_EVENT:
3547
3548
                PM8001_MSG_DBG(pm8001_ha,
3548
 
                        pm8001_printk("OPC_OUB_SATA_EVENT \n"));
 
3549
                        pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3549
3550
                mpi_sata_event(pm8001_ha, piomb);
3550
3551
                break;
3551
3552
        case OPC_OUB_SSP_EVENT:
3858
3859
        circularQ = &pm8001_ha->inbnd_q_tbl[0];
3859
3860
        if (task->data_dir == PCI_DMA_NONE) {
3860
3861
                ATAP = 0x04;  /* no data*/
3861
 
                PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
 
3862
                PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3862
3863
        } else if (likely(!task->ata_task.device_control_reg_update)) {
3863
3864
                if (task->ata_task.dma_xfer) {
3864
3865
                        ATAP = 0x06; /* DMA */
3865
 
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
 
3866
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3866
3867
                } else {
3867
3868
                        ATAP = 0x05; /* PIO*/
3868
 
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
 
3869
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3869
3870
                }
3870
3871
                if (task->ata_task.use_ncq &&
3871
3872
                        dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3872
3873
                        ATAP = 0x07; /* FPDMA */
3873
 
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
 
3874
                        PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3874
3875
                }
3875
3876
        }
3876
3877
        if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))