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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/dma-mapping.h>
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <asm/delay.h>
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MODULE_AUTHOR("Stephen Street");
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define TIMOUT_DFLT 1000
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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
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#define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
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#define MAX_DMA_LEN 8191
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#define DMA_ALIGNMENT 8
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* for testing SSCR1 changes that require SSP restart, basically
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* everything except the service and interrupt enables, the pxa270 developer
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* manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
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* list, but the PXA255 dev man says all bits without really meaning the
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* service and interrupt enables
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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
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| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
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| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
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| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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#define DEFINE_SSP_REG(reg, off) \
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static inline u32 read_##reg(void const __iomem *p) \
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{ return __raw_readl(p + (off)); } \
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static inline void write_##reg(u32 v, void __iomem *p) \
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{ __raw_writel(v, p + (off)); }
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DEFINE_SSP_REG(SSCR0, 0x00)
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DEFINE_SSP_REG(SSCR1, 0x04)
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DEFINE_SSP_REG(SSSR, 0x08)
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DEFINE_SSP_REG(SSITR, 0x0c)
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DEFINE_SSP_REG(SSDR, 0x10)
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DEFINE_SSP_REG(SSTO, 0x28)
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DEFINE_SSP_REG(SSPSP, 0x2c)
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#define START_STATE ((void*)0)
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#define RUNNING_STATE ((void*)1)
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#define DONE_STATE ((void*)2)
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#define ERROR_STATE ((void*)-1)
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#define QUEUE_RUNNING 0
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#define QUEUE_STOPPED 1
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/* Driver model hookup */
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struct platform_device *pdev;
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struct ssp_device *ssp;
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/* SPI framework hookup */
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enum pxa_ssp_type ssp_type;
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struct spi_master *master;
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struct pxa2xx_spi_master *master_info;
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/* DMA setup stuff */
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/* SSP register addresses */
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void __iomem *ioaddr;
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/* Driver message queue */
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struct workqueue_struct *workqueue;
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struct work_struct pump_messages;
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struct list_head queue;
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/* Message Transfer pump */
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struct tasklet_struct pump_transfers;
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/* Current message transfer state info */
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struct spi_message* cur_msg;
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struct spi_transfer* cur_transfer;
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struct chip_data *cur_chip;
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int (*write)(struct driver_data *drv_data);
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int (*read)(struct driver_data *drv_data);
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irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
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void (*cs_control)(u32 command);
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int gpio_cs_inverted;
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int (*write)(struct driver_data *drv_data);
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int (*read)(struct driver_data *drv_data);
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void (*cs_control)(u32 command);
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static void pump_messages(struct work_struct *work);
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static void cs_assert(struct driver_data *drv_data)
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struct chip_data *chip = drv_data->cur_chip;
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if (drv_data->ssp_type == CE4100_SSP) {
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write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
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if (chip->cs_control) {
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chip->cs_control(PXA2XX_CS_ASSERT);
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if (gpio_is_valid(chip->gpio_cs))
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gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
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static void cs_deassert(struct driver_data *drv_data)
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struct chip_data *chip = drv_data->cur_chip;
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if (drv_data->ssp_type == CE4100_SSP)
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if (chip->cs_control) {
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chip->cs_control(PXA2XX_CS_DEASSERT);
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if (gpio_is_valid(chip->gpio_cs))
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gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
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static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
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void __iomem *reg = drv_data->ioaddr;
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if (drv_data->ssp_type == CE4100_SSP)
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val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
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write_SSSR(val, reg);
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static int pxa25x_ssp_comp(struct driver_data *drv_data)
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if (drv_data->ssp_type == PXA25x_SSP)
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if (drv_data->ssp_type == CE4100_SSP)
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static int flush(struct driver_data *drv_data)
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unsigned long limit = loops_per_jiffy << 1;
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void __iomem *reg = drv_data->ioaddr;
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while (read_SSSR(reg) & SSSR_RNE) {
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} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
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write_SSSR_CS(drv_data, SSSR_ROR);
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static int null_writer(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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u8 n_bytes = drv_data->n_bytes;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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drv_data->tx += n_bytes;
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static int null_reader(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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u8 n_bytes = drv_data->n_bytes;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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drv_data->rx += n_bytes;
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return drv_data->rx == drv_data->rx_end;
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static int u8_writer(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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write_SSDR(*(u8 *)(drv_data->tx), reg);
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static int u8_reader(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u8 *)(drv_data->rx) = read_SSDR(reg);
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return drv_data->rx == drv_data->rx_end;
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static int u16_writer(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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write_SSDR(*(u16 *)(drv_data->tx), reg);
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static int u16_reader(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u16 *)(drv_data->rx) = read_SSDR(reg);
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return drv_data->rx == drv_data->rx_end;
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static int u32_writer(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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write_SSDR(*(u32 *)(drv_data->tx), reg);
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static int u32_reader(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u32 *)(drv_data->rx) = read_SSDR(reg);
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return drv_data->rx == drv_data->rx_end;
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static void *next_transfer(struct driver_data *drv_data)
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struct spi_message *msg = drv_data->cur_msg;
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struct spi_transfer *trans = drv_data->cur_transfer;
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/* Move to next transfer */
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if (trans->transfer_list.next != &msg->transfers) {
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drv_data->cur_transfer =
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list_entry(trans->transfer_list.next,
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return RUNNING_STATE;
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static int map_dma_buffers(struct driver_data *drv_data)
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struct spi_message *msg = drv_data->cur_msg;
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struct device *dev = &msg->spi->dev;
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if (!drv_data->cur_chip->enable_dma)
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if (msg->is_dma_mapped)
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return drv_data->rx_dma && drv_data->tx_dma;
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if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
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/* Modify setup if rx buffer is null */
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if (drv_data->rx == NULL) {
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*drv_data->null_dma_buf = 0;
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drv_data->rx = drv_data->null_dma_buf;
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drv_data->rx_map_len = 4;
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drv_data->rx_map_len = drv_data->len;
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/* Modify setup if tx buffer is null */
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if (drv_data->tx == NULL) {
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*drv_data->null_dma_buf = 0;
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drv_data->tx = drv_data->null_dma_buf;
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drv_data->tx_map_len = 4;
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drv_data->tx_map_len = drv_data->len;
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/* Stream map the tx buffer. Always do DMA_TO_DEVICE first
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* so we flush the cache *before* invalidating it, in case
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* the tx and rx buffers overlap.
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drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, drv_data->tx_dma))
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/* Stream map the rx buffer */
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drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
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drv_data->rx_map_len, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, drv_data->rx_dma)) {
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dma_unmap_single(dev, drv_data->tx_dma,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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static void unmap_dma_buffers(struct driver_data *drv_data)
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if (!drv_data->dma_mapped)
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if (!drv_data->cur_msg->is_dma_mapped) {
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dev = &drv_data->cur_msg->spi->dev;
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dma_unmap_single(dev, drv_data->rx_dma,
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drv_data->rx_map_len, DMA_FROM_DEVICE);
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dma_unmap_single(dev, drv_data->tx_dma,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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drv_data->dma_mapped = 0;
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/* caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct driver_data *drv_data)
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struct spi_transfer* last_transfer;
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struct spi_message *msg;
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spin_lock_irqsave(&drv_data->lock, flags);
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msg = drv_data->cur_msg;
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drv_data->cur_msg = NULL;
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drv_data->cur_transfer = NULL;
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queue_work(drv_data->workqueue, &drv_data->pump_messages);
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spin_unlock_irqrestore(&drv_data->lock, flags);
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last_transfer = list_entry(msg->transfers.prev,
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/* Delay if requested before any change in chip select */
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if (last_transfer->delay_usecs)
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udelay(last_transfer->delay_usecs);
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/* Drop chip select UNLESS cs_change is true or we are returning
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* a message with an error, or next message is for another chip
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if (!last_transfer->cs_change)
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cs_deassert(drv_data);
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struct spi_message *next_msg;
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/* Holding of cs was hinted, but we need to make sure
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* the next message is for the same chip. Don't waste
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* time with the following tests unless this was hinted.
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* We cannot postpone this until pump_messages, because
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* after calling msg->complete (below) the driver that
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* sent the current message could be unloaded, which
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* could invalidate the cs_control() callback...
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/* get a pointer to the next message, if any */
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spin_lock_irqsave(&drv_data->lock, flags);
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if (list_empty(&drv_data->queue))
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next_msg = list_entry(drv_data->queue.next,
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struct spi_message, queue);
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spin_unlock_irqrestore(&drv_data->lock, flags);
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/* see if the next and current messages point
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if (next_msg && next_msg->spi != msg->spi)
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if (!next_msg || msg->state == ERROR_STATE)
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cs_deassert(drv_data);
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msg->complete(msg->context);
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drv_data->cur_chip = NULL;
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static int wait_ssp_rx_stall(void const __iomem *ioaddr)
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unsigned long limit = loops_per_jiffy << 1;
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while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
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static int wait_dma_channel_stop(int channel)
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unsigned long limit = loops_per_jiffy << 1;
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while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
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static void dma_error_stop(struct driver_data *drv_data, const char *msg)
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void __iomem *reg = drv_data->ioaddr;
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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unmap_dma_buffers(drv_data);
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dev_err(&drv_data->pdev->dev, "%s\n", msg);
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drv_data->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&drv_data->pump_transfers);
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static void dma_transfer_complete(struct driver_data *drv_data)
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void __iomem *reg = drv_data->ioaddr;
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struct spi_message *msg = drv_data->cur_msg;
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/* Clear and disable interrupts on SSP and DMA channels*/
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_handler: dma rx channel stop failed\n");
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if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_transfer: ssp rx stall failed\n");
569
unmap_dma_buffers(drv_data);
571
/* update the buffer pointer for the amount completed in dma */
572
drv_data->rx += drv_data->len -
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(DCMD(drv_data->rx_channel) & DCMD_LENGTH);
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/* read trailing data from fifo, it does not matter how many
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* bytes are in the fifo just read until buffer is full
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* or fifo is empty, which ever occurs first */
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drv_data->read(drv_data);
580
/* return count of what was actually read */
581
msg->actual_length += drv_data->len -
582
(drv_data->rx_end - drv_data->rx);
584
/* Transfer delays and chip select release are
585
* handled in pump_transfers or giveback
588
/* Move to next transfer */
589
msg->state = next_transfer(drv_data);
591
/* Schedule transfer tasklet */
592
tasklet_schedule(&drv_data->pump_transfers);
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static void dma_handler(int channel, void *data)
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struct driver_data *drv_data = data;
598
u32 irq_status = DCSR(channel) & DMA_INT_MASK;
600
if (irq_status & DCSR_BUSERR) {
602
if (channel == drv_data->tx_channel)
603
dma_error_stop(drv_data,
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"bad bus address on tx channel");
607
dma_error_stop(drv_data,
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"bad bus address on rx channel");
613
/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
614
if ((channel == drv_data->tx_channel)
615
&& (irq_status & DCSR_ENDINTR)
616
&& (drv_data->ssp_type == PXA25x_SSP)) {
618
/* Wait for rx to stall */
619
if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
620
dev_err(&drv_data->pdev->dev,
621
"dma_handler: ssp rx stall failed\n");
623
/* finish this transfer, start the next */
624
dma_transfer_complete(drv_data);
628
static irqreturn_t dma_transfer(struct driver_data *drv_data)
631
void __iomem *reg = drv_data->ioaddr;
633
irq_status = read_SSSR(reg) & drv_data->mask_sr;
634
if (irq_status & SSSR_ROR) {
635
dma_error_stop(drv_data, "dma_transfer: fifo overrun");
639
/* Check for false positive timeout */
640
if ((irq_status & SSSR_TINT)
641
&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
642
write_SSSR(SSSR_TINT, reg);
646
if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
648
/* Clear and disable timeout interrupt, do the rest in
649
* dma_transfer_complete */
650
if (!pxa25x_ssp_comp(drv_data))
653
/* finish this transfer, start the next */
654
dma_transfer_complete(drv_data);
659
/* Opps problem detected */
663
static void reset_sccr1(struct driver_data *drv_data)
665
void __iomem *reg = drv_data->ioaddr;
666
struct chip_data *chip = drv_data->cur_chip;
669
sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
670
sccr1_reg &= ~SSCR1_RFT;
671
sccr1_reg |= chip->threshold;
672
write_SSCR1(sccr1_reg, reg);
675
static void int_error_stop(struct driver_data *drv_data, const char* msg)
677
void __iomem *reg = drv_data->ioaddr;
679
/* Stop and reset SSP */
680
write_SSSR_CS(drv_data, drv_data->clear_sr);
681
reset_sccr1(drv_data);
682
if (!pxa25x_ssp_comp(drv_data))
685
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
687
dev_err(&drv_data->pdev->dev, "%s\n", msg);
689
drv_data->cur_msg->state = ERROR_STATE;
690
tasklet_schedule(&drv_data->pump_transfers);
693
static void int_transfer_complete(struct driver_data *drv_data)
695
void __iomem *reg = drv_data->ioaddr;
698
write_SSSR_CS(drv_data, drv_data->clear_sr);
699
reset_sccr1(drv_data);
700
if (!pxa25x_ssp_comp(drv_data))
703
/* Update total byte transferred return count actual bytes read */
704
drv_data->cur_msg->actual_length += drv_data->len -
705
(drv_data->rx_end - drv_data->rx);
707
/* Transfer delays and chip select release are
708
* handled in pump_transfers or giveback
711
/* Move to next transfer */
712
drv_data->cur_msg->state = next_transfer(drv_data);
714
/* Schedule transfer tasklet */
715
tasklet_schedule(&drv_data->pump_transfers);
718
static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
720
void __iomem *reg = drv_data->ioaddr;
722
u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
723
drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
725
u32 irq_status = read_SSSR(reg) & irq_mask;
727
if (irq_status & SSSR_ROR) {
728
int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
732
if (irq_status & SSSR_TINT) {
733
write_SSSR(SSSR_TINT, reg);
734
if (drv_data->read(drv_data)) {
735
int_transfer_complete(drv_data);
740
/* Drain rx fifo, Fill tx fifo and prevent overruns */
742
if (drv_data->read(drv_data)) {
743
int_transfer_complete(drv_data);
746
} while (drv_data->write(drv_data));
748
if (drv_data->read(drv_data)) {
749
int_transfer_complete(drv_data);
753
if (drv_data->tx == drv_data->tx_end) {
757
sccr1_reg = read_SSCR1(reg);
758
sccr1_reg &= ~SSCR1_TIE;
761
* PXA25x_SSP has no timeout, set up rx threshould for the
762
* remaining RX bytes.
764
if (pxa25x_ssp_comp(drv_data)) {
766
sccr1_reg &= ~SSCR1_RFT;
768
bytes_left = drv_data->rx_end - drv_data->rx;
769
switch (drv_data->n_bytes) {
776
if (bytes_left > RX_THRESH_DFLT)
777
bytes_left = RX_THRESH_DFLT;
779
sccr1_reg |= SSCR1_RxTresh(bytes_left);
781
write_SSCR1(sccr1_reg, reg);
784
/* We did something */
788
static irqreturn_t ssp_int(int irq, void *dev_id)
790
struct driver_data *drv_data = dev_id;
791
void __iomem *reg = drv_data->ioaddr;
792
u32 sccr1_reg = read_SSCR1(reg);
793
u32 mask = drv_data->mask_sr;
796
status = read_SSSR(reg);
798
/* Ignore possible writes if we don't need to write */
799
if (!(sccr1_reg & SSCR1_TIE))
802
if (!(status & mask))
805
if (!drv_data->cur_msg) {
807
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
808
write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
809
if (!pxa25x_ssp_comp(drv_data))
811
write_SSSR_CS(drv_data, drv_data->clear_sr);
813
dev_err(&drv_data->pdev->dev, "bad message state "
814
"in interrupt handler\n");
820
return drv_data->transfer_handler(drv_data);
823
static int set_dma_burst_and_threshold(struct chip_data *chip,
824
struct spi_device *spi,
825
u8 bits_per_word, u32 *burst_code,
828
struct pxa2xx_spi_chip *chip_info =
829
(struct pxa2xx_spi_chip *)spi->controller_data;
836
/* Set the threshold (in registers) to equal the same amount of data
837
* as represented by burst size (in bytes). The computation below
838
* is (burst_size rounded up to nearest 8 byte, word or long word)
839
* divided by (bytes/register); the tx threshold is the inverse of
840
* the rx, so that there will always be enough data in the rx fifo
841
* to satisfy a burst, and there will always be enough space in the
842
* tx fifo to accept a burst (a tx burst will overwrite the fifo if
843
* there is not enough space), there must always remain enough empty
844
* space in the rx fifo for any data loaded to the tx fifo.
845
* Whenever burst_size (in bytes) equals bits/word, the fifo threshold
846
* will be 8, or half the fifo;
847
* The threshold can only be set to 2, 4 or 8, but not 16, because
848
* to burst 16 to the tx fifo, the fifo would have to be empty;
849
* however, the minimum fifo trigger level is 1, and the tx will
850
* request service when the fifo is at this level, with only 15 spaces.
853
/* find bytes/word */
854
if (bits_per_word <= 8)
856
else if (bits_per_word <= 16)
861
/* use struct pxa2xx_spi_chip->dma_burst_size if available */
863
req_burst_size = chip_info->dma_burst_size;
865
switch (chip->dma_burst_size) {
867
/* if the default burst size is not set,
869
chip->dma_burst_size = DCMD_BURST8;
881
if (req_burst_size <= 8) {
882
*burst_code = DCMD_BURST8;
884
} else if (req_burst_size <= 16) {
885
if (bytes_per_word == 1) {
886
/* don't burst more than 1/2 the fifo */
887
*burst_code = DCMD_BURST8;
891
*burst_code = DCMD_BURST16;
895
if (bytes_per_word == 1) {
896
/* don't burst more than 1/2 the fifo */
897
*burst_code = DCMD_BURST8;
900
} else if (bytes_per_word == 2) {
901
/* don't burst more than 1/2 the fifo */
902
*burst_code = DCMD_BURST16;
906
*burst_code = DCMD_BURST32;
911
thresh_words = burst_bytes / bytes_per_word;
913
/* thresh_words will be between 2 and 8 */
914
*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
915
| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
920
static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
922
unsigned long ssp_clk = clk_get_rate(ssp->clk);
924
if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
925
return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
927
return ((ssp_clk / rate - 1) & 0xfff) << 8;
930
static void pump_transfers(unsigned long data)
932
struct driver_data *drv_data = (struct driver_data *)data;
933
struct spi_message *message = NULL;
934
struct spi_transfer *transfer = NULL;
935
struct spi_transfer *previous = NULL;
936
struct chip_data *chip = NULL;
937
struct ssp_device *ssp = drv_data->ssp;
938
void __iomem *reg = drv_data->ioaddr;
944
u32 dma_thresh = drv_data->cur_chip->dma_threshold;
945
u32 dma_burst = drv_data->cur_chip->dma_burst_size;
947
/* Get current state information */
948
message = drv_data->cur_msg;
949
transfer = drv_data->cur_transfer;
950
chip = drv_data->cur_chip;
952
/* Handle for abort */
953
if (message->state == ERROR_STATE) {
954
message->status = -EIO;
959
/* Handle end of message */
960
if (message->state == DONE_STATE) {
966
/* Delay if requested at end of transfer before CS change */
967
if (message->state == RUNNING_STATE) {
968
previous = list_entry(transfer->transfer_list.prev,
971
if (previous->delay_usecs)
972
udelay(previous->delay_usecs);
974
/* Drop chip select only if cs_change is requested */
975
if (previous->cs_change)
976
cs_deassert(drv_data);
979
/* Check for transfers that need multiple DMA segments */
980
if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
982
/* reject already-mapped transfers; PIO won't always work */
983
if (message->is_dma_mapped
984
|| transfer->rx_dma || transfer->tx_dma) {
985
dev_err(&drv_data->pdev->dev,
986
"pump_transfers: mapped transfer length "
987
"of %u is greater than %d\n",
988
transfer->len, MAX_DMA_LEN);
989
message->status = -EINVAL;
994
/* warn ... we force this to PIO mode */
995
if (printk_ratelimit())
996
dev_warn(&message->spi->dev, "pump_transfers: "
997
"DMA disabled for transfer length %ld "
999
(long)drv_data->len, MAX_DMA_LEN);
1002
/* Setup the transfer state based on the type of transfer */
1003
if (flush(drv_data) == 0) {
1004
dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1005
message->status = -EIO;
1009
drv_data->n_bytes = chip->n_bytes;
1010
drv_data->dma_width = chip->dma_width;
1011
drv_data->tx = (void *)transfer->tx_buf;
1012
drv_data->tx_end = drv_data->tx + transfer->len;
1013
drv_data->rx = transfer->rx_buf;
1014
drv_data->rx_end = drv_data->rx + transfer->len;
1015
drv_data->rx_dma = transfer->rx_dma;
1016
drv_data->tx_dma = transfer->tx_dma;
1017
drv_data->len = transfer->len & DCMD_LENGTH;
1018
drv_data->write = drv_data->tx ? chip->write : null_writer;
1019
drv_data->read = drv_data->rx ? chip->read : null_reader;
1021
/* Change speed and bit per word on a per transfer */
1023
if (transfer->speed_hz || transfer->bits_per_word) {
1025
bits = chip->bits_per_word;
1026
speed = chip->speed_hz;
1028
if (transfer->speed_hz)
1029
speed = transfer->speed_hz;
1031
if (transfer->bits_per_word)
1032
bits = transfer->bits_per_word;
1034
clk_div = ssp_get_clk_div(ssp, speed);
1037
drv_data->n_bytes = 1;
1038
drv_data->dma_width = DCMD_WIDTH1;
1039
drv_data->read = drv_data->read != null_reader ?
1040
u8_reader : null_reader;
1041
drv_data->write = drv_data->write != null_writer ?
1042
u8_writer : null_writer;
1043
} else if (bits <= 16) {
1044
drv_data->n_bytes = 2;
1045
drv_data->dma_width = DCMD_WIDTH2;
1046
drv_data->read = drv_data->read != null_reader ?
1047
u16_reader : null_reader;
1048
drv_data->write = drv_data->write != null_writer ?
1049
u16_writer : null_writer;
1050
} else if (bits <= 32) {
1051
drv_data->n_bytes = 4;
1052
drv_data->dma_width = DCMD_WIDTH4;
1053
drv_data->read = drv_data->read != null_reader ?
1054
u32_reader : null_reader;
1055
drv_data->write = drv_data->write != null_writer ?
1056
u32_writer : null_writer;
1058
/* if bits/word is changed in dma mode, then must check the
1059
* thresholds and burst also */
1060
if (chip->enable_dma) {
1061
if (set_dma_burst_and_threshold(chip, message->spi,
1064
if (printk_ratelimit())
1065
dev_warn(&message->spi->dev,
1067
"DMA burst size reduced to "
1068
"match bits_per_word\n");
1073
| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1075
| (bits > 16 ? SSCR0_EDSS : 0);
1078
message->state = RUNNING_STATE;
1080
/* Try to map dma buffer and do a dma transfer if successful, but
1081
* only if the length is non-zero and less than MAX_DMA_LEN.
1083
* Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1084
* of PIO instead. Care is needed above because the transfer may
1085
* have have been passed with buffers that are already dma mapped.
1086
* A zero-length transfer in PIO mode will not try to write/read
1087
* to/from the buffers
1089
* REVISIT large transfers are exactly where we most want to be
1090
* using DMA. If this happens much, split those transfers into
1091
* multiple DMA segments rather than forcing PIO.
1093
drv_data->dma_mapped = 0;
1094
if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1095
drv_data->dma_mapped = map_dma_buffers(drv_data);
1096
if (drv_data->dma_mapped) {
1098
/* Ensure we have the correct interrupt handler */
1099
drv_data->transfer_handler = dma_transfer;
1101
/* Setup rx DMA Channel */
1102
DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1103
DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1104
DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1105
if (drv_data->rx == drv_data->null_dma_buf)
1106
/* No target address increment */
1107
DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1108
| drv_data->dma_width
1112
DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1114
| drv_data->dma_width
1118
/* Setup tx DMA Channel */
1119
DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1120
DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1121
DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1122
if (drv_data->tx == drv_data->null_dma_buf)
1123
/* No source address increment */
1124
DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1125
| drv_data->dma_width
1129
DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1131
| drv_data->dma_width
1135
/* Enable dma end irqs on SSP to detect end of transfer */
1136
if (drv_data->ssp_type == PXA25x_SSP)
1137
DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1139
/* Clear status and start DMA engine */
1140
cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1141
write_SSSR(drv_data->clear_sr, reg);
1142
DCSR(drv_data->rx_channel) |= DCSR_RUN;
1143
DCSR(drv_data->tx_channel) |= DCSR_RUN;
1145
/* Ensure we have the correct interrupt handler */
1146
drv_data->transfer_handler = interrupt_transfer;
1149
cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1150
write_SSSR_CS(drv_data, drv_data->clear_sr);
1153
/* see if we need to reload the config registers */
1154
if ((read_SSCR0(reg) != cr0)
1155
|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1156
(cr1 & SSCR1_CHANGE_MASK)) {
1158
/* stop the SSP, and update the other bits */
1159
write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1160
if (!pxa25x_ssp_comp(drv_data))
1161
write_SSTO(chip->timeout, reg);
1162
/* first set CR1 without interrupt and service enables */
1163
write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1164
/* restart the SSP */
1165
write_SSCR0(cr0, reg);
1168
if (!pxa25x_ssp_comp(drv_data))
1169
write_SSTO(chip->timeout, reg);
1172
cs_assert(drv_data);
1174
/* after chip select, release the data by enabling service
1175
* requests and interrupts, without changing any mode bits */
1176
write_SSCR1(cr1, reg);
1179
static void pump_messages(struct work_struct *work)
1181
struct driver_data *drv_data =
1182
container_of(work, struct driver_data, pump_messages);
1183
unsigned long flags;
1185
/* Lock queue and check for queue work */
1186
spin_lock_irqsave(&drv_data->lock, flags);
1187
if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1189
spin_unlock_irqrestore(&drv_data->lock, flags);
1193
/* Make sure we are not already running a message */
1194
if (drv_data->cur_msg) {
1195
spin_unlock_irqrestore(&drv_data->lock, flags);
1199
/* Extract head of queue */
1200
drv_data->cur_msg = list_entry(drv_data->queue.next,
1201
struct spi_message, queue);
1202
list_del_init(&drv_data->cur_msg->queue);
1204
/* Initial message state*/
1205
drv_data->cur_msg->state = START_STATE;
1206
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1207
struct spi_transfer,
1210
/* prepare to setup the SSP, in pump_transfers, using the per
1211
* chip configuration */
1212
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1214
/* Mark as busy and launch transfers */
1215
tasklet_schedule(&drv_data->pump_transfers);
1218
spin_unlock_irqrestore(&drv_data->lock, flags);
1221
static int transfer(struct spi_device *spi, struct spi_message *msg)
1223
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1224
unsigned long flags;
1226
spin_lock_irqsave(&drv_data->lock, flags);
1228
if (drv_data->run == QUEUE_STOPPED) {
1229
spin_unlock_irqrestore(&drv_data->lock, flags);
1233
msg->actual_length = 0;
1234
msg->status = -EINPROGRESS;
1235
msg->state = START_STATE;
1237
list_add_tail(&msg->queue, &drv_data->queue);
1239
if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1240
queue_work(drv_data->workqueue, &drv_data->pump_messages);
1242
spin_unlock_irqrestore(&drv_data->lock, flags);
1247
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1248
struct pxa2xx_spi_chip *chip_info)
1252
if (chip == NULL || chip_info == NULL)
1255
/* NOTE: setup() can be called multiple times, possibly with
1256
* different chip_info, release previously requested GPIO
1258
if (gpio_is_valid(chip->gpio_cs))
1259
gpio_free(chip->gpio_cs);
1261
/* If (*cs_control) is provided, ignore GPIO chip select */
1262
if (chip_info->cs_control) {
1263
chip->cs_control = chip_info->cs_control;
1267
if (gpio_is_valid(chip_info->gpio_cs)) {
1268
err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1270
dev_err(&spi->dev, "failed to request chip select "
1271
"GPIO%d\n", chip_info->gpio_cs);
1275
chip->gpio_cs = chip_info->gpio_cs;
1276
chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1278
err = gpio_direction_output(chip->gpio_cs,
1279
!chip->gpio_cs_inverted);
1285
static int setup(struct spi_device *spi)
1287
struct pxa2xx_spi_chip *chip_info = NULL;
1288
struct chip_data *chip;
1289
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1290
struct ssp_device *ssp = drv_data->ssp;
1291
unsigned int clk_div;
1292
uint tx_thres = TX_THRESH_DFLT;
1293
uint rx_thres = RX_THRESH_DFLT;
1295
if (!pxa25x_ssp_comp(drv_data)
1296
&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1297
dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1298
"b/w not 4-32 for type non-PXA25x_SSP\n",
1299
drv_data->ssp_type, spi->bits_per_word);
1301
} else if (pxa25x_ssp_comp(drv_data)
1302
&& (spi->bits_per_word < 4
1303
|| spi->bits_per_word > 16)) {
1304
dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1305
"b/w not 4-16 for type PXA25x_SSP\n",
1306
drv_data->ssp_type, spi->bits_per_word);
1310
/* Only alloc on first setup */
1311
chip = spi_get_ctldata(spi);
1313
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1316
"failed setup: can't allocate chip data\n");
1320
if (drv_data->ssp_type == CE4100_SSP) {
1321
if (spi->chip_select > 4) {
1322
dev_err(&spi->dev, "failed setup: "
1323
"cs number must not be > 4.\n");
1328
chip->frm = spi->chip_select;
1331
chip->enable_dma = 0;
1332
chip->timeout = TIMOUT_DFLT;
1333
chip->dma_burst_size = drv_data->master_info->enable_dma ?
1337
/* protocol drivers may change the chip settings, so...
1338
* if chip_info exists, use it */
1339
chip_info = spi->controller_data;
1341
/* chip_info isn't always needed */
1344
if (chip_info->timeout)
1345
chip->timeout = chip_info->timeout;
1346
if (chip_info->tx_threshold)
1347
tx_thres = chip_info->tx_threshold;
1348
if (chip_info->rx_threshold)
1349
rx_thres = chip_info->rx_threshold;
1350
chip->enable_dma = drv_data->master_info->enable_dma;
1351
chip->dma_threshold = 0;
1352
if (chip_info->enable_loopback)
1353
chip->cr1 = SSCR1_LBM;
1356
chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1357
(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1359
/* set dma burst and threshold outside of chip_info path so that if
1360
* chip_info goes away after setting chip->enable_dma, the
1361
* burst and threshold can still respond to changes in bits_per_word */
1362
if (chip->enable_dma) {
1363
/* set up legal burst and threshold for dma */
1364
if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1365
&chip->dma_burst_size,
1366
&chip->dma_threshold)) {
1367
dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1368
"to match bits_per_word\n");
1372
clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1373
chip->speed_hz = spi->max_speed_hz;
1377
| SSCR0_DataSize(spi->bits_per_word > 16 ?
1378
spi->bits_per_word - 16 : spi->bits_per_word)
1380
| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1381
chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1382
chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1383
| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1385
/* NOTE: PXA25x_SSP _could_ use external clocking ... */
1386
if (!pxa25x_ssp_comp(drv_data))
1387
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1388
clk_get_rate(ssp->clk)
1389
/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1390
chip->enable_dma ? "DMA" : "PIO");
1392
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1393
clk_get_rate(ssp->clk) / 2
1394
/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1395
chip->enable_dma ? "DMA" : "PIO");
1397
if (spi->bits_per_word <= 8) {
1399
chip->dma_width = DCMD_WIDTH1;
1400
chip->read = u8_reader;
1401
chip->write = u8_writer;
1402
} else if (spi->bits_per_word <= 16) {
1404
chip->dma_width = DCMD_WIDTH2;
1405
chip->read = u16_reader;
1406
chip->write = u16_writer;
1407
} else if (spi->bits_per_word <= 32) {
1408
chip->cr0 |= SSCR0_EDSS;
1410
chip->dma_width = DCMD_WIDTH4;
1411
chip->read = u32_reader;
1412
chip->write = u32_writer;
1414
dev_err(&spi->dev, "invalid wordsize\n");
1417
chip->bits_per_word = spi->bits_per_word;
1419
spi_set_ctldata(spi, chip);
1421
if (drv_data->ssp_type == CE4100_SSP)
1424
return setup_cs(spi, chip, chip_info);
1427
static void cleanup(struct spi_device *spi)
1429
struct chip_data *chip = spi_get_ctldata(spi);
1430
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1435
if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1436
gpio_free(chip->gpio_cs);
1441
static int __devinit init_queue(struct driver_data *drv_data)
1443
INIT_LIST_HEAD(&drv_data->queue);
1444
spin_lock_init(&drv_data->lock);
1446
drv_data->run = QUEUE_STOPPED;
1449
tasklet_init(&drv_data->pump_transfers,
1450
pump_transfers, (unsigned long)drv_data);
1452
INIT_WORK(&drv_data->pump_messages, pump_messages);
1453
drv_data->workqueue = create_singlethread_workqueue(
1454
dev_name(drv_data->master->dev.parent));
1455
if (drv_data->workqueue == NULL)
1461
static int start_queue(struct driver_data *drv_data)
1463
unsigned long flags;
1465
spin_lock_irqsave(&drv_data->lock, flags);
1467
if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1468
spin_unlock_irqrestore(&drv_data->lock, flags);
1472
drv_data->run = QUEUE_RUNNING;
1473
drv_data->cur_msg = NULL;
1474
drv_data->cur_transfer = NULL;
1475
drv_data->cur_chip = NULL;
1476
spin_unlock_irqrestore(&drv_data->lock, flags);
1478
queue_work(drv_data->workqueue, &drv_data->pump_messages);
1483
static int stop_queue(struct driver_data *drv_data)
1485
unsigned long flags;
1486
unsigned limit = 500;
1489
spin_lock_irqsave(&drv_data->lock, flags);
1491
/* This is a bit lame, but is optimized for the common execution path.
1492
* A wait_queue on the drv_data->busy could be used, but then the common
1493
* execution path (pump_messages) would be required to call wake_up or
1494
* friends on every SPI message. Do this instead */
1495
drv_data->run = QUEUE_STOPPED;
1496
while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1497
spin_unlock_irqrestore(&drv_data->lock, flags);
1499
spin_lock_irqsave(&drv_data->lock, flags);
1502
if (!list_empty(&drv_data->queue) || drv_data->busy)
1505
spin_unlock_irqrestore(&drv_data->lock, flags);
1510
static int destroy_queue(struct driver_data *drv_data)
1514
status = stop_queue(drv_data);
1515
/* we are unloading the module or failing to load (only two calls
1516
* to this routine), and neither call can handle a return value.
1517
* However, destroy_workqueue calls flush_workqueue, and that will
1518
* block until all work is done. If the reason that stop_queue
1519
* timed out is that the work will never finish, then it does no
1520
* good to call destroy_workqueue, so return anyway. */
1524
destroy_workqueue(drv_data->workqueue);
1529
static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
1531
struct device *dev = &pdev->dev;
1532
struct pxa2xx_spi_master *platform_info;
1533
struct spi_master *master;
1534
struct driver_data *drv_data;
1535
struct ssp_device *ssp;
1538
platform_info = dev->platform_data;
1540
ssp = pxa_ssp_request(pdev->id, pdev->name);
1542
dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1546
/* Allocate master with space for drv_data and null dma buffer */
1547
master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1549
dev_err(&pdev->dev, "cannot alloc spi_master\n");
1553
drv_data = spi_master_get_devdata(master);
1554
drv_data->master = master;
1555
drv_data->master_info = platform_info;
1556
drv_data->pdev = pdev;
1557
drv_data->ssp = ssp;
1559
master->dev.parent = &pdev->dev;
1560
master->dev.of_node = pdev->dev.of_node;
1561
/* the spi->mode bits understood by this driver: */
1562
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1564
master->bus_num = pdev->id;
1565
master->num_chipselect = platform_info->num_chipselect;
1566
master->dma_alignment = DMA_ALIGNMENT;
1567
master->cleanup = cleanup;
1568
master->setup = setup;
1569
master->transfer = transfer;
1571
drv_data->ssp_type = ssp->type;
1572
drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1573
sizeof(struct driver_data)), 8);
1575
drv_data->ioaddr = ssp->mmio_base;
1576
drv_data->ssdr_physical = ssp->phys_base + SSDR;
1577
if (pxa25x_ssp_comp(drv_data)) {
1578
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1579
drv_data->dma_cr1 = 0;
1580
drv_data->clear_sr = SSSR_ROR;
1581
drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1583
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1584
drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1585
drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1586
drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1589
status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1592
dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1593
goto out_error_master_alloc;
1596
/* Setup DMA if requested */
1597
drv_data->tx_channel = -1;
1598
drv_data->rx_channel = -1;
1599
if (platform_info->enable_dma) {
1601
/* Get two DMA channels (rx and tx) */
1602
drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1606
if (drv_data->rx_channel < 0) {
1607
dev_err(dev, "problem (%d) requesting rx channel\n",
1608
drv_data->rx_channel);
1610
goto out_error_irq_alloc;
1612
drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1616
if (drv_data->tx_channel < 0) {
1617
dev_err(dev, "problem (%d) requesting tx channel\n",
1618
drv_data->tx_channel);
1620
goto out_error_dma_alloc;
1623
DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1624
DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1627
/* Enable SOC clock */
1628
clk_enable(ssp->clk);
1630
/* Load default SSP configuration */
1631
write_SSCR0(0, drv_data->ioaddr);
1632
write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1633
SSCR1_TxTresh(TX_THRESH_DFLT),
1635
write_SSCR0(SSCR0_SCR(2)
1637
| SSCR0_DataSize(8),
1639
if (!pxa25x_ssp_comp(drv_data))
1640
write_SSTO(0, drv_data->ioaddr);
1641
write_SSPSP(0, drv_data->ioaddr);
1643
/* Initial and start queue */
1644
status = init_queue(drv_data);
1646
dev_err(&pdev->dev, "problem initializing queue\n");
1647
goto out_error_clock_enabled;
1649
status = start_queue(drv_data);
1651
dev_err(&pdev->dev, "problem starting queue\n");
1652
goto out_error_clock_enabled;
1655
/* Register with the SPI framework */
1656
platform_set_drvdata(pdev, drv_data);
1657
status = spi_register_master(master);
1659
dev_err(&pdev->dev, "problem registering spi master\n");
1660
goto out_error_queue_alloc;
1665
out_error_queue_alloc:
1666
destroy_queue(drv_data);
1668
out_error_clock_enabled:
1669
clk_disable(ssp->clk);
1671
out_error_dma_alloc:
1672
if (drv_data->tx_channel != -1)
1673
pxa_free_dma(drv_data->tx_channel);
1674
if (drv_data->rx_channel != -1)
1675
pxa_free_dma(drv_data->rx_channel);
1677
out_error_irq_alloc:
1678
free_irq(ssp->irq, drv_data);
1680
out_error_master_alloc:
1681
spi_master_put(master);
1686
static int pxa2xx_spi_remove(struct platform_device *pdev)
1688
struct driver_data *drv_data = platform_get_drvdata(pdev);
1689
struct ssp_device *ssp;
1694
ssp = drv_data->ssp;
1696
/* Remove the queue */
1697
status = destroy_queue(drv_data);
1699
/* the kernel does not check the return status of this
1700
* this routine (mod->exit, within the kernel). Therefore
1701
* nothing is gained by returning from here, the module is
1702
* going away regardless, and we should not leave any more
1703
* resources allocated than necessary. We cannot free the
1704
* message memory in drv_data->queue, but we can release the
1705
* resources below. I think the kernel should honor -EBUSY
1707
dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1708
"complete, message memory not freed\n");
1710
/* Disable the SSP at the peripheral and SOC level */
1711
write_SSCR0(0, drv_data->ioaddr);
1712
clk_disable(ssp->clk);
1715
if (drv_data->master_info->enable_dma) {
1716
DRCMR(ssp->drcmr_rx) = 0;
1717
DRCMR(ssp->drcmr_tx) = 0;
1718
pxa_free_dma(drv_data->tx_channel);
1719
pxa_free_dma(drv_data->rx_channel);
1723
free_irq(ssp->irq, drv_data);
1728
/* Disconnect from the SPI framework */
1729
spi_unregister_master(drv_data->master);
1731
/* Prevent double remove */
1732
platform_set_drvdata(pdev, NULL);
1737
static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1741
if ((status = pxa2xx_spi_remove(pdev)) != 0)
1742
dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1746
static int pxa2xx_spi_suspend(struct device *dev)
1748
struct driver_data *drv_data = dev_get_drvdata(dev);
1749
struct ssp_device *ssp = drv_data->ssp;
1752
status = stop_queue(drv_data);
1755
write_SSCR0(0, drv_data->ioaddr);
1756
clk_disable(ssp->clk);
1761
static int pxa2xx_spi_resume(struct device *dev)
1763
struct driver_data *drv_data = dev_get_drvdata(dev);
1764
struct ssp_device *ssp = drv_data->ssp;
1767
if (drv_data->rx_channel != -1)
1768
DRCMR(drv_data->ssp->drcmr_rx) =
1769
DRCMR_MAPVLD | drv_data->rx_channel;
1770
if (drv_data->tx_channel != -1)
1771
DRCMR(drv_data->ssp->drcmr_tx) =
1772
DRCMR_MAPVLD | drv_data->tx_channel;
1774
/* Enable the SSP clock */
1775
clk_enable(ssp->clk);
1777
/* Start the queue running */
1778
status = start_queue(drv_data);
1780
dev_err(dev, "problem starting queue (%d)\n", status);
1787
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1788
.suspend = pxa2xx_spi_suspend,
1789
.resume = pxa2xx_spi_resume,
1793
static struct platform_driver driver = {
1795
.name = "pxa2xx-spi",
1796
.owner = THIS_MODULE,
1798
.pm = &pxa2xx_spi_pm_ops,
1801
.probe = pxa2xx_spi_probe,
1802
.remove = pxa2xx_spi_remove,
1803
.shutdown = pxa2xx_spi_shutdown,
1806
static int __init pxa2xx_spi_init(void)
1808
return platform_driver_register(&driver);
1810
subsys_initcall(pxa2xx_spi_init);
1812
static void __exit pxa2xx_spi_exit(void)
1814
platform_driver_unregister(&driver);
1816
module_exit(pxa2xx_spi_exit);