68
68
#define VEC_POS(v) ((v) & (32 - 1))
69
69
#define REG_POS(v) (((v) >> 5) << 4)
71
static unsigned int min_timer_period_us = 500;
72
module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
71
74
static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
73
76
return *((u32 *) (apic->regs + reg_off));
135
138
return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
141
static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
143
return ((apic_get_reg(apic, APIC_LVTT) &
144
apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
138
147
static inline int apic_lvtt_period(struct kvm_lapic *apic)
140
return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
149
return ((apic_get_reg(apic, APIC_LVTT) &
150
apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
153
static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
155
return ((apic_get_reg(apic, APIC_LVTT) &
156
apic->lapic_timer.timer_mode_mask) ==
157
APIC_LVT_TIMER_TSCDEADLINE);
143
160
static inline int apic_lvt_nmi_mode(u32 lvt_val)
168
185
static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
169
LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
186
LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
170
187
LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
171
188
LVT_MASK | APIC_MODE_MASK, /* LVTPC */
172
189
LINT_MASK, LINT_MASK, /* LVT0-1 */
319
printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
320
apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
336
apic_debug("Bad DFR vcpu %d: %08x\n",
337
apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
565
582
val = kvm_apic_id(apic) << 24;
567
584
case APIC_ARBPRI:
568
printk(KERN_WARNING "Access APIC ARBPRI register "
569
"which is for P6\n");
585
apic_debug("Access APIC ARBPRI register which is for P6\n");
572
588
case APIC_TMCCT: /* Timer CCR */
589
if (apic_lvtt_tscdeadline(apic))
573
592
val = apic_get_tmcct(apic);
665
684
static void start_apic_timer(struct kvm_lapic *apic)
667
ktime_t now = apic->lapic_timer.timer.base->get_time();
669
apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
670
APIC_BUS_CYCLE_NS * apic->divide_count;
671
687
atomic_set(&apic->lapic_timer.pending, 0);
673
if (!apic->lapic_timer.period)
676
* Do not allow the guest to program periodic timers with small
677
* interval, since the hrtimers are not throttled by the host
680
if (apic_lvtt_period(apic)) {
681
if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
682
apic->lapic_timer.period = NSEC_PER_MSEC/2;
685
hrtimer_start(&apic->lapic_timer.timer,
686
ktime_add_ns(now, apic->lapic_timer.period),
689
apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
689
if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
690
/* lapic timer in oneshot or peroidic mode */
691
now = apic->lapic_timer.timer.base->get_time();
692
apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
693
* APIC_BUS_CYCLE_NS * apic->divide_count;
695
if (!apic->lapic_timer.period)
698
* Do not allow the guest to program periodic timers with small
699
* interval, since the hrtimers are not throttled by the host
702
if (apic_lvtt_period(apic)) {
703
s64 min_period = min_timer_period_us * 1000LL;
705
if (apic->lapic_timer.period < min_period) {
707
"kvm: vcpu %i: requested %lld ns "
708
"lapic timer period limited to %lld ns\n",
710
apic->lapic_timer.period, min_period);
711
apic->lapic_timer.period = min_period;
715
hrtimer_start(&apic->lapic_timer.timer,
716
ktime_add_ns(now, apic->lapic_timer.period),
719
apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
691
721
"timer initial count 0x%x, period %lldns, "
692
722
"expire @ 0x%016" PRIx64 ".\n", __func__,
695
725
apic->lapic_timer.period,
696
726
ktime_to_ns(ktime_add_ns(now,
697
727
apic->lapic_timer.period)));
728
} else if (apic_lvtt_tscdeadline(apic)) {
729
/* lapic timer in tsc deadline mode */
730
u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
732
struct kvm_vcpu *vcpu = apic->vcpu;
733
unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu);
736
if (unlikely(!tscdeadline || !this_tsc_khz))
739
local_irq_save(flags);
741
now = apic->lapic_timer.timer.base->get_time();
742
guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
743
if (likely(tscdeadline > guest_tsc)) {
744
ns = (tscdeadline - guest_tsc) * 1000000ULL;
745
do_div(ns, this_tsc_khz);
747
hrtimer_start(&apic->lapic_timer.timer,
748
ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
750
local_irq_restore(flags);
700
754
static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
853
if ((apic_get_reg(apic, APIC_LVTT) &
854
apic->lapic_timer.timer_mode_mask) !=
855
(val & apic->lapic_timer.timer_mode_mask))
856
hrtimer_cancel(&apic->lapic_timer.timer);
858
if (!apic_sw_enabled(apic))
859
val |= APIC_LVT_MASKED;
860
val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
861
apic_set_reg(apic, APIC_LVTT, val);
865
if (apic_lvtt_tscdeadline(apic))
800
868
hrtimer_cancel(&apic->lapic_timer.timer);
801
869
apic_set_reg(apic, APIC_TMICT, val);
802
870
start_apic_timer(apic);
807
printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
875
apic_debug("KVM_WRITE:TDCR %x\n", val);
808
876
apic_set_reg(apic, APIC_TDCR, val);
809
877
update_divide_count(apic);
813
881
if (apic_x2apic_mode(apic) && val != 0) {
814
printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
882
apic_debug("KVM_WRITE:ESR not zero %x\n", val);
935
void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
937
struct kvm_lapic *apic = vcpu->arch.apic;
940
apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
942
EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
867
944
void kvm_free_lapic(struct kvm_vcpu *vcpu)
869
946
if (!vcpu->arch.apic)
883
960
*----------------------------------------------------------------------
963
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
965
struct kvm_lapic *apic = vcpu->arch.apic;
969
if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
972
return apic->lapic_timer.tscdeadline;
975
void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
977
struct kvm_lapic *apic = vcpu->arch.apic;
981
if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
984
hrtimer_cancel(&apic->lapic_timer.timer);
985
apic->lapic_timer.tscdeadline = data;
986
start_apic_timer(apic);
886
989
void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
888
991
struct kvm_lapic *apic = vcpu->arch.apic;