922
921
#define M25P_INSTR_DP 0xb9
923
922
#define M25P_INSTR_RES 0xab
924
/* Minidump related */
927
* Version of the template
929
* X.Major.Minor.RELEASE
931
#define QLA82XX_MINIDUMP_VERSION 0x10101
936
#define QLA82XX_RDNOP 0
937
#define QLA82XX_RDCRB 1
938
#define QLA82XX_RDMUX 2
939
#define QLA82XX_QUEUE 3
940
#define QLA82XX_BOARD 4
941
#define QLA82XX_RDSRE 5
942
#define QLA82XX_RDOCM 6
943
#define QLA82XX_CACHE 10
944
#define QLA82XX_L1DAT 11
945
#define QLA82XX_L1INS 12
946
#define QLA82XX_L2DTG 21
947
#define QLA82XX_L2ITG 22
948
#define QLA82XX_L2DAT 23
949
#define QLA82XX_L2INS 24
950
#define QLA82XX_RDROM 71
951
#define QLA82XX_RDMEM 72
952
#define QLA82XX_CNTRL 98
953
#define QLA82XX_TLHDR 99
954
#define QLA82XX_RDEND 255
957
* Opcodes for Control Entries.
958
* These Flags are bit fields.
960
#define QLA82XX_DBG_OPCODE_WR 0x01
961
#define QLA82XX_DBG_OPCODE_RW 0x02
962
#define QLA82XX_DBG_OPCODE_AND 0x04
963
#define QLA82XX_DBG_OPCODE_OR 0x08
964
#define QLA82XX_DBG_OPCODE_POLL 0x10
965
#define QLA82XX_DBG_OPCODE_RDSTATE 0x20
966
#define QLA82XX_DBG_OPCODE_WRSTATE 0x40
967
#define QLA82XX_DBG_OPCODE_MDSTATE 0x80
970
* Template Header and Entry Header definitions start here.
975
* Parts of the template header can be modified by the driver.
976
* These include the saved_state_array, capture_debug_level, driver_timestamp
979
#define QLA82XX_DBG_STATE_ARRAY_LEN 16
980
#define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
981
#define QLA82XX_DBG_RSVD_ARRAY_LEN 8
986
#define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
987
#define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */
989
struct qla82xx_md_template_hdr {
991
uint32_t first_entry_offset;
992
uint32_t size_of_template;
993
uint32_t capture_debug_level;
995
uint32_t num_of_entries;
997
uint32_t driver_timestamp;
998
uint32_t template_checksum;
1000
uint32_t driver_capture_mask;
1001
uint32_t driver_info[3];
1003
uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN];
1004
uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN];
1006
/* markers_array used to capture some special locations on board */
1007
uint32_t markers_array[QLA82XX_DBG_RSVD_ARRAY_LEN];
1008
uint32_t num_of_free_entries; /* For internal use */
1009
uint32_t free_entry_offset; /* For internal use */
1010
uint32_t total_table_size; /* For internal use */
1011
uint32_t bkup_table_offset; /* For internal use */
1015
* Entry Header: Common to All Entry Types
1019
* Driver Code is for driver to write some info about the entry.
1020
* Currently not used.
1022
typedef struct qla82xx_md_entry_hdr {
1023
uint32_t entry_type;
1024
uint32_t entry_size;
1025
uint32_t entry_capture_size;
1027
uint8_t entry_capture_mask;
1029
uint8_t driver_code;
1030
uint8_t driver_flags;
1032
} __packed qla82xx_md_entry_hdr_t;
1035
* Read CRB entry header
1037
struct qla82xx_md_entry_crb {
1038
qla82xx_md_entry_hdr_t h;
1041
uint8_t addr_stride;
1042
uint8_t state_index_a;
1043
uint16_t poll_timeout;
1051
uint8_t state_index_v;
1062
* Cache entry header
1064
struct qla82xx_md_entry_cache {
1065
qla82xx_md_entry_hdr_t h;
1067
uint32_t tag_reg_addr;
1069
uint16_t tag_value_stride;
1070
uint16_t init_tag_value;
1076
uint32_t control_addr;
1078
uint16_t write_value;
1085
uint8_t read_addr_stride;
1086
uint8_t read_addr_cnt;
1094
struct qla82xx_md_entry_rdocm {
1095
qla82xx_md_entry_hdr_t h;
1105
uint32_t read_addr_stride;
1106
uint32_t read_addr_cntrl;
1112
struct qla82xx_md_entry_rdmem {
1113
qla82xx_md_entry_hdr_t h;
1116
uint32_t read_data_size;
1122
struct qla82xx_md_entry_rdrom {
1123
qla82xx_md_entry_hdr_t h;
1126
uint32_t read_data_size;
1129
struct qla82xx_md_entry_mux {
1130
qla82xx_md_entry_hdr_t h;
1132
uint32_t select_addr;
1137
uint32_t select_value;
1138
uint32_t select_value_stride;
1143
struct qla82xx_md_entry_queue {
1144
qla82xx_md_entry_hdr_t h;
1146
uint32_t select_addr;
1148
uint16_t queue_id_stride;
1159
uint8_t read_addr_stride;
1160
uint8_t read_addr_cnt;
1165
#define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1166
#define RQST_TMPLT_SIZE 0x0
1167
#define RQST_TMPLT 0x1
1168
#define MD_DIRECT_ROM_WINDOW 0x42110030
1169
#define MD_DIRECT_ROM_READ_BASE 0x42150000
1170
#define MD_MIU_TEST_AGT_CTRL 0x41000090
1171
#define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1172
#define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1174
static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 0x410000AC,
1175
0x410000B8, 0x410000BC };
1177
#define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1178
#define CRB_NIU_XG_PAUSE_CTL_P1 0x8