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  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Documentation/ABI/testing/sysfs-devices-system-cpu
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                to learn how to control the knobs.
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What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
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Date:      August 2008
 
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What:           /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
 
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Date:           August 2008
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KernelVersion:  2.6.27
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Contact:        mark.langsdorf@amd.com
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Description:    These files exist in every cpu's cache index directories.
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                There are currently 2 cache_disable_# files in each
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                directory.  Reading from these files on a supported
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                processor will return that cache disable index value
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                for that processor and node.  Writing to one of these
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                files will cause the specificed cache index to be disabled.
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                Currently, only AMD Family 10h Processors support cache index
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                disable, and only for their L3 caches.  See the BIOS and
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                Kernel Developer's Guide at
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                http://support.amd.com/us/Embedded_TechDocs/31116-Public-GH-BKDG_3-28_5-28-09.pdf       
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                for formatting information and other details on the
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                cache index disable.
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Users:    joachim.deguara@amd.com
 
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Contact:        discuss@x86-64.org
 
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Description:    Disable L3 cache indices
 
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                These files exist in every CPU's cache/index3 directory. Each
 
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                cache_disable_{0,1} file corresponds to one disable slot which
 
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                can be used to disable a cache index. Reading from these files
 
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                on a processor with this functionality will return the currently
 
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                disabled index for that node. There is one L3 structure per
 
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                node, or per internal node on MCM machines. Writing a valid
 
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                index to one of these files will cause the specificed cache
 
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                index to be disabled.
 
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                All AMD processors with L3 caches provide this functionality.
 
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                For details, see BKDGs at
 
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                http://developer.amd.com/documentation/guides/Pages/default.aspx