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* GPL LICENSE SUMMARY
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* Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
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* Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* Keep-Warm (KW) buffer base address.
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* Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
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* Driver must allocate a 4KByte buffer that is for keeping the
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* host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
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* DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
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* DRAM access when doing Txing or Rxing. The dummy accesses prevent host
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* from going into a power-savings mode that would cause higher DRAM latency,
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* and possible data over/under-runs, before all Tx/Rx is complete.
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* Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
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* of the buffer, which must be 4K aligned. Once this is set up, the 4965
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* of the buffer, which must be 4K aligned. Once this is set up, the device
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* automatically invokes keep-warm accesses when normal accesses might not
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* be sufficient to maintain fast DRAM response.
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* TFD Circular Buffers Base (CBBC) addresses
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* 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
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* Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
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* circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
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* (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
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* bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
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* Rx SRAM Control and Status Registers (RSCSR)
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* These registers provide handshake between driver and 4965 for the Rx queue
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* These registers provide handshake between driver and device for the Rx queue
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* (this queue handles *all* command responses, notifications, Rx data, etc.
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* sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
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* sent from uCode to host driver). Unlike Tx, there is only one Rx
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* queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
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* concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
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* Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
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* mapping between RBDs and RBs.
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* Driver must allocate host DRAM memory for the following, and set the
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* physical address of each into 4965 registers:
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* physical address of each into device registers:
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* 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
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* entries (although any power of 2, up to 4096, is selectable by driver).
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* Driver sets physical address [35:8] of base of RBD circular buffer
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* into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
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* 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
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* 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
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* (RBs) have been filled, via a "write pointer", actually the index of
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* the RB's corresponding RBD within the circular buffer. Driver sets
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* physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
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* Bit fields in lower dword of Rx status buffer (upper dword not used
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* by driver; see struct iwl4965_shared, val0):
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* 31-12: Not used by driver
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* 11- 0: Index of last filled Rx buffer descriptor
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* (4965 writes, driver reads this value)
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* (device writes, driver reads this value)
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* As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
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* As the driver prepares Receive Buffers (RBs) for device to fill, driver must
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* enter pointers to these RBs into contiguous RBD circular buffer entries,
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* and update the 4965's "write" index register,
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* and update the device's "write" index register,
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* FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
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* This "write" index corresponds to the *next* RBD that the driver will make
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* RBs), should be 8 after preparing the first 8 RBs (for example), and must
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* wrap back to 0 at the end of the circular buffer (but don't wrap before
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* "read" index has advanced past 1! See below).
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* NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
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* NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
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* As the 4965 fills RBs (referenced from contiguous RBDs within the circular
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* As the device fills RBs (referenced from contiguous RBDs within the circular
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* buffer), it updates the Rx status buffer in host DRAM, 2) described above,
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* to tell the driver the index of the latest filled RBD. The driver must
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* read this "read" index from DRAM after receiving an Rx interrupt from 4965.
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* read this "read" index from DRAM after receiving an Rx interrupt from device
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* The driver must also internally keep track of a third index, which is the
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* next RBD to process. When receiving an Rx interrupt, driver should process
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* driver may process the RB pointed to by RBD 0. Depending on volume of
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* traffic, there may be many RBs to process.
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* If read index == write index, 4965 thinks there is no room to put new data.
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* If read index == write index, device thinks there is no room to put new data.
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* Due to this, the maximum number of filled RBs is 255, instead of 256. To
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* be safe, make sure that there is a gap of at least 2 RBDs between "write"
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* and "read" indexes; that is, make sure that there are no more than 254
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* Transmit DMA Channel Control/Status Registers (TCSR)
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* 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
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* Device has one configuration register for each of 8 Tx DMA/FIFO channels
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* supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
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* which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
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#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
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/* Find Control/Status reg for given Tx DMA/FIFO channel */
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#define FH49_TCSR_CHNL_NUM (7)
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#define FH50_TCSR_CHNL_NUM (8)
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/* TCSR: tx_config register values */
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#define RX_LOW_WATERMARK 8
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/* Size of one Rx buffer in host DRAM */
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#define IWL_RX_BUF_SIZE_3K (3 * 1000) /* 3945 only */
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#define IWL_RX_BUF_SIZE_4K (4 * 1024)
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#define IWL_RX_BUF_SIZE_8K (8 * 1024)
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* @finished_rb_num [0:11] - Indicates the index of the current RB
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* in which the last frame was written to
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* @finished_fr_num [0:11] - Indicates the index of the RX Frame
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* which was transfered
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* which was transferred
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struct iwl_rb_status {
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__le16 closed_rb_num;
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__le16 closed_fr_num;
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__le16 finished_rb_num;
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__le16 finished_fr_nam;
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__le32 __unused; /* 3945 only */