← Back to branch summary

~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

« back to all changes in this revision

Viewing changes to arch/mips/cavium-octeon/smp.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

Show diffs side-by-side

added added

removed removed

Lines of Context:
arch/mips/cavium-octeon/smp.c
37
37
        uint64_t action;
38
38
 
39
39
        /* Load the mailbox register to figure out what we're supposed to do */
40
 
        action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
 
40
        action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
41
41
 
42
42
        /* Clear the mailbox to clear the interrupt */
43
43
        cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
44
44
 
45
45
        if (action & SMP_CALL_FUNCTION)
46
46
                smp_call_function_interrupt();
 
47
        if (action & SMP_RESCHEDULE_YOURSELF)
 
48
                scheduler_ipi();
47
49
 
48
50
        /* Check if we've been told to flush the icache */
49
51
        if (action & SMP_ICACHE_FLUSH)
171
173
 * After we've done initial boot, this function is called to allow the
172
174
 * board code to clean up state, if needed
173
175
 */
174
 
static void octeon_init_secondary(void)
 
176
static void __cpuinit octeon_init_secondary(void)
175
177
{
176
 
        const int coreid = cvmx_get_core_num();
177
 
        union cvmx_ciu_intx_sum0 interrupt_enable;
178
178
        unsigned int sr;
179
179
 
180
 
#ifdef CONFIG_HOTPLUG_CPU
181
 
        struct linux_app_boot_info *labi;
182
 
 
183
 
        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
184
 
 
185
 
        if (labi->labi_signature != LABI_SIGNATURE)
186
 
                panic("The bootloader version on this board is incorrect.");
187
 
#endif
188
 
 
189
180
        sr = set_c0_status(ST0_BEV);
190
181
        write_c0_ebase((u32)ebase);
191
182
        write_c0_status(sr);
192
183
 
193
184
        octeon_check_cpu_bist();
194
185
        octeon_init_cvmcount();
195
 
        /*
196
 
        pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
197
 
        */
198
 
        /* Enable Mailbox interrupts to this core. These are the only
199
 
           interrupts allowed on line 3 */
200
 
        cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
201
 
        interrupt_enable.u64 = 0;
202
 
        interrupt_enable.s.mbox = 0x3;
203
 
        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
204
 
        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
205
 
        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
206
 
        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
207
 
        /* Enable core interrupt processing for 2,3 and 7 */
208
 
        set_c0_status(0x8c01);
 
186
 
 
187
        octeon_irq_setup_secondary();
 
188
        raw_local_irq_enable();
209
189
}
210
190
 
211
191
/**
214
194
 */
215
195
void octeon_prepare_cpus(unsigned int max_cpus)
216
196
{
217
 
        cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
 
197
#ifdef CONFIG_HOTPLUG_CPU
 
198
        struct linux_app_boot_info *labi;
 
199
 
 
200
        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 
201
 
 
202
        if (labi->labi_signature != LABI_SIGNATURE)
 
203
                panic("The bootloader version on this board is incorrect.");
 
204
#endif
 
205
        /*
 
206
         * Only the low order mailbox bits are used for IPIs, leave
 
207
         * the other bits alone.
 
208
         */
 
209
        cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
218
210
        if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
219
 
                        "mailbox0", mailbox_interrupt)) {
 
211
                        "SMP-IPI", mailbox_interrupt)) {
220
212
                panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
221
213
        }
222
 
        if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
223
 
                        "mailbox1", mailbox_interrupt)) {
224
 
                panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
225
 
        }
226
214
}
227
215
 
228
216
/**