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Viewing changes to arch/arm/mach-exynos4/include/mach/regs-usb-phy.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
 
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/*
 
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 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 
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 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 
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 *
 
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 * This program is free software; you can redistribute  it and/or modify it
 
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 * under  the terms of  the GNU General  Public License as published by the
 
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 * Free Software Foundation;  either version 2 of the  License, or (at your
 
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 * option) any later version.
 
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 */
 
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#ifndef __PLAT_S5P_REGS_USB_PHY_H
 
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#define __PLAT_S5P_REGS_USB_PHY_H
 
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#define EXYNOS4_HSOTG_PHYREG(x)         ((x) + S3C_VA_USB_HSPHY)
 
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#define EXYNOS4_PHYPWR                  EXYNOS4_HSOTG_PHYREG(0x00)
 
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#define PHY1_HSIC_NORMAL_MASK           (0xf << 9)
 
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#define PHY1_HSIC1_SLEEP                (1 << 12)
 
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#define PHY1_HSIC1_FORCE_SUSPEND        (1 << 11)
 
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#define PHY1_HSIC0_SLEEP                (1 << 10)
 
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#define PHY1_HSIC0_FORCE_SUSPEND        (1 << 9)
 
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#define PHY1_STD_NORMAL_MASK            (0x7 << 6)
 
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#define PHY1_STD_SLEEP                  (1 << 8)
 
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#define PHY1_STD_ANALOG_POWERDOWN       (1 << 7)
 
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#define PHY1_STD_FORCE_SUSPEND          (1 << 6)
 
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#define PHY0_NORMAL_MASK                (0x39 << 0)
 
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#define PHY0_SLEEP                      (1 << 5)
 
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#define PHY0_OTG_DISABLE                (1 << 4)
 
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#define PHY0_ANALOG_POWERDOWN           (1 << 3)
 
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#define PHY0_FORCE_SUSPEND              (1 << 0)
 
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#define EXYNOS4_PHYCLK                  EXYNOS4_HSOTG_PHYREG(0x04)
 
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#define PHY1_COMMON_ON_N                (1 << 7)
 
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#define PHY0_COMMON_ON_N                (1 << 4)
 
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#define PHY0_ID_PULLUP                  (1 << 2)
 
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#define CLKSEL_MASK                     (0x3 << 0)
 
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#define CLKSEL_SHIFT                    (0)
 
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#define CLKSEL_48M                      (0x0 << 0)
 
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#define CLKSEL_12M                      (0x2 << 0)
 
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#define CLKSEL_24M                      (0x3 << 0)
 
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#define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
 
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#define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
 
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#define HOST_LINK_PORT2_SWRST           (1 << 9)
 
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#define HOST_LINK_PORT1_SWRST           (1 << 8)
 
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#define HOST_LINK_PORT0_SWRST           (1 << 7)
 
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#define HOST_LINK_ALL_SWRST             (1 << 6)
 
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#define PHY1_SWRST_MASK                 (0x7 << 3)
 
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#define PHY1_HSIC_SWRST                 (1 << 5)
 
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#define PHY1_STD_SWRST                  (1 << 4)
 
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#define PHY1_ALL_SWRST                  (1 << 3)
 
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#define PHY0_SWRST_MASK                 (0x7 << 0)
 
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#define PHY0_PHYLINK_SWRST              (1 << 2)
 
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#define PHY0_HLINK_SWRST                (1 << 1)
 
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#define PHY0_SWRST                      (1 << 0)
 
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#define EXYNOS4_PHY1CON                 EXYNOS4_HSOTG_PHYREG(0x34)
 
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#define FPENABLEN                       (1 << 0)
 
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#endif /* __PLAT_S5P_REGS_USB_PHY_H */