2
* Copyright (c) 2010 Broadcom Corporation
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <proto/802.11.h>
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#include "wlc_types.h"
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#include "wlc_phy_shim.h"
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#include "phy/wlc_phy_hal.h"
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#include "wlc_channel.h"
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#include "wl_export.h"
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#include "wlc_antsel.h"
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#include "pcie_core.h"
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#include "wlc_alloc.h"
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#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
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#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
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#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
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#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
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#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
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#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
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#ifndef BMAC_DUP_TO_REMOVE
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#define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
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#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
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#endif /* BMAC_DUP_TO_REMOVE */
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#define DMAREG(wlc_hw, direction, fifonum) \
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((direction == DMA_TX) ? \
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(void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
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(void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
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* The following table lists the buffer memory allocated to xmt fifos in HW.
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* the size is in units of 256bytes(one block), total size is HW dependent
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* ucode has default fifo partition, sw can overwrite if necessary
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* This is documented in twiki under the topic UcodeTxFifo. Please ensure
87
* the twiki is updated before making changes.
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#define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
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static u16 xmtfifo_sz[][NFIFO] = {
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{20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
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{9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
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{20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
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{20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
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{9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
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static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
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static void wlc_coreinit(struct wlc_info *wlc);
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/* used by wlc_wakeucode_init() */
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static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
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const struct d11init *inits);
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static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
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static void wlc_ucode_download(struct wlc_hw_info *wlc);
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static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
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/* used by wlc_dpc() */
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static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
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static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
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static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
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/* used by wlc_down() */
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static void wlc_flushqueues(struct wlc_info *wlc);
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static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
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static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
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static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
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static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
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static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
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static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
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/* Low Level Prototypes */
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static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
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static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
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static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
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static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
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static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
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static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
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static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
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static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
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static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
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static bool wlc_validboardtype(struct wlc_hw_info *wlc);
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static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
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static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
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static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
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static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
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static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
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static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
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static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
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static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
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static u32 wlc_wlintrsoff(struct wlc_info *wlc);
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static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
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static void wlc_gpio_init(struct wlc_info *wlc);
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static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
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static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
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static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
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static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
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static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
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chanspec_t chanspec);
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static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
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static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
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static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
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/* === Low Level functions === */
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void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
170
wlc_hw->shortslot = shortslot;
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if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
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wlc_suspend_mac_and_wait(wlc_hw->wlc);
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wlc_bmac_update_slot_timing(wlc_hw, shortslot);
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wlc_enable_mac(wlc_hw->wlc);
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* Update the slot timing for standard 11b/g (20us slots)
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* or shortslot 11g (9us slots)
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* The PSM needs to be suspended for this call.
184
static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
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/* 11g short slot: 11a timing */
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W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
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wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
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/* 11g long slot: 11b timing */
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W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
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wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
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static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
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struct wiphy *wiphy = wlc_hw->wlc->wiphy;
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/* init microcode host flags */
207
wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
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/* do band-specific ucode IHR, SHM, and SCR inits */
210
if (D11REV_IS(wlc_hw->corerev, 23)) {
211
if (WLCISNPHY(wlc_hw->band)) {
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wlc_write_inits(wlc_hw, d11n0bsinitvals16);
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wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
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" %d\n", __func__, wlc_hw->unit,
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if (D11REV_IS(wlc_hw->corerev, 24)) {
220
if (WLCISLCNPHY(wlc_hw->band)) {
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wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
223
wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
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" core rev %d\n", __func__,
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wlc_hw->unit, wlc_hw->corerev);
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wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
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__func__, wlc_hw->unit, wlc_hw->corerev);
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/* switch to new band but leave it inactive */
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static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
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struct wlc_hw_info *wlc_hw = wlc->hw;
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BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
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WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
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/* disable interrupts */
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macintmask = wl_intrsoff(wlc->wl);
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wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
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wlc_bmac_core_phy_clk(wlc_hw, OFF);
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wlc_setxband(wlc_hw, bandunit);
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/* Process received frames */
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* Return true if more frames need to be processed. false otherwise.
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* Param 'bound' indicates max. # frames to process before break out.
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wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
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struct sk_buff *head = NULL;
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struct sk_buff *tail = NULL;
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uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
269
wlc_d11rxhdr_t *wlc_rxhdr = NULL;
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BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
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/* gather received frames */
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while ((p = dma_rx(wlc_hw->di[fifo]))) {
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/* !give others some time to run! */
283
if (++n >= bound_limit)
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/* post more rbufs */
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dma_rxfill(wlc_hw->di[fifo]);
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/* process each frame */
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while ((p = head) != NULL) {
295
wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
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/* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
298
wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
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wlc_recv(wlc_hw->wlc, p);
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return n >= bound_limit;
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/* second-level interrupt processing
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* Return true if another dpc needs to be re-scheduled. false otherwise.
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* Param 'bounded' indicates if applicable loops should be bounded.
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bool wlc_dpc(struct wlc_info *wlc, bool bounded)
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struct wlc_hw_info *wlc_hw = wlc->hw;
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d11regs_t *regs = wlc_hw->regs;
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struct wiphy *wiphy = wlc->wiphy;
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if (DEVICEREMOVED(wlc)) {
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wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
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/* grab and clear the saved software intstatus bits */
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macintstatus = wlc->macintstatus;
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wlc->macintstatus = 0;
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BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
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wlc_hw->unit, macintstatus);
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WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
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/* BCN template is available */
335
/* ZZZ: Use AP_ACTIVE ? */
336
if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
337
&& (macintstatus & MI_BCNTPL)) {
338
wlc_update_beacon(wlc);
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/* PMQ entry addition */
342
if (macintstatus & MI_PMQ) {
346
if (macintstatus & MI_TFS) {
347
if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
348
wlc->macintstatus |= MI_TFS;
350
wiphy_err(wiphy, "MI_TFS: fatal\n");
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if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
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/* ATIM window end */
359
if (macintstatus & MI_ATIMWINEND) {
360
BCMMSG(wlc->wiphy, "end of ATIM window\n");
361
OR_REG(®s->maccommand, wlc->qvalid);
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/* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
366
if (macintstatus & MI_DMAINT) {
367
if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
368
wlc->macintstatus |= MI_DMAINT;
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/* TX FIFO suspend/flush completion */
373
if (macintstatus & MI_TXSTOP) {
374
if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
375
/* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
379
/* noise sample collected */
380
if (macintstatus & MI_BG_NOISE) {
381
wlc_phy_noise_sample_intr(wlc_hw->band->pi);
384
if (macintstatus & MI_GP0) {
385
wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
386
"(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
388
printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
389
__func__, wlc_hw->sih->chip,
390
wlc_hw->sih->chiprev);
395
/* gptimer timeout */
396
if (macintstatus & MI_TO) {
397
W_REG(®s->gptimer, 0);
400
if (macintstatus & MI_RFDISABLE) {
401
BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
402
" RF Disable Input\n", wlc_hw->unit);
403
wl_rfkill_set_hw_state(wlc->wl);
406
/* send any enq'd tx packets. Just makes sure to jump start tx */
407
if (!pktq_empty(&wlc->pkt_queue->q))
410
/* it isn't done and needs to be resched if macintstatus is non-zero */
411
return wlc->macintstatus != 0;
415
return wlc->macintstatus != 0;
418
/* common low-level watchdog code */
419
void wlc_bmac_watchdog(void *arg)
421
struct wlc_info *wlc = (struct wlc_info *) arg;
422
struct wlc_hw_info *wlc_hw = wlc->hw;
424
BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
429
/* increment second count */
432
/* Check for FIFO error interrupts */
433
wlc_bmac_fifoerrors(wlc_hw);
435
/* make sure RX dma has buffers */
436
dma_rxfill(wlc->hw->di[RX_FIFO]);
438
wlc_phy_watchdog(wlc_hw->band->pi);
442
wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
443
bool mute, struct txpwr_limits *txpwr)
447
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
449
wlc_hw->chanspec = chanspec;
451
/* Switch bands if necessary */
452
if (NBANDS_HW(wlc_hw) > 1) {
453
bandunit = CHSPEC_WLCBANDUNIT(chanspec);
454
if (wlc_hw->band->bandunit != bandunit) {
455
/* wlc_bmac_setband disables other bandunit,
456
* use light band switch if not up yet
459
wlc_phy_chanspec_radio_set(wlc_hw->
460
bandstate[bandunit]->
462
wlc_bmac_setband(wlc_hw, bandunit, chanspec);
464
wlc_setxband(wlc_hw, bandunit);
469
wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
473
wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
475
wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
477
wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
478
wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
480
/* Update muting of the channel */
481
wlc_bmac_mute(wlc_hw, mute, 0);
485
int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
487
state->machwcap = wlc_hw->machwcap;
492
static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
496
/* ucode host flag 2 needed for pio mode, independent of band and fifo */
498
struct wlc_hw_info *wlc_hw = wlc->hw;
499
uint unit = wlc_hw->unit;
500
wlc_tunables_t *tune = wlc->pub->tunables;
501
struct wiphy *wiphy = wlc->wiphy;
503
/* name and offsets for dma_attach */
504
snprintf(name, sizeof(name), "wl%d", unit);
506
if (wlc_hw->di[0] == 0) { /* Init FIFOs */
508
int dma_attach_err = 0;
509
/* Find out the DMA addressing capability and let OS know
510
* All the channels within one DMA core have 'common-minimum' same
514
dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
516
if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
517
wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
518
"resources failed\n", unit);
524
* TX: TX_AC_BK_FIFO (TX AC Background data packets)
525
* RX: RX_FIFO (RX data packets)
527
wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
528
(wme ? DMAREG(wlc_hw, DMA_TX, 0) :
529
NULL), DMAREG(wlc_hw, DMA_RX, 0),
530
(wme ? tune->ntxd : 0), tune->nrxd,
531
tune->rxbufsz, -1, tune->nrxbufpost,
532
WL_HWRXOFF, &wl_msg_level);
533
dma_attach_err |= (NULL == wlc_hw->di[0]);
537
* TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
538
* (legacy) TX_DATA_FIFO (TX data packets)
541
wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
542
DMAREG(wlc_hw, DMA_TX, 1), NULL,
543
tune->ntxd, 0, 0, -1, 0, 0,
545
dma_attach_err |= (NULL == wlc_hw->di[1]);
549
* TX: TX_AC_VI_FIFO (TX AC Video data packets)
552
wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
553
DMAREG(wlc_hw, DMA_TX, 2), NULL,
554
tune->ntxd, 0, 0, -1, 0, 0,
556
dma_attach_err |= (NULL == wlc_hw->di[2]);
559
* TX: TX_AC_VO_FIFO (TX AC Voice data packets)
560
* (legacy) TX_CTL_FIFO (TX control & mgmt packets)
562
wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
563
DMAREG(wlc_hw, DMA_TX, 3),
564
NULL, tune->ntxd, 0, 0, -1,
565
0, 0, &wl_msg_level);
566
dma_attach_err |= (NULL == wlc_hw->di[3]);
567
/* Cleaner to leave this as if with AP defined */
569
if (dma_attach_err) {
570
wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
575
/* get pointer to dma engine tx flow control variable */
576
for (i = 0; i < NFIFO; i++)
579
(uint *) dma_getvar(wlc_hw->di[i],
583
/* initial ucode host flags */
584
wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
589
static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
593
for (j = 0; j < NFIFO; j++) {
595
dma_detach(wlc_hw->di[j]);
596
wlc_hw->di[j] = NULL;
602
* run backplane attach, init nvram
604
* initialize software state for each core and band
605
* put the whole chip in reset(driver down state), no clock
607
int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
608
bool piomode, void *regsva, uint bustype, void *btparam)
610
struct wlc_hw_info *wlc_hw;
612
char *macaddr = NULL;
617
shared_phy_params_t sha_params;
618
struct wiphy *wiphy = wlc->wiphy;
620
BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
628
wlc_hw->band = wlc_hw->bandstate[0];
629
wlc_hw->_piomode = piomode;
631
/* populate struct wlc_hw_info with default values */
632
wlc_bmac_info_init(wlc_hw);
635
* Do the hardware portion of the attach.
636
* Also initialize software state that depends on the particular hardware
639
wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
640
&wlc_hw->vars, &wlc_hw->vars_size);
641
if (wlc_hw->sih == NULL) {
642
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
650
* Get vendid/devid nvram overwrites, which could be different
651
* than those the BIOS recognizes for devices on PCMCIA_BUS,
652
* SDIO_BUS, and SROMless devices on PCI_BUS.
655
bustype = BCMBUSTYPE;
657
if (bustype != SI_BUS) {
660
var = getvar(vars, "vendid");
662
vendor = (u16) simple_strtoul(var, NULL, 0);
663
wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
666
var = getvar(vars, "devid");
668
u16 devid = (u16) simple_strtoul(var, NULL, 0);
669
if (devid != 0xffff) {
671
wiphy_err(wiphy, "Overriding device id = 0x%x"
676
/* verify again the device is supported */
677
if (!wlc_chipmatch(vendor, device)) {
678
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
679
"vendor/device (0x%x/0x%x)\n",
680
unit, vendor, device);
686
wlc_hw->vendorid = vendor;
687
wlc_hw->deviceid = device;
689
/* set bar0 window to point at D11 core */
690
wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
691
wlc_hw->corerev = ai_corerev(wlc_hw->sih);
695
wlc->regs = wlc_hw->regs;
697
/* validate chip, chiprev and corerev */
698
if (!wlc_isgoodchip(wlc_hw)) {
703
/* initialize power control registers */
704
ai_clkctl_init(wlc_hw->sih);
706
/* request fastclock and force fastclock for the rest of attach
707
* bring the d11 core out of reset.
708
* For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
709
* But it will be called again inside wlc_corereset, after d11 is out of reset.
711
wlc_clkctl_clk(wlc_hw, CLK_FAST);
712
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
714
if (!wlc_bmac_validate_chip_access(wlc_hw)) {
715
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
721
/* get the board rev, used just below */
722
j = getintvar(vars, "boardrev");
723
/* promote srom boardrev of 0xFF to 1 */
724
if (j == BOARDREV_PROMOTABLE)
725
j = BOARDREV_PROMOTED;
726
wlc_hw->boardrev = (u16) j;
727
if (!wlc_validboardtype(wlc_hw)) {
728
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
729
"board type (0x%x)" " or revision level (0x%x)\n",
730
unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
734
wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
735
wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
736
wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
738
if (wlc_hw->boardflags & BFL_NOPLLDOWN)
739
wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
741
if ((wlc_hw->sih->bustype == PCI_BUS)
742
&& (ai_pci_war16165(wlc_hw->sih)))
743
wlc->war16165 = true;
745
/* check device id(srom, nvram etc.) to set bands */
746
if (wlc_hw->deviceid == BCM43224_D11N_ID) {
747
/* Dualband boards */
752
if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
755
/* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
756
* init of these values
758
wlc->vendorid = wlc_hw->vendorid;
759
wlc->deviceid = wlc_hw->deviceid;
760
wlc->pub->sih = wlc_hw->sih;
761
wlc->pub->corerev = wlc_hw->corerev;
762
wlc->pub->sromrev = wlc_hw->sromrev;
763
wlc->pub->boardrev = wlc_hw->boardrev;
764
wlc->pub->boardflags = wlc_hw->boardflags;
765
wlc->pub->boardflags2 = wlc_hw->boardflags2;
766
wlc->pub->_nbands = wlc_hw->_nbands;
768
wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
770
if (wlc_hw->physhim == NULL) {
771
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
777
/* pass all the parameters to wlc_phy_shared_attach in one struct */
778
sha_params.sih = wlc_hw->sih;
779
sha_params.physhim = wlc_hw->physhim;
780
sha_params.unit = unit;
781
sha_params.corerev = wlc_hw->corerev;
782
sha_params.vars = vars;
783
sha_params.vid = wlc_hw->vendorid;
784
sha_params.did = wlc_hw->deviceid;
785
sha_params.chip = wlc_hw->sih->chip;
786
sha_params.chiprev = wlc_hw->sih->chiprev;
787
sha_params.chippkg = wlc_hw->sih->chippkg;
788
sha_params.sromrev = wlc_hw->sromrev;
789
sha_params.boardtype = wlc_hw->sih->boardtype;
790
sha_params.boardrev = wlc_hw->boardrev;
791
sha_params.boardvendor = wlc_hw->sih->boardvendor;
792
sha_params.boardflags = wlc_hw->boardflags;
793
sha_params.boardflags2 = wlc_hw->boardflags2;
794
sha_params.bustype = wlc_hw->sih->bustype;
795
sha_params.buscorerev = wlc_hw->sih->buscorerev;
797
/* alloc and save pointer to shared phy state area */
798
wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
799
if (!wlc_hw->phy_sh) {
804
/* initialize software state for each core and band */
805
for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
807
* band0 is always 2.4Ghz
808
* band1, if present, is 5Ghz
811
/* So if this is a single band 11a card, use band 1 */
812
if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
815
wlc_setxband(wlc_hw, j);
817
wlc_hw->band->bandunit = j;
818
wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
819
wlc->band->bandunit = j;
820
wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
821
wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
823
wlc_hw->machwcap = R_REG(®s->machwcap);
824
wlc_hw->machwcap_backup = wlc_hw->machwcap;
826
/* init tx fifo size */
828
xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
830
/* Get a phy for this band */
831
wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
832
(void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
834
if (wlc_hw->band->pi == NULL) {
835
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
836
"attach failed\n", unit);
841
wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
843
wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
844
&wlc_hw->band->phyrev,
845
&wlc_hw->band->radioid,
846
&wlc_hw->band->radiorev);
847
wlc_hw->band->abgphy_encore =
848
wlc_phy_get_encore(wlc_hw->band->pi);
849
wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
850
wlc_hw->band->core_flags =
851
wlc_phy_get_coreflags(wlc_hw->band->pi);
853
/* verify good phy_type & supported phy revision */
854
if (WLCISNPHY(wlc_hw->band)) {
855
if (NCONF_HAS(wlc_hw->band->phyrev))
859
} else if (WLCISLCNPHY(wlc_hw->band)) {
860
if (LCNCONF_HAS(wlc_hw->band->phyrev))
866
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
867
"phy type/rev (%d/%d)\n", unit,
868
wlc_hw->band->phytype, wlc_hw->band->phyrev);
874
/* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
875
* high level attach. However we can not make that change until all low level access
876
* is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
877
* wlc_hw->band->pi as well for incremental update of low level fns, and cut over
878
* low only init when all fns updated.
880
wlc->band->pi = wlc_hw->band->pi;
881
wlc->band->phytype = wlc_hw->band->phytype;
882
wlc->band->phyrev = wlc_hw->band->phyrev;
883
wlc->band->radioid = wlc_hw->band->radioid;
884
wlc->band->radiorev = wlc_hw->band->radiorev;
886
/* default contention windows size limits */
887
wlc_hw->band->CWmin = APHY_CWMIN;
888
wlc_hw->band->CWmax = PHY_CWMAX;
890
if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
896
/* disable core to match driver "down" state */
897
wlc_coredisable(wlc_hw);
899
/* Match driver "down" state */
900
if (wlc_hw->sih->bustype == PCI_BUS)
901
ai_pci_down(wlc_hw->sih);
903
/* register sb interrupt callback functions */
904
ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
905
(void *)wlc_wlintrsrestore, NULL, wlc);
907
/* turn off pll and xtal to match driver "down" state */
908
wlc_bmac_xtal(wlc_hw, OFF);
910
/* *********************************************************************
911
* The hardware is in the DOWN state at this point. D11 core
912
* or cores are in reset with clocks off, and the board PLLs
913
* are off if possible.
915
* Beyond this point, wlc->sbclk == false and chip registers
916
* should not be touched.
917
*********************************************************************
920
/* init etheraddr state variables */
921
macaddr = wlc_get_macaddr(wlc_hw);
922
if (macaddr == NULL) {
923
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
928
bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
929
if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
930
is_zero_ether_addr(wlc_hw->etheraddr)) {
931
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
938
"deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
939
wlc_hw->deviceid, wlc_hw->_nbands,
940
wlc_hw->sih->boardtype, macaddr);
945
wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
951
* Initialize wlc_info default values ...
952
* may get overrides later in this function
953
* BMAC_NOTES, move low out and resolve the dangling ones
955
static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
957
struct wlc_info *wlc = wlc_hw->wlc;
959
/* set default sw macintmask value */
960
wlc->defmacintmask = DEF_MACINTMASK;
962
/* various 802.11g modes */
963
wlc_hw->shortslot = false;
965
wlc_hw->SFBL = RETRY_SHORT_FB;
966
wlc_hw->LFBL = RETRY_LONG_FB;
968
/* default mac retry limits */
969
wlc_hw->SRL = RETRY_SHORT_DEF;
970
wlc_hw->LRL = RETRY_LONG_DEF;
971
wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
977
int wlc_bmac_detach(struct wlc_info *wlc)
980
struct wlc_hwband *band;
981
struct wlc_hw_info *wlc_hw = wlc->hw;
987
/* detach interrupt sync mechanism since interrupt is disabled and per-port
988
* interrupt object may has been freed. this must be done before sb core switch
990
ai_deregister_intr_callback(wlc_hw->sih);
992
if (wlc_hw->sih->bustype == PCI_BUS)
993
ai_pci_sleep(wlc_hw->sih);
996
wlc_bmac_detach_dmapio(wlc_hw);
999
for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1001
/* Detach this band's phy */
1002
wlc_phy_detach(band->pi);
1005
band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1008
/* Free shared phy state */
1009
wlc_phy_shared_detach(wlc_hw->phy_sh);
1011
wlc_phy_shim_detach(wlc_hw->physhim);
1014
kfree(wlc_hw->vars);
1015
wlc_hw->vars = NULL;
1018
ai_detach(wlc_hw->sih);
1026
void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1028
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1030
/* reset the core */
1031
if (!DEVICEREMOVED(wlc_hw->wlc))
1032
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1034
/* purge the dma rings */
1035
wlc_flushqueues(wlc_hw->wlc);
1037
wlc_reset_bmac_done(wlc_hw->wlc);
1041
wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1045
struct wlc_info *wlc = wlc_hw->wlc;
1047
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1049
/* request FAST clock if not on */
1050
fastclk = wlc_hw->forcefastclk;
1052
wlc_clkctl_clk(wlc_hw, CLK_FAST);
1054
/* disable interrupts */
1055
macintmask = wl_intrsoff(wlc->wl);
1057
/* set up the specified band and chanspec */
1058
wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1059
wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1061
/* do one-time phy inits and calibration */
1062
wlc_phy_cal_init(wlc_hw->band->pi);
1064
/* core-specific initialization */
1067
/* suspend the tx fifos and mute the phy for preism cac time */
1069
wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1071
/* band-specific inits */
1072
wlc_bmac_bsinit(wlc, chanspec);
1074
/* restore macintmask */
1075
wl_intrsrestore(wlc->wl, macintmask);
1077
/* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1078
* and wlc_enable_mac() will clear this override bit.
1080
mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1083
* initialize mac_suspend_depth to 1 to match ucode initial suspended state
1085
wlc_hw->mac_suspend_depth = 1;
1087
/* restore the clk */
1089
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1092
int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1096
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1099
* Enable pll and xtal, initialize the power control registers,
1100
* and force fastclock for the remainder of wlc_up().
1102
wlc_bmac_xtal(wlc_hw, ON);
1103
ai_clkctl_init(wlc_hw->sih);
1104
wlc_clkctl_clk(wlc_hw, CLK_FAST);
1107
* Configure pci/pcmcia here instead of in wlc_attach()
1108
* to allow mfg hotswap: down, hotswap (chip power cycle), up.
1110
coremask = (1 << wlc_hw->wlc->core->coreidx);
1112
if (wlc_hw->sih->bustype == PCI_BUS)
1113
ai_pci_setup(wlc_hw->sih, coremask);
1116
* Need to read the hwradio status here to cover the case where the system
1117
* is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1119
if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1120
/* put SB PCI in down state again */
1121
if (wlc_hw->sih->bustype == PCI_BUS)
1122
ai_pci_down(wlc_hw->sih);
1123
wlc_bmac_xtal(wlc_hw, OFF);
1127
if (wlc_hw->sih->bustype == PCI_BUS)
1128
ai_pci_up(wlc_hw->sih);
1130
/* reset the d11 core */
1131
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1136
int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1138
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1141
wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1143
/* FULLY enable dynamic power control and d11 core interrupt */
1144
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1145
wl_intrson(wlc_hw->wlc->wl);
1149
int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1154
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1159
dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1161
/* disable interrupts */
1163
wlc_hw->wlc->macintmask = 0;
1165
/* now disable interrupts */
1166
wl_intrsoff(wlc_hw->wlc->wl);
1168
/* ensure we're running on the pll clock again */
1169
wlc_clkctl_clk(wlc_hw, CLK_FAST);
1171
/* down phy at the last of this stage */
1172
callbacks += wlc_phy_down(wlc_hw->band->pi);
1177
int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1182
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1188
wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1190
dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1193
wlc_hw->sbclk = false;
1194
wlc_hw->clk = false;
1195
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1197
/* reclaim any posted packets */
1198
wlc_flushqueues(wlc_hw->wlc);
1201
/* Reset and disable the core */
1202
if (ai_iscoreup(wlc_hw->sih)) {
1203
if (R_REG(&wlc_hw->regs->maccontrol) &
1205
wlc_suspend_mac_and_wait(wlc_hw->wlc);
1206
callbacks += wl_reset(wlc_hw->wlc->wl);
1207
wlc_coredisable(wlc_hw);
1210
/* turn off primary xtal and pll */
1211
if (!wlc_hw->noreset) {
1212
if (wlc_hw->sih->bustype == PCI_BUS)
1213
ai_pci_down(wlc_hw->sih);
1214
wlc_bmac_xtal(wlc_hw, OFF);
1221
void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1223
/* delay before first read of ucode state */
1226
/* wait until ucode is no longer asleep */
1227
SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1228
DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1231
void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1233
memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1236
static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1238
return wlc_hw->band->bandtype;
1241
/* control chip clock to save power, enable dynamic clock or force fast clock */
1242
static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1244
if (PMUCTL_ENAB(wlc_hw->sih)) {
1245
/* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1246
* but mac core will still run on ALP(not HT) when it enters powersave mode,
1247
* which means the FCA bit may not be set.
1248
* should wakeup mac if driver wants it to run on HT.
1252
if (mode == CLK_FAST) {
1253
OR_REG(&wlc_hw->regs->clk_ctl_st,
1260
clk_ctl_st) & CCS_HTAVAIL) == 0),
1261
PMU_MAX_TRANSITION_DLY);
1264
clk_ctl_st) & CCS_HTAVAIL));
1266
if ((wlc_hw->sih->pmurev == 0) &&
1269
clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1272
clk_ctl_st) & CCS_HTAVAIL)
1274
PMU_MAX_TRANSITION_DLY);
1275
AND_REG(&wlc_hw->regs->clk_ctl_st,
1279
wlc_hw->forcefastclk = (mode == CLK_FAST);
1282
/* old chips w/o PMU, force HT through cc,
1283
* then use FCA to verify mac is running fast clock
1286
wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1288
/* check fast clock is available (if core is not in reset) */
1289
if (wlc_hw->forcefastclk && wlc_hw->clk)
1290
WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1293
/* keep the ucode wake bit on if forcefastclk is on
1294
* since we do not want ucode to put us back to slow clock
1295
* when it dozes for PM mode.
1296
* Code below matches the wake override bit with current forcefastclk state
1297
* Only setting bit in wake_override instead of waking ucode immediately
1298
* since old code (wlc.c 1.4499) had this behavior. Older code set
1299
* wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1300
* (protected by an up check) was executed just below.
1302
if (wlc_hw->forcefastclk)
1303
mboolset(wlc_hw->wake_override,
1304
WLC_WAKE_OVERRIDE_FORCEFAST);
1306
mboolclr(wlc_hw->wake_override,
1307
WLC_WAKE_OVERRIDE_FORCEFAST);
1311
/* set initial host flags value */
1313
wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1315
struct wlc_hw_info *wlc_hw = wlc->hw;
1317
memset(mhfs, 0, MHFMAX * sizeof(u16));
1319
mhfs[MHF2] |= mhf2_init;
1321
/* prohibit use of slowclock on multifunction boards */
1322
if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1323
mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1325
if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1326
mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1327
mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1331
/* set or clear ucode host flag bits
1332
* it has an optimization for no-change write
1333
* it only writes through shared memory when the core has clock;
1334
* pre-CLK changes should use wlc_write_mhf to get around the optimization
1337
* bands values are: WLC_BAND_AUTO <--- Current band only
1338
* WLC_BAND_5G <--- 5G band only
1339
* WLC_BAND_2G <--- 2G band only
1340
* WLC_BAND_ALL <--- All bands
1343
wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1347
u16 addr[MHFMAX] = {
1348
M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1351
struct wlc_hwband *band;
1353
if ((val & ~mask) || idx >= MHFMAX)
1354
return; /* error condition */
1357
/* Current band only or all bands,
1358
* then set the band to current band
1362
band = wlc_hw->band;
1365
band = wlc_hw->bandstate[BAND_5G_INDEX];
1368
band = wlc_hw->bandstate[BAND_2G_INDEX];
1371
band = NULL; /* error condition */
1375
save = band->mhfs[idx];
1376
band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1378
/* optimization: only write through if changed, and
1379
* changed band is the current band
1381
if (wlc_hw->clk && (band->mhfs[idx] != save)
1382
&& (band == wlc_hw->band))
1383
wlc_bmac_write_shm(wlc_hw, addr[idx],
1384
(u16) band->mhfs[idx]);
1387
if (bands == WLC_BAND_ALL) {
1388
wlc_hw->bandstate[0]->mhfs[idx] =
1389
(wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1390
wlc_hw->bandstate[1]->mhfs[idx] =
1391
(wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1395
u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1397
struct wlc_hwband *band;
1400
return 0; /* error condition */
1403
band = wlc_hw->band;
1406
band = wlc_hw->bandstate[BAND_5G_INDEX];
1409
band = wlc_hw->bandstate[BAND_2G_INDEX];
1412
band = NULL; /* error condition */
1418
return band->mhfs[idx];
1421
static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1425
M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1429
for (idx = 0; idx < MHFMAX; idx++) {
1430
wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1434
/* set the maccontrol register to desired reset state and
1435
* initialize the sw cache of the register
1437
static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1439
/* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1440
wlc_hw->maccontrol = 0;
1441
wlc_hw->suspended_fifos = 0;
1442
wlc_hw->wake_override = 0;
1443
wlc_hw->mute_override = 0;
1444
wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1447
/* set or clear maccontrol bits */
1448
void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1454
return; /* error condition */
1455
maccontrol = wlc_hw->maccontrol;
1456
new_maccontrol = (maccontrol & ~mask) | val;
1458
/* if the new maccontrol value is the same as the old, nothing to do */
1459
if (new_maccontrol == maccontrol)
1462
/* something changed, cache the new value */
1463
wlc_hw->maccontrol = new_maccontrol;
1465
/* write the new values with overrides applied */
1466
wlc_mctrl_write(wlc_hw);
1469
/* write the software state of maccontrol and overrides to the maccontrol register */
1470
static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1472
u32 maccontrol = wlc_hw->maccontrol;
1474
/* OR in the wake bit if overridden */
1475
if (wlc_hw->wake_override)
1476
maccontrol |= MCTL_WAKE;
1478
/* set AP and INFRA bits for mute if needed */
1479
if (wlc_hw->mute_override) {
1480
maccontrol &= ~(MCTL_AP);
1481
maccontrol |= MCTL_INFRA;
1484
W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1487
void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1489
if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1490
mboolset(wlc_hw->wake_override, override_bit);
1494
mboolset(wlc_hw->wake_override, override_bit);
1496
wlc_mctrl_write(wlc_hw);
1497
wlc_bmac_wait_for_wake(wlc_hw);
1502
void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1504
mboolclr(wlc_hw->wake_override, override_bit);
1506
if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1509
wlc_mctrl_write(wlc_hw);
1514
/* When driver needs ucode to stop beaconing, it has to make sure that
1515
* MCTL_AP is clear and MCTL_INFRA is set
1516
* Mode MCTL_AP MCTL_INFRA
1518
* STA 0 1 <--- This will ensure no beacons
1521
static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1523
wlc_hw->mute_override = 1;
1525
/* if maccontrol already has AP == 0 and INFRA == 1 without this
1526
* override, then there is no change to write
1528
if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1531
wlc_mctrl_write(wlc_hw);
1536
/* Clear the override on AP and INFRA bits */
1537
static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1539
if (wlc_hw->mute_override == 0)
1542
wlc_hw->mute_override = 0;
1544
/* if maccontrol already has AP == 0 and INFRA == 1 without this
1545
* override, then there is no change to write
1547
if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1550
wlc_mctrl_write(wlc_hw);
1554
* Write a MAC address to the given match reg offset in the RXE match engine.
1557
wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1565
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
1568
regs = wlc_hw->regs;
1569
mac_l = addr[0] | (addr[1] << 8);
1570
mac_m = addr[2] | (addr[3] << 8);
1571
mac_h = addr[4] | (addr[5] << 8);
1573
/* enter the MAC addr into the RXE match registers */
1574
W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1575
W_REG(®s->rcm_mat_data, mac_l);
1576
W_REG(®s->rcm_mat_data, mac_m);
1577
W_REG(®s->rcm_mat_data, mac_h);
1582
wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1588
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1590
regs = wlc_hw->regs;
1591
W_REG(®s->tplatewrptr, offset);
1593
/* if MCTL_BIGEND bit set in mac control register,
1594
* the chip swaps data in fifo, as well as data in
1597
be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
1600
memcpy(&word, buf, sizeof(u32));
1603
word = cpu_to_be32(word);
1605
word = cpu_to_le32(word);
1607
W_REG(®s->tplatewrdata, word);
1609
buf = (u8 *) buf + sizeof(u32);
1614
void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1616
wlc_hw->band->CWmin = newmin;
1618
W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1619
(void)R_REG(&wlc_hw->regs->objaddr);
1620
W_REG(&wlc_hw->regs->objdata, newmin);
1623
void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1625
wlc_hw->band->CWmax = newmax;
1627
W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1628
(void)R_REG(&wlc_hw->regs->objaddr);
1629
W_REG(&wlc_hw->regs->objdata, newmax);
1632
void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1636
/* request FAST clock if not on */
1637
fastclk = wlc_hw->forcefastclk;
1639
wlc_clkctl_clk(wlc_hw, CLK_FAST);
1641
wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1643
wlc_bmac_phy_reset(wlc_hw);
1644
wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1646
/* restore the clk */
1648
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1652
wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1654
d11regs_t *regs = wlc_hw->regs;
1656
wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1658
/* write beacon length to SCR */
1659
wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1660
/* mark beacon0 valid */
1661
OR_REG(®s->maccommand, MCMD_BCN0VLD);
1665
wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1667
d11regs_t *regs = wlc_hw->regs;
1669
wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1671
/* write beacon length to SCR */
1672
wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1673
/* mark beacon1 valid */
1674
OR_REG(®s->maccommand, MCMD_BCN1VLD);
1677
/* mac is assumed to be suspended at this point */
1679
wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1682
d11regs_t *regs = wlc_hw->regs;
1685
wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1686
wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1689
if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
1690
wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1693
(R_REG(®s->maccommand) & MCMD_BCN1VLD))
1694
wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1698
static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1701
struct wlc_info *wlc = wlc_hw->wlc;
1702
/* update SYNTHPU_DLY */
1704
if (WLCISLCNPHY(wlc->band)) {
1705
v = SYNTHPU_DLY_LPPHY_US;
1706
} else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1707
v = SYNTHPU_DLY_NPHY_US;
1709
v = SYNTHPU_DLY_BPHY_US;
1712
wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1715
/* band-specific init */
1717
WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1719
struct wlc_hw_info *wlc_hw = wlc->hw;
1721
BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1722
wlc_hw->band->bandunit);
1724
wlc_ucode_bsinit(wlc_hw);
1726
wlc_phy_init(wlc_hw->band->pi, chanspec);
1728
wlc_ucode_txant_set(wlc_hw);
1730
/* cwmin is band-specific, update hardware with value for current band */
1731
wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1732
wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1734
wlc_bmac_update_slot_timing(wlc_hw,
1735
BAND_5G(wlc_hw->band->
1736
bandtype) ? true : wlc_hw->
1739
/* write phytype and phyvers */
1740
wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1741
wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1743
/* initialize the txphyctl1 rate table since shmem is shared between bands */
1744
wlc_upd_ofdm_pctl1_table(wlc_hw);
1746
wlc_bmac_upd_synthpu(wlc_hw);
1749
static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1751
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1753
wlc_hw->phyclk = clk;
1755
if (OFF == clk) { /* clear gmode bit, put phy into reset */
1757
ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1758
(SICF_PRST | SICF_FGC));
1760
ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1763
} else { /* take phy out of reset */
1765
ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1767
ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1773
/* Perform a soft reset of the PHY PLL */
1774
void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1776
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1778
ai_corereg(wlc_hw->sih, SI_CC_IDX,
1779
offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1781
ai_corereg(wlc_hw->sih, SI_CC_IDX,
1782
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1784
ai_corereg(wlc_hw->sih, SI_CC_IDX,
1785
offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1787
ai_corereg(wlc_hw->sih, SI_CC_IDX,
1788
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1792
/* light way to turn on phy clock without reset for NPHY only
1793
* refer to wlc_bmac_core_phy_clk for full version
1795
void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1797
/* support(necessary for NPHY and HYPHY) only */
1798
if (!WLCISNPHY(wlc_hw->band))
1802
ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1804
ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1808
void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1811
ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1813
ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1816
void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1818
wlc_phy_t *pih = wlc_hw->band->pi;
1820
bool phy_in_reset = false;
1822
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1827
phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1829
/* Specific reset sequence required for NPHY rev 3 and 4 */
1830
if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1831
NREV_LE(wlc_hw->band->phyrev, 4)) {
1832
/* Set the PHY bandwidth */
1833
ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1837
/* Perform a soft reset of the PHY PLL */
1838
wlc_bmac_core_phypll_reset(wlc_hw);
1841
ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1842
(SICF_PRST | SICF_PCLKE));
1843
phy_in_reset = true;
1846
ai_core_cflags(wlc_hw->sih,
1847
(SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1848
(SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1852
wlc_bmac_core_phy_clk(wlc_hw, ON);
1855
wlc_phy_anacore(pih, ON);
1858
/* switch to and initialize new band */
1860
WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1861
chanspec_t chanspec) {
1862
struct wlc_info *wlc = wlc_hw->wlc;
1865
/* Enable the d11 core before accessing it */
1866
if (!ai_iscoreup(wlc_hw->sih)) {
1867
ai_core_reset(wlc_hw->sih, 0, 0);
1868
wlc_mctrl_reset(wlc_hw);
1871
macintmask = wlc_setband_inact(wlc, bandunit);
1876
wlc_bmac_core_phy_clk(wlc_hw, ON);
1878
/* band-specific initializations */
1879
wlc_bmac_bsinit(wlc, chanspec);
1882
* If there are any pending software interrupt bits,
1883
* then replace these with a harmless nonzero value
1884
* so wlc_dpc() will re-enable interrupts when done.
1886
if (wlc->macintstatus)
1887
wlc->macintstatus = MI_DMAINT;
1889
/* restore macintmask */
1890
wl_intrsrestore(wlc->wl, macintmask);
1892
/* ucode should still be suspended.. */
1893
WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1896
/* low-level band switch utility routine */
1897
void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
1899
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1902
wlc_hw->band = wlc_hw->bandstate[bandunit];
1904
/* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1905
wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1907
/* set gmode core flag */
1908
if (wlc_hw->sbclk && !wlc_hw->noreset) {
1909
ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1910
((bandunit == 0) ? SICF_GMODE : 0));
1914
static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
1917
/* reject unsupported corerev */
1918
if (!VALID_COREREV(wlc_hw->corerev)) {
1919
wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1927
static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
1929
bool goodboard = true;
1930
uint boardrev = wlc_hw->boardrev;
1934
else if (boardrev > 0xff) {
1935
uint brt = (boardrev & 0xf000) >> 12;
1936
uint b0 = (boardrev & 0xf00) >> 8;
1937
uint b1 = (boardrev & 0xf0) >> 4;
1938
uint b2 = boardrev & 0xf;
1940
if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1945
if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1951
static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
1953
const char *varname = "macaddr";
1956
/* If macaddr exists, use it (Sromrev4, CIS, ...). */
1957
macaddr = getvar(wlc_hw->vars, varname);
1958
if (macaddr != NULL)
1961
if (NBANDS_HW(wlc_hw) > 1)
1962
varname = "et1macaddr";
1964
varname = "il0macaddr";
1966
macaddr = getvar(wlc_hw->vars, varname);
1967
if (macaddr == NULL) {
1968
wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1969
"getvar(%s) not found\n", wlc_hw->unit, varname);
1976
* Return true if radio is disabled, otherwise false.
1977
* hw radio disable signal is an external pin, users activate it asynchronously
1978
* this function could be called when driver is down and w/o clock
1979
* it operates on different registers depending on corerev and boardflag.
1981
bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
1984
u32 resetbits = 0, flags = 0;
1986
xtal = wlc_hw->sbclk;
1988
wlc_bmac_xtal(wlc_hw, ON);
1990
/* may need to take core out of reset first */
1994
* mac no longer enables phyclk automatically when driver
1995
* accesses phyreg throughput mac. This can be skipped since
1996
* only mac reg is accessed below
1998
flags |= SICF_PCLKE;
2000
/* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2001
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2002
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2003
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
2005
(d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2007
ai_core_reset(wlc_hw->sih, flags, resetbits);
2008
wlc_mctrl_reset(wlc_hw);
2011
v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2013
/* put core back into reset */
2015
ai_core_disable(wlc_hw->sih, 0);
2018
wlc_bmac_xtal(wlc_hw, OFF);
2023
/* Initialize just the hardware when coming out of POR or S3/S5 system states */
2024
void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2026
if (wlc_hw->wlc->pub->hw_up)
2029
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2032
* Enable pll and xtal, initialize the power control registers,
2033
* and force fastclock for the remainder of wlc_up().
2035
wlc_bmac_xtal(wlc_hw, ON);
2036
ai_clkctl_init(wlc_hw->sih);
2037
wlc_clkctl_clk(wlc_hw, CLK_FAST);
2039
if (wlc_hw->sih->bustype == PCI_BUS) {
2040
ai_pci_fixcfg(wlc_hw->sih);
2042
/* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2043
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2044
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2045
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
2047
(d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2051
/* Inform phy that a POR reset has occurred so it does a complete phy init */
2052
wlc_phy_por_inform(wlc_hw->band->pi);
2054
wlc_hw->ucode_loaded = false;
2055
wlc_hw->wlc->pub->hw_up = true;
2057
if ((wlc_hw->boardflags & BFL_FEM)
2058
&& (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2060
(wlc_hw->boardrev >= 0x1250
2061
&& (wlc_hw->boardflags & BFL_FEM_BT)))
2062
ai_epa_4313war(wlc_hw->sih);
2066
static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2068
struct hnddma_pub *di = wlc_hw->di[fifo];
2069
return dma_rxreset(di);
2073
* ensure fask clock during reset
2075
* reset d11(out of reset)
2076
* reset phy(out of reset)
2077
* clear software macintstatus for fresh new start
2078
* one testing hack wlc_hw->noreset will bypass the d11/phy reset
2080
void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2087
if (flags == WLC_USE_COREFLAGS)
2088
flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2090
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2092
regs = wlc_hw->regs;
2094
/* request FAST clock if not on */
2095
fastclk = wlc_hw->forcefastclk;
2097
wlc_clkctl_clk(wlc_hw, CLK_FAST);
2099
/* reset the dma engines except first time thru */
2100
if (ai_iscoreup(wlc_hw->sih)) {
2101
for (i = 0; i < NFIFO; i++)
2102
if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2103
wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2104
"dma_txreset[%d]: cannot stop dma\n",
2105
wlc_hw->unit, __func__, i);
2108
if ((wlc_hw->di[RX_FIFO])
2109
&& (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2110
wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2111
"[%d]: cannot stop dma\n",
2112
wlc_hw->unit, __func__, RX_FIFO);
2115
/* if noreset, just stop the psm and return */
2116
if (wlc_hw->noreset) {
2117
wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2118
wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2123
* mac no longer enables phyclk automatically when driver accesses
2124
* phyreg throughput mac, AND phy_reset is skipped at early stage when
2125
* band->pi is invalid. need to enable PHY CLK
2127
flags |= SICF_PCLKE;
2130
* In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2131
* is cleared by the core_reset. have to re-request it.
2132
* This adds some delay and we can optimize it by also requesting fastclk through
2133
* chipcommon during this period if necessary. But that has to work coordinate
2134
* with other driver like mips/arm since they may touch chipcommon as well.
2136
wlc_hw->clk = false;
2137
ai_core_reset(wlc_hw->sih, flags, resetbits);
2139
if (wlc_hw->band && wlc_hw->band->pi)
2140
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2142
wlc_mctrl_reset(wlc_hw);
2144
if (PMUCTL_ENAB(wlc_hw->sih))
2145
wlc_clkctl_clk(wlc_hw, CLK_FAST);
2147
wlc_bmac_phy_reset(wlc_hw);
2149
/* turn on PHY_PLL */
2150
wlc_bmac_core_phypll_ctl(wlc_hw, true);
2152
/* clear sw intstatus */
2153
wlc_hw->wlc->macintstatus = 0;
2155
/* restore the clk setting */
2157
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2160
/* txfifo sizes needs to be modified(increased) since the newer cores
2163
static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2165
d11regs_t *regs = wlc_hw->regs;
2167
u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2168
u16 txfifo_def, txfifo_def1;
2171
/* tx fifos start at TXFIFO_START_BLK from the Base address */
2172
txfifo_startblk = TXFIFO_START_BLK;
2174
/* sequence of operations: reset fifo, set fifo size, reset fifo */
2175
for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2177
txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2178
txfifo_def = (txfifo_startblk & 0xff) |
2179
(((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2180
txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2182
1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2184
TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2186
W_REG(®s->xmtfifocmd, txfifo_cmd);
2187
W_REG(®s->xmtfifodef, txfifo_def);
2188
W_REG(®s->xmtfifodef1, txfifo_def1);
2190
W_REG(®s->xmtfifocmd, txfifo_cmd);
2192
txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2195
* need to propagate to shm location to be in sync since ucode/hw won't
2198
wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2199
wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2200
wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2201
wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2202
wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2203
((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2204
xmtfifo_sz[TX_AC_BK_FIFO]));
2205
wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2206
((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2207
xmtfifo_sz[TX_BCMC_FIFO]));
2212
* download ucode/PCM
2213
* let ucode run to suspended
2214
* download ucode inits
2215
* config other core registers
2218
static void wlc_coreinit(struct wlc_info *wlc)
2220
struct wlc_hw_info *wlc_hw = wlc->hw;
2225
bool fifosz_fixup = false;
2228
struct wiphy *wiphy = wlc->wiphy;
2230
regs = wlc_hw->regs;
2232
BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2235
wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2237
wlc_ucode_download(wlc_hw);
2239
* FIFOSZ fixup. driver wants to controls the fifo allocation.
2241
fifosz_fixup = true;
2243
/* let the PSM run to the suspended state, set mode to BSS STA */
2244
W_REG(®s->macintstatus, -1);
2245
wlc_bmac_mctrl(wlc_hw, ~0,
2246
(MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2248
/* wait for ucode to self-suspend after auto-init */
2249
SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
2251
if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
2252
wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2253
"suspend!\n", wlc_hw->unit);
2257
sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2259
if (D11REV_IS(wlc_hw->corerev, 23)) {
2260
if (WLCISNPHY(wlc_hw->band))
2261
wlc_write_inits(wlc_hw, d11n0initvals16);
2263
wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2264
" %d\n", __func__, wlc_hw->unit,
2266
} else if (D11REV_IS(wlc_hw->corerev, 24)) {
2267
if (WLCISLCNPHY(wlc_hw->band)) {
2268
wlc_write_inits(wlc_hw, d11lcn0initvals24);
2270
wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2271
" %d\n", __func__, wlc_hw->unit,
2275
wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2276
__func__, wlc_hw->unit, wlc_hw->corerev);
2279
/* For old ucode, txfifo sizes needs to be modified(increased) */
2280
if (fifosz_fixup == true) {
2281
wlc_corerev_fifofixup(wlc_hw);
2284
/* check txfifo allocations match between ucode and driver */
2285
buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2286
if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2290
buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2291
if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2295
buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2296
buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2297
buf[TX_AC_BK_FIFO] &= 0xff;
2298
if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2302
if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2306
buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2307
buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2308
buf[TX_BCMC_FIFO] &= 0xff;
2309
if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2313
if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2318
wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2319
" driver size %d index %d\n", buf[i],
2320
wlc_hw->xmtfifo_sz[i], i);
2323
/* make sure we can still talk to the mac */
2324
WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
2326
/* band-specific inits done by wlc_bsinit() */
2328
/* Set up frame burst size and antenna swap threshold init values */
2329
wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2330
wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2332
/* enable one rx interrupt per received frame */
2333
W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2335
/* set the station mode (BSS STA) */
2336
wlc_bmac_mctrl(wlc_hw,
2337
(MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2338
(MCTL_INFRA | MCTL_DISCARD_PMQ));
2340
/* set up Beacon interval */
2341
bcnint_us = 0x8000 << 10;
2342
W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2343
W_REG(®s->tsf_cfpstart, bcnint_us);
2344
W_REG(®s->macintstatus, MI_GP1);
2346
/* write interrupt mask */
2347
W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2349
/* allow the MAC to control the PHY clock (dynamic on/off) */
2350
wlc_bmac_macphyclk_set(wlc_hw, ON);
2352
/* program dynamic clock control fast powerup delay register */
2353
wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2354
W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2356
/* tell the ucode the corerev */
2357
wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2359
/* tell the ucode MAC capabilities */
2360
wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2361
(u16) (wlc_hw->machwcap & 0xffff));
2362
wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2364
machwcap >> 16) & 0xffff));
2366
/* write retry limits to SCR, this done after PSM init */
2367
W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2368
(void)R_REG(®s->objaddr);
2369
W_REG(®s->objdata, wlc_hw->SRL);
2370
W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2371
(void)R_REG(®s->objaddr);
2372
W_REG(®s->objdata, wlc_hw->LRL);
2374
/* write rate fallback retry limits */
2375
wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2376
wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2378
AND_REG(®s->ifs_ctl, 0x0FFF);
2379
W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
2381
/* dma initializations */
2382
wlc->txpend16165war = 0;
2384
/* init the tx dma engines */
2385
for (i = 0; i < NFIFO; i++) {
2387
dma_txinit(wlc_hw->di[i]);
2390
/* init the rx dma engine(s) and post receive buffers */
2391
dma_rxinit(wlc_hw->di[RX_FIFO]);
2392
dma_rxfill(wlc_hw->di[RX_FIFO]);
2395
/* This function is used for changing the tsf frac register
2396
* If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2397
* If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2398
* If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2399
* HTPHY Formula is 2^26/freq(MHz) e.g.
2400
* For spuron2 - 126MHz -> 2^26/126 = 532610.0
2401
* - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2402
* For spuron: 123MHz -> 2^26/123 = 545600.5
2403
* - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2404
* For spur off: 120MHz -> 2^26/120 = 559240.5
2405
* - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2408
void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2411
regs = wlc_hw->regs;
2413
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2414
(wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2415
if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2416
W_REG(®s->tsf_clk_frac_l, 0x2082);
2417
W_REG(®s->tsf_clk_frac_h, 0x8);
2418
} else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2419
W_REG(®s->tsf_clk_frac_l, 0x5341);
2420
W_REG(®s->tsf_clk_frac_h, 0x8);
2421
} else { /* 120Mhz */
2422
W_REG(®s->tsf_clk_frac_l, 0x8889);
2423
W_REG(®s->tsf_clk_frac_h, 0x8);
2425
} else if (WLCISLCNPHY(wlc_hw->band)) {
2426
if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2427
W_REG(®s->tsf_clk_frac_l, 0x7CE0);
2428
W_REG(®s->tsf_clk_frac_h, 0xC);
2429
} else { /* 80Mhz */
2430
W_REG(®s->tsf_clk_frac_l, 0xCCCD);
2431
W_REG(®s->tsf_clk_frac_h, 0xC);
2436
/* Initialize GPIOs that are controlled by D11 core */
2437
static void wlc_gpio_init(struct wlc_info *wlc)
2439
struct wlc_hw_info *wlc_hw = wlc->hw;
2443
regs = wlc_hw->regs;
2445
/* use GPIO select 0 to get all gpio signals from the gpio out reg */
2446
wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2449
* Common GPIO setup:
2450
* G0 = LED 0 = WLAN Activity
2451
* G1 = LED 1 = WLAN 2.4 GHz Radio State
2452
* G2 = LED 2 = WLAN 5 GHz Radio State
2453
* G4 = radio disable input (HI enabled, LO disabled)
2458
/* Allocate GPIOs for mimo antenna diversity feature */
2459
if (wlc_hw->antsel_type == ANTSEL_2x3) {
2460
/* Enable antenna diversity, use 2x3 mode */
2461
wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2462
MHF3_ANTSEL_EN, WLC_BAND_ALL);
2463
wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2464
MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2466
/* init superswitch control */
2467
wlc_phy_antsel_init(wlc_hw->band->pi, false);
2469
} else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2470
gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2472
* The board itself is powered by these GPIOs
2473
* (when not sending pattern) so set them high
2475
OR_REG(®s->psm_gpio_oe,
2476
(BOARD_GPIO_12 | BOARD_GPIO_13));
2477
OR_REG(®s->psm_gpio_out,
2478
(BOARD_GPIO_12 | BOARD_GPIO_13));
2480
/* Enable antenna diversity, use 2x4 mode */
2481
wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2482
MHF3_ANTSEL_EN, WLC_BAND_ALL);
2483
wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2486
/* Configure the desired clock to be 4Mhz */
2487
wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2488
ANTSEL_CLKDIV_4MHZ);
2491
/* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2492
if (wlc_hw->boardflags & BFL_PACTRL)
2493
gm |= gc |= BOARD_GPIO_PACTRL;
2495
/* apply to gpiocontrol register */
2496
ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2499
static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2501
struct wlc_info *wlc;
2504
if (wlc_hw->ucode_loaded)
2507
if (D11REV_IS(wlc_hw->corerev, 23)) {
2508
if (WLCISNPHY(wlc_hw->band)) {
2509
wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2511
wlc_hw->ucode_loaded = true;
2513
wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2515
__func__, wlc_hw->unit, wlc_hw->corerev);
2516
} else if (D11REV_IS(wlc_hw->corerev, 24)) {
2517
if (WLCISLCNPHY(wlc_hw->band)) {
2518
wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2520
wlc_hw->ucode_loaded = true;
2522
wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2524
__func__, wlc_hw->unit, wlc_hw->corerev);
2529
static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2530
const uint nbytes) {
2531
d11regs_t *regs = wlc_hw->regs;
2535
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2537
count = (nbytes / sizeof(u32));
2539
W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2540
(void)R_REG(®s->objaddr);
2541
for (i = 0; i < count; i++)
2542
W_REG(®s->objdata, ucode[i]);
2545
static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
2546
const struct d11init *inits)
2551
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2553
base = (volatile u8 *)wlc_hw->regs;
2555
for (i = 0; inits[i].addr != 0xffff; i++) {
2556
if (inits[i].size == 2)
2557
W_REG((u16 *)(base + inits[i].addr),
2559
else if (inits[i].size == 4)
2560
W_REG((u32 *)(base + inits[i].addr),
2565
static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2568
u16 phytxant = wlc_hw->bmac_phytxant;
2569
u16 mask = PHY_TXC_ANT_MASK;
2571
/* set the Probe Response frame phy control word */
2572
phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2573
phyctl = (phyctl & ~mask) | phytxant;
2574
wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2576
/* set the Response (ACK/CTS) frame phy control word */
2577
phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2578
phyctl = (phyctl & ~mask) | phytxant;
2579
wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2582
void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2584
/* update sw state */
2585
wlc_hw->bmac_phytxant = phytxant;
2587
/* push to ucode if up */
2590
wlc_ucode_txant_set(wlc_hw);
2594
u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2596
return (u16) wlc_hw->wlc->stf->txant;
2599
void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2601
wlc_hw->antsel_type = antsel_type;
2603
/* Update the antsel type for phy module to use */
2604
wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2607
void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2611
uint intstatus, idx;
2612
d11regs_t *regs = wlc_hw->regs;
2613
struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2615
unit = wlc_hw->unit;
2617
for (idx = 0; idx < NFIFO; idx++) {
2618
/* read intstatus register and ignore any non-error bits */
2620
R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
2624
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2625
unit, idx, intstatus);
2627
if (intstatus & I_RO) {
2628
wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2629
"overflow\n", unit, idx);
2633
if (intstatus & I_PC) {
2634
wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2639
if (intstatus & I_PD) {
2640
wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2645
if (intstatus & I_DE) {
2646
wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2647
"error\n", unit, idx);
2651
if (intstatus & I_RU) {
2652
wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2653
"underflow\n", idx, unit);
2656
if (intstatus & I_XU) {
2657
wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2658
"underflow\n", idx, unit);
2663
wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2666
W_REG(®s->intctrlregs[idx].intstatus,
2671
void wlc_intrson(struct wlc_info *wlc)
2673
struct wlc_hw_info *wlc_hw = wlc->hw;
2674
wlc->macintmask = wlc->defmacintmask;
2675
W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2678
/* callback for siutils.c, which has only wlc handler, no wl
2679
* they both check up, not only because there is no need to off/restore d11 interrupt
2680
* but also because per-port code may require sync with valid interrupt.
2683
static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2688
return wl_intrsoff(wlc->wl);
2691
static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2696
wl_intrsrestore(wlc->wl, macintmask);
2699
u32 wlc_intrsoff(struct wlc_info *wlc)
2701
struct wlc_hw_info *wlc_hw = wlc->hw;
2707
macintmask = wlc->macintmask; /* isr can still happen */
2709
W_REG(&wlc_hw->regs->macintmask, 0);
2710
(void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2711
udelay(1); /* ensure int line is no longer driven */
2712
wlc->macintmask = 0;
2714
/* return previous macintmask; resolve race between us and our isr */
2715
return wlc->macintstatus ? 0 : macintmask;
2718
void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2720
struct wlc_hw_info *wlc_hw = wlc->hw;
2724
wlc->macintmask = macintmask;
2725
W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2728
static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2730
u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2733
/* suspend tx fifos */
2734
wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2735
wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2736
wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2737
wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2739
/* zero the address match register so we do not send ACKs */
2740
wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2743
/* resume tx fifos */
2744
if (!wlc_hw->wlc->tx_suspended) {
2745
wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2747
wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2748
wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2749
wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2751
/* Restore address */
2752
wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2756
wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2759
wlc_ucode_mute_override_set(wlc_hw);
2761
wlc_ucode_mute_override_clear(wlc_hw);
2764
int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2769
*blocks = wlc_hw->xmtfifo_sz[fifo];
2774
/* wlc_bmac_tx_fifo_suspended:
2775
* Check the MAC's tx suspend status for a tx fifo.
2777
* When the MAC acknowledges a tx suspend, it indicates that no more
2778
* packets will be transmitted out the radio. This is independent of
2779
* DMA channel suspension---the DMA may have finished suspending, or may still
2780
* be pulling data into a tx fifo, by the time the MAC acks the suspend
2783
static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2785
/* check that a suspend has been requested and is no longer pending */
2788
* for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2789
* and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2790
* chnstatus register.
2791
* The tx fifo suspend completion is independent of the DMA suspend completion and
2792
* may be acked before or after the DMA is suspended.
2794
if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2795
(R_REG(&wlc_hw->regs->chnstatus) &
2796
(1 << tx_fifo)) == 0)
2802
static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2804
u8 fifo = 1 << tx_fifo;
2806
/* Two clients of this code, 11h Quiet period and scanning. */
2808
/* only suspend if not already suspended */
2809
if ((wlc_hw->suspended_fifos & fifo) == fifo)
2812
/* force the core awake only if not already */
2813
if (wlc_hw->suspended_fifos == 0)
2814
wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2816
wlc_hw->suspended_fifos |= fifo;
2818
if (wlc_hw->di[tx_fifo]) {
2819
/* Suspending AMPDU transmissions in the middle can cause underflow
2820
* which may result in mismatch between ucode and driver
2821
* so suspend the mac before suspending the FIFO
2823
if (WLC_PHY_11N_CAP(wlc_hw->band))
2824
wlc_suspend_mac_and_wait(wlc_hw->wlc);
2826
dma_txsuspend(wlc_hw->di[tx_fifo]);
2828
if (WLC_PHY_11N_CAP(wlc_hw->band))
2829
wlc_enable_mac(wlc_hw->wlc);
2833
static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2835
/* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2836
* here for PIO otherwise the watchdog will catch the inconsistency and fire
2838
/* Two clients of this code, 11h Quiet period and scanning. */
2839
if (wlc_hw->di[tx_fifo])
2840
dma_txresume(wlc_hw->di[tx_fifo]);
2842
/* allow core to sleep again */
2843
if (wlc_hw->suspended_fifos == 0)
2846
wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2847
if (wlc_hw->suspended_fifos == 0)
2848
wlc_ucode_wake_override_clear(wlc_hw,
2849
WLC_WAKE_OVERRIDE_TXFIFO);
2854
* Read and clear macintmask and macintstatus and intstatus registers.
2855
* This routine should be called with interrupts off
2857
* -1 if DEVICEREMOVED(wlc) evaluates to true;
2858
* 0 if the interrupt is not for us, or we are in some special cases;
2859
* device interrupt status bits otherwise.
2861
static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
2863
struct wlc_hw_info *wlc_hw = wlc->hw;
2864
d11regs_t *regs = wlc_hw->regs;
2867
/* macintstatus includes a DMA interrupt summary bit */
2868
macintstatus = R_REG(®s->macintstatus);
2870
BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2873
/* detect cardbus removed, in power down(suspend) and in reset */
2874
if (DEVICEREMOVED(wlc))
2877
/* DEVICEREMOVED succeeds even when the core is still resetting,
2878
* handle that case here.
2880
if (macintstatus == 0xffffffff)
2883
/* defer unsolicited interrupts */
2884
macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2887
if (macintstatus == 0)
2890
/* interrupts are already turned off for CFE build
2891
* Caution: For CFE Turning off the interrupts again has some undesired
2894
/* turn off the interrupts */
2895
W_REG(®s->macintmask, 0);
2896
(void)R_REG(®s->macintmask); /* sync readback */
2897
wlc->macintmask = 0;
2899
/* clear device interrupts */
2900
W_REG(®s->macintstatus, macintstatus);
2902
/* MI_DMAINT is indication of non-zero intstatus */
2903
if (macintstatus & MI_DMAINT) {
2905
* only fifo interrupt enabled is I_RI in
2906
* RX_FIFO. If MI_DMAINT is set, assume it
2907
* is set and clear the interrupt.
2909
W_REG(®s->intctrlregs[RX_FIFO].intstatus,
2913
return macintstatus;
2916
/* Update wlc->macintstatus and wlc->intstatus[]. */
2917
/* Return true if they are updated successfully. false otherwise */
2918
bool wlc_intrsupd(struct wlc_info *wlc)
2922
/* read and clear macintstatus and intstatus registers */
2923
macintstatus = wlc_intstatus(wlc, false);
2925
/* device is removed */
2926
if (macintstatus == 0xffffffff)
2929
/* update interrupt status in software */
2930
wlc->macintstatus |= macintstatus;
2936
* First-level interrupt processing.
2937
* Return true if this was our interrupt, false otherwise.
2938
* *wantdpc will be set to true if further wlc_dpc() processing is required,
2941
bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
2943
struct wlc_hw_info *wlc_hw = wlc->hw;
2948
if (!wlc_hw->up || !wlc->macintmask)
2951
/* read and clear macintstatus and intstatus registers */
2952
macintstatus = wlc_intstatus(wlc, true);
2954
if (macintstatus == 0xffffffff)
2955
wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2958
/* it is not for us */
2959
if (macintstatus == 0)
2964
/* save interrupt status bits */
2965
wlc->macintstatus = macintstatus;
2972
wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
2974
/* discard intermediate indications for ucode with one legitimate case:
2975
* e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2976
* tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2977
* transmission count)
2979
if (!(txs->status & TX_STATUS_AMPDU)
2980
&& (txs->status & TX_STATUS_INTERMEDIATE)) {
2984
return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
2987
/* process tx completion events in BMAC
2988
* Return true if more tx status need to be processed. false otherwise.
2991
wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
2993
bool morepending = false;
2994
struct wlc_info *wlc = wlc_hw->wlc;
2996
tx_status_t txstatus, *txs;
3000
* Param 'max_tx_num' indicates max. # tx status to process before
3003
uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3005
BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3008
regs = wlc_hw->regs;
3010
&& (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
3012
if (s1 == 0xffffffff) {
3013
wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3014
wlc_hw->unit, __func__);
3018
s2 = R_REG(®s->frmtxstatus2);
3020
txs->status = s1 & TXS_STATUS_MASK;
3021
txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3022
txs->sequence = s2 & TXS_SEQ_MASK;
3023
txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3024
txs->lasttxtime = 0;
3026
*fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3028
/* !give others some time to run! */
3029
if (++n >= max_tx_num)
3036
if (n >= max_tx_num)
3039
if (!pktq_empty(&wlc->pkt_queue->q))
3045
void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3047
struct wlc_hw_info *wlc_hw = wlc->hw;
3048
d11regs_t *regs = wlc_hw->regs;
3050
struct wiphy *wiphy = wlc->wiphy;
3052
BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3053
wlc_hw->band->bandunit);
3056
* Track overlapping suspend requests
3058
wlc_hw->mac_suspend_depth++;
3059
if (wlc_hw->mac_suspend_depth > 1)
3062
/* force the core awake */
3063
wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3065
mc = R_REG(®s->maccontrol);
3067
if (mc == 0xffffffff) {
3068
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3073
WARN_ON(mc & MCTL_PSM_JMP_0);
3074
WARN_ON(!(mc & MCTL_PSM_RUN));
3075
WARN_ON(!(mc & MCTL_EN_MAC));
3077
mi = R_REG(®s->macintstatus);
3078
if (mi == 0xffffffff) {
3079
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3084
WARN_ON(mi & MI_MACSSPNDD);
3086
wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3088
SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
3089
WLC_MAX_MAC_SUSPEND);
3091
if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
3092
wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3093
" and MI_MACSSPNDD is still not on.\n",
3094
wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3095
wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3096
"psm_brc 0x%04x\n", wlc_hw->unit,
3097
R_REG(®s->psmdebug),
3098
R_REG(®s->phydebug),
3099
R_REG(®s->psm_brc));
3102
mc = R_REG(®s->maccontrol);
3103
if (mc == 0xffffffff) {
3104
wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3109
WARN_ON(mc & MCTL_PSM_JMP_0);
3110
WARN_ON(!(mc & MCTL_PSM_RUN));
3111
WARN_ON(mc & MCTL_EN_MAC);
3114
void wlc_enable_mac(struct wlc_info *wlc)
3116
struct wlc_hw_info *wlc_hw = wlc->hw;
3117
d11regs_t *regs = wlc_hw->regs;
3120
BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3121
wlc->band->bandunit);
3124
* Track overlapping suspend requests
3126
wlc_hw->mac_suspend_depth--;
3127
if (wlc_hw->mac_suspend_depth > 0)
3130
mc = R_REG(®s->maccontrol);
3131
WARN_ON(mc & MCTL_PSM_JMP_0);
3132
WARN_ON(mc & MCTL_EN_MAC);
3133
WARN_ON(!(mc & MCTL_PSM_RUN));
3135
wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3136
W_REG(®s->macintstatus, MI_MACSSPNDD);
3138
mc = R_REG(®s->maccontrol);
3139
WARN_ON(mc & MCTL_PSM_JMP_0);
3140
WARN_ON(!(mc & MCTL_EN_MAC));
3141
WARN_ON(!(mc & MCTL_PSM_RUN));
3143
mi = R_REG(®s->macintstatus);
3144
WARN_ON(mi & MI_MACSSPNDD);
3146
wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3149
static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3153
WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3154
WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3160
if (!WLC_PHY_11N_CAP(wlc_hw->band))
3163
/* walk the phy rate table and update the entries */
3164
for (i = 0; i < ARRAY_SIZE(rates); i++) {
3167
entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3169
/* read the SHM Rate Table entry OFDM PCTL1 values */
3171
wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3173
/* modify the value */
3174
pctl1 &= ~PHY_TXC1_MODE_MASK;
3175
pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3177
/* Update the SHM Rate Table entry OFDM PCTL1 values */
3178
wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3183
static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3187
struct plcp_signal_rate_lookup {
3191
/* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3192
const struct plcp_signal_rate_lookup rate_lookup[] = {
3195
{WLC_RATE_12M, 0xA},
3196
{WLC_RATE_18M, 0xE},
3197
{WLC_RATE_24M, 0x9},
3198
{WLC_RATE_36M, 0xD},
3199
{WLC_RATE_48M, 0x8},
3203
for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3204
if (rate == rate_lookup[i].rate) {
3205
plcp_rate = rate_lookup[i].signal_rate;
3210
/* Find the SHM pointer to the rate table entry by looking in the
3213
return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3216
void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3218
wlc_hw->hw_stf_ss_opmode = stf_mode;
3221
wlc_upd_ofdm_pctl1_table(wlc_hw);
3225
wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3228
d11regs_t *regs = wlc_hw->regs;
3230
/* read the tsf timer low, then high to get an atomic read */
3231
*tsf_l_ptr = R_REG(®s->tsf_timerlow);
3232
*tsf_h_ptr = R_REG(®s->tsf_timerhigh);
3237
static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3241
struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3243
BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3245
regs = wlc_hw->regs;
3247
/* Validate dchip register access */
3249
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3250
(void)R_REG(®s->objaddr);
3251
w = R_REG(®s->objdata);
3253
/* Can we write and read back a 32bit register? */
3254
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3255
(void)R_REG(®s->objaddr);
3256
W_REG(®s->objdata, (u32) 0xaa5555aa);
3258
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3259
(void)R_REG(®s->objaddr);
3260
val = R_REG(®s->objdata);
3261
if (val != (u32) 0xaa5555aa) {
3262
wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3263
"expected 0xaa5555aa\n", wlc_hw->unit, val);
3267
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3268
(void)R_REG(®s->objaddr);
3269
W_REG(®s->objdata, (u32) 0x55aaaa55);
3271
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3272
(void)R_REG(®s->objaddr);
3273
val = R_REG(®s->objdata);
3274
if (val != (u32) 0x55aaaa55) {
3275
wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3276
"expected 0x55aaaa55\n", wlc_hw->unit, val);
3280
W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
3281
(void)R_REG(®s->objaddr);
3282
W_REG(®s->objdata, w);
3284
/* clear CFPStart */
3285
W_REG(®s->tsf_cfpstart, 0);
3287
w = R_REG(®s->maccontrol);
3288
if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3289
(w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3290
wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3291
"0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3292
(MCTL_IHR_EN | MCTL_WAKE),
3293
(MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3300
#define PHYPLL_WAIT_US 100000
3302
void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3307
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3310
regs = wlc_hw->regs;
3313
if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3314
OR_REG(®s->clk_ctl_st,
3315
(CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3316
CCS_ERSRC_REQ_PHYPLL));
3317
SPINWAIT((R_REG(®s->clk_ctl_st) &
3318
(CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3321
tmp = R_REG(®s->clk_ctl_st);
3322
if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3323
(CCS_ERSRC_AVAIL_HT)) {
3324
wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3325
" PLL failed\n", __func__);
3328
OR_REG(®s->clk_ctl_st,
3329
(CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3330
SPINWAIT((R_REG(®s->clk_ctl_st) &
3331
(CCS_ERSRC_AVAIL_D11PLL |
3332
CCS_ERSRC_AVAIL_PHYPLL)) !=
3333
(CCS_ERSRC_AVAIL_D11PLL |
3334
CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3336
tmp = R_REG(®s->clk_ctl_st);
3338
(CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3340
(CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3341
wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3342
"PHY PLL failed\n", __func__);
3346
/* Since the PLL may be shared, other cores can still be requesting it;
3347
* so we'll deassert the request but not wait for status to comply.
3349
AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3350
tmp = R_REG(®s->clk_ctl_st);
3354
void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3358
BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3360
dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3365
if (wlc_hw->noreset)
3369
wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3371
/* turn off analog core */
3372
wlc_phy_anacore(wlc_hw->band->pi, OFF);
3374
/* turn off PHYPLL to save power */
3375
wlc_bmac_core_phypll_ctl(wlc_hw, false);
3377
/* No need to set wlc->pub->radio_active = OFF
3378
* because this function needs down capability and
3379
* radio_active is designed for BCMNODOWN.
3382
/* remove gpio controls */
3383
if (wlc_hw->ucode_dbgsel)
3384
ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3386
wlc_hw->clk = false;
3387
ai_core_disable(wlc_hw->sih, 0);
3388
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3391
/* power both the pll and external oscillator on/off */
3392
static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3394
BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3396
/* dont power down if plldown is false or we must poll hw radio disable */
3397
if (!want && wlc_hw->pllreq)
3401
ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3403
wlc_hw->sbclk = want;
3404
if (!wlc_hw->sbclk) {
3405
wlc_hw->clk = false;
3406
if (wlc_hw->band && wlc_hw->band->pi)
3407
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3411
static void wlc_flushqueues(struct wlc_info *wlc)
3413
struct wlc_hw_info *wlc_hw = wlc->hw;
3416
wlc->txpend16165war = 0;
3418
/* free any posted tx packets */
3419
for (i = 0; i < NFIFO; i++)
3420
if (wlc_hw->di[i]) {
3421
dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3422
TXPKTPENDCLR(wlc, i);
3423
BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3426
/* free any posted rx packets */
3427
dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3430
u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3432
return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3435
void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3437
wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3441
wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3443
d11regs_t *regs = wlc_hw->regs;
3444
volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3445
volatile u16 *objdata_hi = objdata_lo + 1;
3448
W_REG(®s->objaddr, sel | (offset >> 2));
3449
(void)R_REG(®s->objaddr);
3451
v = R_REG(objdata_hi);
3453
v = R_REG(objdata_lo);
3460
wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3462
d11regs_t *regs = wlc_hw->regs;
3463
volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
3464
volatile u16 *objdata_hi = objdata_lo + 1;
3466
W_REG(®s->objaddr, sel | (offset >> 2));
3467
(void)R_REG(®s->objaddr);
3469
W_REG(objdata_hi, v);
3471
W_REG(objdata_lo, v);
3475
/* Copy a buffer to shared memory of specified type .
3476
* SHM 'offset' needs to be an even address and
3477
* Buffer length 'len' must be an even number of bytes
3478
* 'sel' selects the type of memory
3481
wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3485
const u8 *p = (const u8 *)buf;
3488
if (len <= 0 || (offset & 1) || (len & 1))
3491
for (i = 0; i < len; i += 2) {
3492
v = p[i] | (p[i + 1] << 8);
3493
wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3497
/* Copy a piece of shared memory of specified type to a buffer .
3498
* SHM 'offset' needs to be an even address and
3499
* Buffer length 'len' must be an even number of bytes
3500
* 'sel' selects the type of memory
3503
wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3510
if (len <= 0 || (offset & 1) || (len & 1))
3513
for (i = 0; i < len; i += 2) {
3514
v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3516
p[i + 1] = (v >> 8) & 0xFF;
3520
void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3522
BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3525
*buf = wlc_hw->vars;
3526
*len = wlc_hw->vars_size;
3529
void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3534
/* write retry limit to SCR, shouldn't need to suspend */
3536
W_REG(&wlc_hw->regs->objaddr,
3537
OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3538
(void)R_REG(&wlc_hw->regs->objaddr);
3539
W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3540
W_REG(&wlc_hw->regs->objaddr,
3541
OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3542
(void)R_REG(&wlc_hw->regs->objaddr);
3543
W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3547
void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3550
if (mboolisset(wlc_hw->pllreq, req_bit))
3553
mboolset(wlc_hw->pllreq, req_bit);
3555
if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3556
if (!wlc_hw->sbclk) {
3557
wlc_bmac_xtal(wlc_hw, ON);
3561
if (!mboolisset(wlc_hw->pllreq, req_bit))
3564
mboolclr(wlc_hw->pllreq, req_bit);
3566
if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3567
if (wlc_hw->sbclk) {
3568
wlc_bmac_xtal(wlc_hw, OFF);
3576
u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3581
/* get the phy specific rate encoding for the PLCP SIGNAL field */
3582
/* XXX4321 fixup needed ? */
3584
table_ptr = M_RT_DIRMAP_A;
3586
table_ptr = M_RT_DIRMAP_B;
3588
/* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3589
* the index into the rate table.
3591
phy_rate = rate_info[rate] & WLC_RATE_MASK;
3592
index = phy_rate & 0xf;
3594
/* Find the SHM pointer to the rate table entry by looking in the
3597
return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3600
void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3602
wlc_hw->antsel_avail = antsel_avail;
added
removed
drivers/staging/brcm80211/brcmsmac/wlc_bmac.c
