← Back to branch summary

~ubuntu-branches/ubuntu/precise/linux-ti-omap4/precise

« back to all changes in this revision

Viewing changes to arch/mips/include/asm/netlogic/xlr/pic.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

Show diffs side-by-side

added added

removed removed

Lines of Context:
arch/mips/include/asm/netlogic/xlr/pic.h
 
1
/*
 
2
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 
3
 * reserved.
 
4
 *
 
5
 * This software is available to you under a choice of one of two
 
6
 * licenses.  You may choose to be licensed under the terms of the GNU
 
7
 * General Public License (GPL) Version 2, available from the file
 
8
 * COPYING in the main directory of this source tree, or the NetLogic
 
9
 * license below:
 
10
 *
 
11
 * Redistribution and use in source and binary forms, with or without
 
12
 * modification, are permitted provided that the following conditions
 
13
 * are met:
 
14
 *
 
15
 * 1. Redistributions of source code must retain the above copyright
 
16
 *    notice, this list of conditions and the following disclaimer.
 
17
 * 2. Redistributions in binary form must reproduce the above copyright
 
18
 *    notice, this list of conditions and the following disclaimer in
 
19
 *    the documentation and/or other materials provided with the
 
20
 *    distribution.
 
21
 *
 
22
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 
23
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 
24
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 
25
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 
26
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 
27
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 
28
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 
29
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 
30
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 
31
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 
32
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
33
 */
 
34
 
 
35
#ifndef _ASM_NLM_XLR_PIC_H
 
36
#define _ASM_NLM_XLR_PIC_H
 
37
 
 
38
#define PIC_CLKS_PER_SEC                66666666ULL
 
39
/* PIC hardware interrupt numbers */
 
40
#define PIC_IRT_WD_INDEX                0
 
41
#define PIC_IRT_TIMER_0_INDEX           1
 
42
#define PIC_IRT_TIMER_1_INDEX           2
 
43
#define PIC_IRT_TIMER_2_INDEX           3
 
44
#define PIC_IRT_TIMER_3_INDEX           4
 
45
#define PIC_IRT_TIMER_4_INDEX           5
 
46
#define PIC_IRT_TIMER_5_INDEX           6
 
47
#define PIC_IRT_TIMER_6_INDEX           7
 
48
#define PIC_IRT_TIMER_7_INDEX           8
 
49
#define PIC_IRT_CLOCK_INDEX             PIC_IRT_TIMER_7_INDEX
 
50
#define PIC_IRT_UART_0_INDEX            9
 
51
#define PIC_IRT_UART_1_INDEX            10
 
52
#define PIC_IRT_I2C_0_INDEX             11
 
53
#define PIC_IRT_I2C_1_INDEX             12
 
54
#define PIC_IRT_PCMCIA_INDEX            13
 
55
#define PIC_IRT_GPIO_INDEX              14
 
56
#define PIC_IRT_HYPER_INDEX             15
 
57
#define PIC_IRT_PCIX_INDEX              16
 
58
/* XLS */
 
59
#define PIC_IRT_CDE_INDEX               15
 
60
#define PIC_IRT_BRIDGE_TB_XLS_INDEX     16
 
61
/* XLS */
 
62
#define PIC_IRT_GMAC0_INDEX             17
 
63
#define PIC_IRT_GMAC1_INDEX             18
 
64
#define PIC_IRT_GMAC2_INDEX             19
 
65
#define PIC_IRT_GMAC3_INDEX             20
 
66
#define PIC_IRT_XGS0_INDEX              21
 
67
#define PIC_IRT_XGS1_INDEX              22
 
68
#define PIC_IRT_HYPER_FATAL_INDEX       23
 
69
#define PIC_IRT_PCIX_FATAL_INDEX        24
 
70
#define PIC_IRT_BRIDGE_AERR_INDEX       25
 
71
#define PIC_IRT_BRIDGE_BERR_INDEX       26
 
72
#define PIC_IRT_BRIDGE_TB_XLR_INDEX     27
 
73
#define PIC_IRT_BRIDGE_AERR_NMI_INDEX   28
 
74
/* XLS */
 
75
#define PIC_IRT_GMAC4_INDEX             21
 
76
#define PIC_IRT_GMAC5_INDEX             22
 
77
#define PIC_IRT_GMAC6_INDEX             23
 
78
#define PIC_IRT_GMAC7_INDEX             24
 
79
#define PIC_IRT_BRIDGE_ERR_INDEX        25
 
80
#define PIC_IRT_PCIE_LINK0_INDEX        26
 
81
#define PIC_IRT_PCIE_LINK1_INDEX        27
 
82
#define PIC_IRT_PCIE_LINK2_INDEX        23
 
83
#define PIC_IRT_PCIE_LINK3_INDEX        24
 
84
#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX  28
 
85
#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX  29
 
86
#define PIC_IRT_SRIO_LINK0_INDEX        26
 
87
#define PIC_IRT_SRIO_LINK1_INDEX        27
 
88
#define PIC_IRT_SRIO_LINK2_INDEX        28
 
89
#define PIC_IRT_SRIO_LINK3_INDEX        29
 
90
#define PIC_IRT_PCIE_INT_INDEX          28
 
91
#define PIC_IRT_PCIE_FATAL_INDEX        29
 
92
#define PIC_IRT_GPIO_B_INDEX            30
 
93
#define PIC_IRT_USB_INDEX               31
 
94
/* XLS */
 
95
#define PIC_NUM_IRTS                    32
 
96
 
 
97
 
 
98
#define PIC_CLOCK_TIMER                 7
 
99
 
 
100
/* PIC Registers */
 
101
#define PIC_CTRL                        0x00
 
102
#define PIC_IPI                         0x04
 
103
#define PIC_INT_ACK                     0x06
 
104
 
 
105
#define WD_MAX_VAL_0                    0x08
 
106
#define WD_MAX_VAL_1                    0x09
 
107
#define WD_MASK_0                       0x0a
 
108
#define WD_MASK_1                       0x0b
 
109
#define WD_HEARBEAT_0                   0x0c
 
110
#define WD_HEARBEAT_1                   0x0d
 
111
 
 
112
#define PIC_IRT_0_BASE                  0x40
 
113
#define PIC_IRT_1_BASE                  0x80
 
114
#define PIC_TIMER_MAXVAL_0_BASE         0x100
 
115
#define PIC_TIMER_MAXVAL_1_BASE         0x110
 
116
#define PIC_TIMER_COUNT_0_BASE          0x120
 
117
#define PIC_TIMER_COUNT_1_BASE          0x130
 
118
 
 
119
#define PIC_IRT_0(picintr)      (PIC_IRT_0_BASE + (picintr))
 
120
#define PIC_IRT_1(picintr)      (PIC_IRT_1_BASE + (picintr))
 
121
 
 
122
#define PIC_TIMER_MAXVAL_0(i)   (PIC_TIMER_MAXVAL_0_BASE + (i))
 
123
#define PIC_TIMER_MAXVAL_1(i)   (PIC_TIMER_MAXVAL_1_BASE + (i))
 
124
#define PIC_TIMER_COUNT_0(i)    (PIC_TIMER_COUNT_0_BASE + (i))
 
125
#define PIC_TIMER_COUNT_1(i)    (PIC_TIMER_COUNT_0_BASE + (i))
 
126
 
 
127
/*
 
128
 * Mapping between hardware interrupt numbers and IRQs on CPU
 
129
 * we use a simple scheme to map PIC interrupts 0-31 to IRQs
 
130
 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
 
131
 * count/compare and FMN
 
132
 */
 
133
#define PIC_IRQ_BASE            8
 
134
#define PIC_INTR_TO_IRQ(i)      (PIC_IRQ_BASE + (i))
 
135
#define PIC_IRQ_TO_INTR(i)      ((i) - PIC_IRQ_BASE)
 
136
 
 
137
#define PIC_IRT_FIRST_IRQ       PIC_IRQ_BASE
 
138
#define PIC_WD_IRQ              PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
 
139
#define PIC_TIMER_0_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
 
140
#define PIC_TIMER_1_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
 
141
#define PIC_TIMER_2_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
 
142
#define PIC_TIMER_3_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
 
143
#define PIC_TIMER_4_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
 
144
#define PIC_TIMER_5_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
 
145
#define PIC_TIMER_6_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
 
146
#define PIC_TIMER_7_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
 
147
#define PIC_CLOCK_IRQ           (PIC_TIMER_7_IRQ)
 
148
#define PIC_UART_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
 
149
#define PIC_UART_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
 
150
#define PIC_I2C_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
 
151
#define PIC_I2C_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
 
152
#define PIC_PCMCIA_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
 
153
#define PIC_GPIO_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
 
154
#define PIC_HYPER_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
 
155
#define PIC_PCIX_IRQ            PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
 
156
/* XLS */
 
157
#define PIC_CDE_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
 
158
#define PIC_BRIDGE_TB_XLS_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
 
159
/* end XLS */
 
160
#define PIC_GMAC_0_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
 
161
#define PIC_GMAC_1_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
 
162
#define PIC_GMAC_2_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
 
163
#define PIC_GMAC_3_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
 
164
#define PIC_XGS_0_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
 
165
#define PIC_XGS_1_IRQ           PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
 
166
#define PIC_HYPER_FATAL_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
 
167
#define PIC_PCIX_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
 
168
#define PIC_BRIDGE_AERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
 
169
#define PIC_BRIDGE_BERR_IRQ     PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
 
170
#define PIC_BRIDGE_TB_XLR_IRQ   PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
 
171
#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
 
172
/* XLS defines */
 
173
#define PIC_GMAC_4_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
 
174
#define PIC_GMAC_5_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
 
175
#define PIC_GMAC_6_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
 
176
#define PIC_GMAC_7_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
 
177
#define PIC_BRIDGE_ERR_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
 
178
#define PIC_PCIE_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
 
179
#define PIC_PCIE_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
 
180
#define PIC_PCIE_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
 
181
#define PIC_PCIE_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
 
182
#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
 
183
#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
 
184
#define PIC_SRIO_LINK0_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
 
185
#define PIC_SRIO_LINK1_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
 
186
#define PIC_SRIO_LINK2_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
 
187
#define PIC_SRIO_LINK3_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
 
188
#define PIC_PCIE_INT_IRQ        PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
 
189
#define PIC_PCIE_FATAL_IRQ      PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
 
190
#define PIC_GPIO_B_IRQ          PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
 
191
#define PIC_USB_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
 
192
#define PIC_IRT_LAST_IRQ        PIC_USB_IRQ
 
193
/* end XLS */
 
194
 
 
195
#ifndef __ASSEMBLY__
 
196
static inline void pic_send_ipi(u32 ipi)
 
197
{
 
198
        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
199
 
 
200
        netlogic_write_reg(mmio, PIC_IPI, ipi);
 
201
}
 
202
 
 
203
static inline u32 pic_read_control(void)
 
204
{
 
205
        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
206
 
 
207
        return netlogic_read_reg(mmio, PIC_CTRL);
 
208
}
 
209
 
 
210
static inline void pic_write_control(u32 control)
 
211
{
 
212
        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
213
 
 
214
        netlogic_write_reg(mmio, PIC_CTRL, control);
 
215
}
 
216
 
 
217
static inline void pic_update_control(u32 control)
 
218
{
 
219
        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
220
 
 
221
        netlogic_write_reg(mmio, PIC_CTRL,
 
222
                (control | netlogic_read_reg(mmio, PIC_CTRL)));
 
223
}
 
224
 
 
225
#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
 
226
                                        ((irq) <= PIC_TIMER_7_IRQ))
 
227
#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
 
228
                                        ((irq) <= PIC_IRT_LAST_IRQ))
 
229
#endif
 
230
 
 
231
#endif /* _ASM_NLM_XLR_PIC_H */