6
6
* with various broken implementations of this HW.
8
8
* Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9
* Copyright 2010-2011 Freescale Semiconductor, Inc.
10
11
* This file is subject to the terms and conditions of the GNU General Public
11
12
* License. See the file COPYING in the main directory of this archive
208
221
_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
224
static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
226
unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227
((tm & 3) * MPIC_INFO(TIMER_STRIDE));
230
offset += 0x1000 / 4;
232
return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
235
static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
237
unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238
((tm & 3) * MPIC_INFO(TIMER_STRIDE));
241
offset += 0x1000 / 4;
243
_mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
211
246
static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
213
unsigned int cpu = 0;
248
unsigned int cpu = mpic_processor_id(mpic);
215
if (mpic->flags & MPIC_PRIMARY)
216
cpu = hard_smp_processor_id();
217
250
return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
220
253
static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
222
unsigned int cpu = 0;
224
if (mpic->flags & MPIC_PRIMARY)
225
cpu = hard_smp_processor_id();
255
unsigned int cpu = mpic_processor_id(mpic);
227
257
_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
263
293
#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
264
294
#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
265
295
#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296
#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297
#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
266
298
#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
267
299
#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
268
300
#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
365
397
if (fixup->base == NULL)
368
DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
369
source, irqflags, fixup->index);
400
DBG("startup_ht_interrupt(0x%x) index: %d\n",
401
source, fixup->index);
370
402
raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
371
403
/* Enable and configure */
372
404
writeb(0x10 + 2 * fixup->index, fixup->base + 2);
373
405
tmp = readl(fixup->base + 4);
375
if (irqflags & IRQ_LEVEL)
377
409
writel(tmp, fixup->base + 4);
378
410
raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
606
#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
608
637
/* Find an mpic associated with a given linux interrupt */
609
638
static struct mpic *mpic_find(unsigned int irq)
611
640
if (irq < NUM_ISA_INTERRUPTS)
614
return irq_to_desc(irq)->chip_data;
643
return irq_get_chip_data(irq);
617
646
/* Determine if the linux irq is an IPI */
618
647
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
620
unsigned int src = mpic_irq_to_hw(irq);
649
unsigned int src = virq_to_hw(irq);
622
651
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
654
/* Determine if the linux irq is a timer */
655
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
657
unsigned int src = virq_to_hw(irq);
659
return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
626
662
/* Convert a cpu mask from logical to physical cpu numbers. */
627
663
static inline u32 mpic_physmask(u32 cpumask)
632
for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
668
for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
633
669
mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
637
673
#ifdef CONFIG_SMP
638
674
/* Get the mpic structure from the IPI number */
639
static inline struct mpic * mpic_from_ipi(unsigned int ipi)
675
static inline struct mpic * mpic_from_ipi(struct irq_data *d)
641
return irq_to_desc(ipi)->chip_data;
677
return irq_data_get_irq_chip_data(d);
645
681
/* Get the mpic structure from the irq number */
646
682
static inline struct mpic * mpic_from_irq(unsigned int irq)
648
return irq_to_desc(irq)->chip_data;
684
return irq_get_chip_data(irq);
687
/* Get the mpic structure from the irq data */
688
static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
690
return irq_data_get_irq_chip_data(d);
651
693
/* Send an EOI */
663
void mpic_unmask_irq(unsigned int irq)
705
void mpic_unmask_irq(struct irq_data *d)
665
707
unsigned int loops = 100000;
666
struct mpic *mpic = mpic_from_irq(irq);
667
unsigned int src = mpic_irq_to_hw(irq);
708
struct mpic *mpic = mpic_from_irq_data(d);
709
unsigned int src = irqd_to_hwirq(d);
669
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
711
DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
671
713
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
672
714
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
681
723
} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
684
void mpic_mask_irq(unsigned int irq)
726
void mpic_mask_irq(struct irq_data *d)
686
728
unsigned int loops = 100000;
687
struct mpic *mpic = mpic_from_irq(irq);
688
unsigned int src = mpic_irq_to_hw(irq);
729
struct mpic *mpic = mpic_from_irq_data(d);
730
unsigned int src = irqd_to_hwirq(d);
690
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
732
DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
692
734
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
693
735
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
703
745
} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
706
void mpic_end_irq(unsigned int irq)
748
void mpic_end_irq(struct irq_data *d)
708
struct mpic *mpic = mpic_from_irq(irq);
750
struct mpic *mpic = mpic_from_irq_data(d);
711
DBG("%s: end_irq: %d\n", mpic->name, irq);
753
DBG("%s: end_irq: %d\n", mpic->name, d->irq);
713
755
/* We always EOI on end_irq() even for edge interrupts since that
714
756
* should only lower the priority, the MPIC should have properly
721
763
#ifdef CONFIG_MPIC_U3_HT_IRQS
723
static void mpic_unmask_ht_irq(unsigned int irq)
765
static void mpic_unmask_ht_irq(struct irq_data *d)
725
struct mpic *mpic = mpic_from_irq(irq);
726
unsigned int src = mpic_irq_to_hw(irq);
728
mpic_unmask_irq(irq);
730
if (irq_to_desc(irq)->status & IRQ_LEVEL)
767
struct mpic *mpic = mpic_from_irq_data(d);
768
unsigned int src = irqd_to_hwirq(d);
772
if (irqd_is_level_type(d))
731
773
mpic_ht_end_irq(mpic, src);
734
static unsigned int mpic_startup_ht_irq(unsigned int irq)
776
static unsigned int mpic_startup_ht_irq(struct irq_data *d)
736
struct mpic *mpic = mpic_from_irq(irq);
737
unsigned int src = mpic_irq_to_hw(irq);
778
struct mpic *mpic = mpic_from_irq_data(d);
779
unsigned int src = irqd_to_hwirq(d);
739
mpic_unmask_irq(irq);
740
mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
782
mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
745
static void mpic_shutdown_ht_irq(unsigned int irq)
787
static void mpic_shutdown_ht_irq(struct irq_data *d)
747
struct mpic *mpic = mpic_from_irq(irq);
748
unsigned int src = mpic_irq_to_hw(irq);
789
struct mpic *mpic = mpic_from_irq_data(d);
790
unsigned int src = irqd_to_hwirq(d);
750
mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
792
mpic_shutdown_ht_interrupt(mpic, src);
754
static void mpic_end_ht_irq(unsigned int irq)
796
static void mpic_end_ht_irq(struct irq_data *d)
756
struct mpic *mpic = mpic_from_irq(irq);
757
unsigned int src = mpic_irq_to_hw(irq);
798
struct mpic *mpic = mpic_from_irq_data(d);
799
unsigned int src = irqd_to_hwirq(d);
760
DBG("%s: end_irq: %d\n", mpic->name, irq);
802
DBG("%s: end_irq: %d\n", mpic->name, d->irq);
762
804
/* We always EOI on end_irq() even for edge interrupts since that
763
805
* should only lower the priority, the MPIC should have properly
764
806
* latched another edge interrupt coming in anyway
767
if (irq_to_desc(irq)->status & IRQ_LEVEL)
809
if (irqd_is_level_type(d))
768
810
mpic_ht_end_irq(mpic, src);
773
815
#ifdef CONFIG_SMP
775
static void mpic_unmask_ipi(unsigned int irq)
817
static void mpic_unmask_ipi(struct irq_data *d)
777
struct mpic *mpic = mpic_from_ipi(irq);
778
unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
819
struct mpic *mpic = mpic_from_ipi(d);
820
unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
780
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
822
DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
781
823
mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
784
static void mpic_mask_ipi(unsigned int irq)
826
static void mpic_mask_ipi(struct irq_data *d)
786
828
/* NEVER disable an IPI... that's just plain wrong! */
789
static void mpic_end_ipi(unsigned int irq)
831
static void mpic_end_ipi(struct irq_data *d)
791
struct mpic *mpic = mpic_from_ipi(irq);
833
struct mpic *mpic = mpic_from_ipi(d);
794
836
* IPIs are marked IRQ_PER_CPU. This has the side effect of
803
845
#endif /* CONFIG_SMP */
805
int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
807
struct mpic *mpic = mpic_from_irq(irq);
808
unsigned int src = mpic_irq_to_hw(irq);
847
static void mpic_unmask_tm(struct irq_data *d)
849
struct mpic *mpic = mpic_from_irq_data(d);
850
unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
852
DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
853
mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
857
static void mpic_mask_tm(struct irq_data *d)
859
struct mpic *mpic = mpic_from_irq_data(d);
860
unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
862
mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
866
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
869
struct mpic *mpic = mpic_from_irq_data(d);
870
unsigned int src = irqd_to_hwirq(d);
810
872
if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
811
873
int cpuid = irq_choose_cpu(cpumask);
813
875
mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
817
alloc_cpumask_var(&tmp, GFP_KERNEL);
819
cpumask_and(tmp, cpumask, cpu_online_mask);
877
u32 mask = cpumask_bits(cpumask)[0];
879
mask &= cpumask_bits(cpu_online_mask)[0];
821
881
mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
822
mpic_physmask(cpumask_bits(tmp)[0]));
824
free_cpumask_var(tmp);
882
mpic_physmask(mask));
851
int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
909
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
853
struct mpic *mpic = mpic_from_irq(virq);
854
unsigned int src = mpic_irq_to_hw(virq);
855
struct irq_desc *desc = irq_to_desc(virq);
911
struct mpic *mpic = mpic_from_irq_data(d);
912
unsigned int src = irqd_to_hwirq(d);
856
913
unsigned int vecpri, vold, vnew;
858
915
DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
859
mpic, virq, src, flow_type);
916
mpic, d->irq, src, flow_type);
861
918
if (src >= mpic->irq_count)
867
924
if (flow_type == IRQ_TYPE_NONE)
868
925
flow_type = IRQ_TYPE_LEVEL_LOW;
870
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
871
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
872
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
873
desc->status |= IRQ_LEVEL;
927
irqd_set_trigger_type(d, flow_type);
875
929
if (mpic_is_ht_interrupt(mpic, src))
876
930
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
885
939
if (vold != vnew)
886
940
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
942
return IRQ_SET_MASK_OK_NOCOPY;;
891
945
void mpic_set_vector(unsigned int virq, unsigned int vector)
893
947
struct mpic *mpic = mpic_from_irq(virq);
894
unsigned int src = mpic_irq_to_hw(virq);
948
unsigned int src = virq_to_hw(virq);
895
949
unsigned int vecpri;
897
951
DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
906
960
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
963
void mpic_set_destination(unsigned int virq, unsigned int cpuid)
965
struct mpic *mpic = mpic_from_irq(virq);
966
unsigned int src = virq_to_hw(virq);
968
DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
969
mpic, virq, src, cpuid);
971
if (src >= mpic->irq_count)
974
mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
909
977
static struct irq_chip mpic_irq_chip = {
910
.mask = mpic_mask_irq,
911
.unmask = mpic_unmask_irq,
913
.set_type = mpic_set_irq_type,
978
.irq_mask = mpic_mask_irq,
979
.irq_unmask = mpic_unmask_irq,
980
.irq_eoi = mpic_end_irq,
981
.irq_set_type = mpic_set_irq_type,
916
984
#ifdef CONFIG_SMP
917
985
static struct irq_chip mpic_ipi_chip = {
918
.mask = mpic_mask_ipi,
919
.unmask = mpic_unmask_ipi,
986
.irq_mask = mpic_mask_ipi,
987
.irq_unmask = mpic_unmask_ipi,
988
.irq_eoi = mpic_end_ipi,
922
990
#endif /* CONFIG_SMP */
992
static struct irq_chip mpic_tm_chip = {
993
.irq_mask = mpic_mask_tm,
994
.irq_unmask = mpic_unmask_tm,
995
.irq_eoi = mpic_end_irq,
924
998
#ifdef CONFIG_MPIC_U3_HT_IRQS
925
999
static struct irq_chip mpic_irq_ht_chip = {
926
.startup = mpic_startup_ht_irq,
927
.shutdown = mpic_shutdown_ht_irq,
928
.mask = mpic_mask_irq,
929
.unmask = mpic_unmask_ht_irq,
930
.eoi = mpic_end_ht_irq,
931
.set_type = mpic_set_irq_type,
1000
.irq_startup = mpic_startup_ht_irq,
1001
.irq_shutdown = mpic_shutdown_ht_irq,
1002
.irq_mask = mpic_mask_irq,
1003
.irq_unmask = mpic_unmask_ht_irq,
1004
.irq_eoi = mpic_end_ht_irq,
1005
.irq_set_type = mpic_set_irq_type,
933
1007
#endif /* CONFIG_MPIC_U3_HT_IRQS */
957
1031
WARN_ON(!(mpic->flags & MPIC_PRIMARY));
959
1033
DBG("mpic: mapping as IPI\n");
960
set_irq_chip_data(virq, mpic);
961
set_irq_chip_and_handler(virq, &mpic->hc_ipi,
1034
irq_set_chip_data(virq, mpic);
1035
irq_set_chip_and_handler(virq, &mpic->hc_ipi,
962
1036
handle_percpu_irq);
965
1039
#endif /* CONFIG_SMP */
1041
if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1042
WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1044
DBG("mpic: mapping as timer\n");
1045
irq_set_chip_data(virq, mpic);
1046
irq_set_chip_and_handler(virq, &mpic->hc_tm,
1047
handle_fasteoi_irq);
967
1051
if (hw >= mpic->irq_count)
981
1065
DBG("mpic: mapping to irq chip @%p\n", chip);
983
set_irq_chip_data(virq, mpic);
984
set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
1067
irq_set_chip_data(virq, mpic);
1068
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
986
1070
/* Set default irq type */
987
set_irq_type(virq, IRQ_TYPE_NONE);
1071
irq_set_irq_type(virq, IRQ_TYPE_NONE);
1073
/* If the MPIC was reset, then all vectors have already been
1074
* initialized. Otherwise, a per source lazy initialization
1077
if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1078
mpic_set_vector(virq, hw);
1079
mpic_set_destination(virq, mpic_processor_id(mpic));
1080
mpic_irq_set_priority(virq, 8);
1004
1099
*out_hwirq = intspec[0];
1100
if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1102
* Freescale MPIC with extended intspec:
1103
* First two cells are as usual. Third specifies
1104
* an "interrupt type". Fourth is type-specific data.
1106
* See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1108
switch (intspec[2]) {
1110
case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1113
if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1116
*out_hwirq = mpic->ipi_vecs[intspec[0]];
1119
if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1122
*out_hwirq = mpic->timer_vecs[intspec[0]];
1125
pr_debug("%s: unknown irq type %u\n",
1126
__func__, intspec[2]);
1130
*out_flags = map_mpic_senses[intspec[1] & 3];
1131
} else if (intsize > 1) {
1006
1132
u32 mask = 0x3;
1008
1134
/* Apple invented a new race of encoding on machines with
1060
1191
mpic->hc_irq = mpic_irq_chip;
1061
1192
mpic->hc_irq.name = name;
1062
1193
if (flags & MPIC_PRIMARY)
1063
mpic->hc_irq.set_affinity = mpic_set_affinity;
1194
mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1064
1195
#ifdef CONFIG_MPIC_U3_HT_IRQS
1065
1196
mpic->hc_ht_irq = mpic_irq_ht_chip;
1066
1197
mpic->hc_ht_irq.name = name;
1067
1198
if (flags & MPIC_PRIMARY)
1068
mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1199
mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1069
1200
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1071
1202
#ifdef CONFIG_SMP
1084
1218
intvec_top = 255;
1086
mpic->timer_vecs[0] = intvec_top - 8;
1087
mpic->timer_vecs[1] = intvec_top - 7;
1088
mpic->timer_vecs[2] = intvec_top - 6;
1089
mpic->timer_vecs[3] = intvec_top - 5;
1220
mpic->timer_vecs[0] = intvec_top - 12;
1221
mpic->timer_vecs[1] = intvec_top - 11;
1222
mpic->timer_vecs[2] = intvec_top - 10;
1223
mpic->timer_vecs[3] = intvec_top - 9;
1224
mpic->timer_vecs[4] = intvec_top - 8;
1225
mpic->timer_vecs[5] = intvec_top - 7;
1226
mpic->timer_vecs[6] = intvec_top - 6;
1227
mpic->timer_vecs[7] = intvec_top - 5;
1090
1228
mpic->ipi_vecs[0] = intvec_top - 4;
1091
1229
mpic->ipi_vecs[1] = intvec_top - 3;
1092
1230
mpic->ipi_vecs[2] = intvec_top - 2;
1096
1234
/* Check for "big-endian" in device-tree */
1097
1235
if (node && of_get_property(node, "big-endian", NULL) != NULL)
1098
1236
mpic->flags |= MPIC_BIG_ENDIAN;
1237
if (node && of_device_is_compatible(node, "fsl,mpic"))
1238
mpic->flags |= MPIC_FSL;
1100
1240
/* Look for protected sources */
1153
1293
mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1156
if (flags & MPIC_WANTS_RESET) {
1297
/* When using a device-node, reset requests are only honored if the MPIC
1298
* is allowed to reset.
1300
if (mpic_reset_prohibited(node))
1301
mpic->flags |= MPIC_NO_RESET;
1303
if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1304
printk(KERN_DEBUG "mpic: Resetting\n");
1157
1305
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1158
1306
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1159
1307
| MPIC_GREG_GCONF_RESET);
1279
1427
/* Set current processor priority to max */
1280
1428
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1282
/* Initialize timers: just disable them all */
1430
/* Initialize timers to our reserved vectors and mask them for now */
1283
1431
for (i = 0; i < 4; i++) {
1284
1432
mpic_write(mpic->tmregs,
1285
1433
i * MPIC_INFO(TIMER_STRIDE) +
1286
MPIC_INFO(TIMER_DESTINATION), 0);
1434
MPIC_INFO(TIMER_DESTINATION),
1435
1 << hard_smp_processor_id());
1287
1436
mpic_write(mpic->tmregs,
1288
1437
i * MPIC_INFO(TIMER_STRIDE) +
1289
1438
MPIC_INFO(TIMER_VECTOR_PRI),
1290
1439
MPIC_VECPRI_MASK |
1440
(9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1291
1441
(mpic->timer_vecs[0] + i));
1314
1464
mpic_pasemi_msi_init(mpic);
1316
if (mpic->flags & MPIC_PRIMARY)
1317
cpu = hard_smp_processor_id();
1466
cpu = mpic_processor_id(mpic);
1321
for (i = 0; i < mpic->num_sources; i++) {
1322
/* start with vector = source number, and masked */
1323
u32 vecpri = MPIC_VECPRI_MASK | i |
1324
(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1468
if (!(mpic->flags & MPIC_NO_RESET)) {
1469
for (i = 0; i < mpic->num_sources; i++) {
1470
/* start with vector = source number, and masked */
1471
u32 vecpri = MPIC_VECPRI_MASK | i |
1472
(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1326
/* check if protected */
1327
if (mpic->protected && test_bit(i, mpic->protected))
1330
mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1331
mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1474
/* check if protected */
1475
if (mpic->protected && test_bit(i, mpic->protected))
1478
mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1479
mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1334
1483
/* Init spurious vector */
1397
1546
~MPIC_VECPRI_PRIORITY_MASK;
1398
1547
mpic_ipi_write(src - mpic->ipi_vecs[0],
1399
1548
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1549
} else if (mpic_is_tm(mpic, irq)) {
1550
reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1551
~MPIC_VECPRI_PRIORITY_MASK;
1552
mpic_tm_write(src - mpic->timer_vecs[0],
1553
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1401
1555
reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1402
1556
& ~MPIC_VECPRI_PRIORITY_MASK;
1579
static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
1731
void smp_mpic_message_pass(int cpu, int msg)
1581
1733
struct mpic *mpic = mpic_primary;
1583
1736
BUG_ON(mpic == NULL);
1586
DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1589
mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1590
ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1591
mpic_physmask(cpumask_bits(cpu_mask)[0]));
1594
void smp_mpic_message_pass(int target, int msg)
1598
1738
/* make sure we're sending something that translates to an IPI */
1599
1739
if ((unsigned int)msg > 3) {
1600
1740
printk("SMP %d: smp_message_pass: unknown msg %d\n",
1601
1741
smp_processor_id(), msg);
1606
mpic_send_ipi(msg, cpu_online_mask);
1608
case MSG_ALL_BUT_SELF:
1609
alloc_cpumask_var(&tmp, GFP_NOWAIT);
1610
cpumask_andnot(tmp, cpu_online_mask,
1611
cpumask_of(smp_processor_id()));
1612
mpic_send_ipi(msg, tmp);
1613
free_cpumask_var(tmp);
1616
mpic_send_ipi(msg, cpumask_of(target));
1746
DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1749
physmask = 1 << get_hard_smp_processor_id(cpu);
1751
mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1752
msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1621
1755
int __init smp_mpic_probe(void)
1670
1803
mpic->save_data[i].dest =
1671
1804
mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1808
static int mpic_suspend(void)
1810
struct mpic *mpic = mpics;
1813
mpic_suspend_one(mpic);
1677
static int mpic_resume(struct sys_device *dev)
1820
static void mpic_resume_one(struct mpic *mpic)
1679
struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1682
1824
for (i = 0; i < mpic->num_sources; i++) {
1705
1847
} /* end for loop */
1711
static struct sysdev_class mpic_sysclass = {
1850
static void mpic_resume(void)
1852
struct mpic *mpic = mpics;
1855
mpic_resume_one(mpic);
1860
static struct syscore_ops mpic_syscore_ops = {
1713
1861
.resume = mpic_resume,
1714
1862
.suspend = mpic_suspend,
1719
1865
static int mpic_init_sys(void)
1721
struct mpic *mpic = mpics;
1724
error = sysdev_class_register(&mpic_sysclass);
1726
while (mpic && !error) {
1727
mpic->sysdev.cls = &mpic_sysclass;
1728
mpic->sysdev.id = id++;
1729
error = sysdev_register(&mpic->sysdev);
1867
register_syscore_ops(&mpic_syscore_ops);
1735
1871
device_initcall(mpic_init_sys);