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Viewing changes to drivers/gpu/drm/radeon/atombios_dp.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/gpu/drm/radeon/atombios_dp.c
43
43
        "0dB", "3.5dB", "6dB", "9.5dB"
44
44
};
45
45
 
46
 
static const int dp_clocks[] = {
47
 
        54000,  /* 1 lane, 1.62 Ghz */
48
 
        90000,  /* 1 lane, 2.70 Ghz */
49
 
        108000, /* 2 lane, 1.62 Ghz */
50
 
        180000, /* 2 lane, 2.70 Ghz */
51
 
        216000, /* 4 lane, 1.62 Ghz */
52
 
        360000, /* 4 lane, 2.70 Ghz */
 
46
/***** radeon AUX functions *****/
 
47
union aux_channel_transaction {
 
48
        PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
 
49
        PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
53
50
};
54
51
 
55
 
static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
56
 
 
57
 
/* common helper functions */
58
 
static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
59
 
{
60
 
        int i;
61
 
        u8 max_link_bw;
62
 
        u8 max_lane_count;
63
 
 
64
 
        if (!dpcd)
65
 
                return 0;
66
 
 
67
 
        max_link_bw = dpcd[DP_MAX_LINK_RATE];
68
 
        max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
69
 
 
70
 
        switch (max_link_bw) {
71
 
        case DP_LINK_BW_1_62:
72
 
        default:
73
 
                for (i = 0; i < num_dp_clocks; i++) {
74
 
                        if (i % 2)
75
 
                                continue;
76
 
                        switch (max_lane_count) {
77
 
                        case 1:
78
 
                                if (i > 1)
79
 
                                        return 0;
80
 
                                break;
81
 
                        case 2:
82
 
                                if (i > 3)
83
 
                                        return 0;
84
 
                                break;
85
 
                        case 4:
86
 
                        default:
87
 
                                break;
88
 
                        }
89
 
                        if (dp_clocks[i] > mode_clock) {
90
 
                                if (i < 2)
91
 
                                        return 1;
92
 
                                else if (i < 4)
93
 
                                        return 2;
94
 
                                else
95
 
                                        return 4;
96
 
                        }
97
 
                }
98
 
                break;
99
 
        case DP_LINK_BW_2_7:
100
 
                for (i = 0; i < num_dp_clocks; i++) {
101
 
                        switch (max_lane_count) {
102
 
                        case 1:
103
 
                                if (i > 1)
104
 
                                        return 0;
105
 
                                break;
106
 
                        case 2:
107
 
                                if (i > 3)
108
 
                                        return 0;
109
 
                                break;
110
 
                        case 4:
111
 
                        default:
112
 
                                break;
113
 
                        }
114
 
                        if (dp_clocks[i] > mode_clock) {
115
 
                                if (i < 2)
116
 
                                        return 1;
117
 
                                else if (i < 4)
118
 
                                        return 2;
119
 
                                else
120
 
                                        return 4;
121
 
                        }
122
 
                }
123
 
                break;
124
 
        }
125
 
 
126
 
        return 0;
127
 
}
128
 
 
129
 
static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
130
 
{
131
 
        int i;
132
 
        u8 max_link_bw;
133
 
        u8 max_lane_count;
134
 
 
135
 
        if (!dpcd)
136
 
                return 0;
137
 
 
138
 
        max_link_bw = dpcd[DP_MAX_LINK_RATE];
139
 
        max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
140
 
 
141
 
        switch (max_link_bw) {
142
 
        case DP_LINK_BW_1_62:
143
 
        default:
144
 
                for (i = 0; i < num_dp_clocks; i++) {
145
 
                        if (i % 2)
146
 
                                continue;
147
 
                        switch (max_lane_count) {
148
 
                        case 1:
149
 
                                if (i > 1)
150
 
                                        return 0;
151
 
                                break;
152
 
                        case 2:
153
 
                                if (i > 3)
154
 
                                        return 0;
155
 
                                break;
156
 
                        case 4:
157
 
                        default:
158
 
                                break;
159
 
                        }
160
 
                        if (dp_clocks[i] > mode_clock)
161
 
                                return 162000;
162
 
                }
163
 
                break;
164
 
        case DP_LINK_BW_2_7:
165
 
                for (i = 0; i < num_dp_clocks; i++) {
166
 
                        switch (max_lane_count) {
167
 
                        case 1:
168
 
                                if (i > 1)
169
 
                                        return 0;
170
 
                                break;
171
 
                        case 2:
172
 
                                if (i > 3)
173
 
                                        return 0;
174
 
                                break;
175
 
                        case 4:
176
 
                        default:
177
 
                                break;
178
 
                        }
179
 
                        if (dp_clocks[i] > mode_clock)
180
 
                                return (i % 2) ? 270000 : 162000;
181
 
                }
182
 
        }
183
 
 
184
 
        return 0;
185
 
}
186
 
 
187
 
int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
188
 
{
189
 
        int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
190
 
        int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock);
191
 
 
192
 
        if ((lanes == 0) || (dp_clock == 0))
193
 
                return MODE_CLOCK_HIGH;
194
 
 
195
 
        return MODE_OK;
196
 
}
 
52
static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
 
53
                                 u8 *send, int send_bytes,
 
54
                                 u8 *recv, int recv_size,
 
55
                                 u8 delay, u8 *ack)
 
56
{
 
57
        struct drm_device *dev = chan->dev;
 
58
        struct radeon_device *rdev = dev->dev_private;
 
59
        union aux_channel_transaction args;
 
60
        int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
 
61
        unsigned char *base;
 
62
        int recv_bytes;
 
63
 
 
64
        memset(&args, 0, sizeof(args));
 
65
 
 
66
        base = (unsigned char *)rdev->mode_info.atom_context->scratch;
 
67
 
 
68
        memcpy(base, send, send_bytes);
 
69
 
 
70
        args.v1.lpAuxRequest = 0;
 
71
        args.v1.lpDataOut = 16;
 
72
        args.v1.ucDataOutLen = 0;
 
73
        args.v1.ucChannelID = chan->rec.i2c_id;
 
74
        args.v1.ucDelay = delay / 10;
 
75
        if (ASIC_IS_DCE4(rdev))
 
76
                args.v2.ucHPD_ID = chan->rec.hpd;
 
77
 
 
78
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 
79
 
 
80
        *ack = args.v1.ucReplyStatus;
 
81
 
 
82
        /* timeout */
 
83
        if (args.v1.ucReplyStatus == 1) {
 
84
                DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 
85
                return -ETIMEDOUT;
 
86
        }
 
87
 
 
88
        /* flags not zero */
 
89
        if (args.v1.ucReplyStatus == 2) {
 
90
                DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 
91
                return -EBUSY;
 
92
        }
 
93
 
 
94
        /* error */
 
95
        if (args.v1.ucReplyStatus == 3) {
 
96
                DRM_DEBUG_KMS("dp_aux_ch error\n");
 
97
                return -EIO;
 
98
        }
 
99
 
 
100
        recv_bytes = args.v1.ucDataOutLen;
 
101
        if (recv_bytes > recv_size)
 
102
                recv_bytes = recv_size;
 
103
 
 
104
        if (recv && recv_size)
 
105
                memcpy(recv, base + 16, recv_bytes);
 
106
 
 
107
        return recv_bytes;
 
108
}
 
109
 
 
110
static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 
111
                                      u16 address, u8 *send, u8 send_bytes, u8 delay)
 
112
{
 
113
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 
114
        int ret;
 
115
        u8 msg[20];
 
116
        int msg_bytes = send_bytes + 4;
 
117
        u8 ack;
 
118
 
 
119
        if (send_bytes > 16)
 
120
                return -1;
 
121
 
 
122
        msg[0] = address;
 
123
        msg[1] = address >> 8;
 
124
        msg[2] = AUX_NATIVE_WRITE << 4;
 
125
        msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 
126
        memcpy(&msg[4], send, send_bytes);
 
127
 
 
128
        while (1) {
 
129
                ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 
130
                                            msg, msg_bytes, NULL, 0, delay, &ack);
 
131
                if (ret < 0)
 
132
                        return ret;
 
133
                if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 
134
                        break;
 
135
                else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 
136
                        udelay(400);
 
137
                else
 
138
                        return -EIO;
 
139
        }
 
140
 
 
141
        return send_bytes;
 
142
}
 
143
 
 
144
static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 
145
                                     u16 address, u8 *recv, int recv_bytes, u8 delay)
 
146
{
 
147
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 
148
        u8 msg[4];
 
149
        int msg_bytes = 4;
 
150
        u8 ack;
 
151
        int ret;
 
152
 
 
153
        msg[0] = address;
 
154
        msg[1] = address >> 8;
 
155
        msg[2] = AUX_NATIVE_READ << 4;
 
156
        msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 
157
 
 
158
        while (1) {
 
159
                ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 
160
                                            msg, msg_bytes, recv, recv_bytes, delay, &ack);
 
161
                if (ret == 0)
 
162
                        return -EPROTO;
 
163
                if (ret < 0)
 
164
                        return ret;
 
165
                if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 
166
                        return ret;
 
167
                else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 
168
                        udelay(400);
 
169
                else
 
170
                        return -EIO;
 
171
        }
 
172
}
 
173
 
 
174
static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 
175
                                 u16 reg, u8 val)
 
176
{
 
177
        radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 
178
}
 
179
 
 
180
static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 
181
                               u16 reg)
 
182
{
 
183
        u8 val = 0;
 
184
 
 
185
        radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 
186
 
 
187
        return val;
 
188
}
 
189
 
 
190
int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 
191
                         u8 write_byte, u8 *read_byte)
 
192
{
 
193
        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 
194
        struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
 
195
        u16 address = algo_data->address;
 
196
        u8 msg[5];
 
197
        u8 reply[2];
 
198
        unsigned retry;
 
199
        int msg_bytes;
 
200
        int reply_bytes = 1;
 
201
        int ret;
 
202
        u8 ack;
 
203
 
 
204
        /* Set up the command byte */
 
205
        if (mode & MODE_I2C_READ)
 
206
                msg[2] = AUX_I2C_READ << 4;
 
207
        else
 
208
                msg[2] = AUX_I2C_WRITE << 4;
 
209
 
 
210
        if (!(mode & MODE_I2C_STOP))
 
211
                msg[2] |= AUX_I2C_MOT << 4;
 
212
 
 
213
        msg[0] = address;
 
214
        msg[1] = address >> 8;
 
215
 
 
216
        switch (mode) {
 
217
        case MODE_I2C_WRITE:
 
218
                msg_bytes = 5;
 
219
                msg[3] = msg_bytes << 4;
 
220
                msg[4] = write_byte;
 
221
                break;
 
222
        case MODE_I2C_READ:
 
223
                msg_bytes = 4;
 
224
                msg[3] = msg_bytes << 4;
 
225
                break;
 
226
        default:
 
227
                msg_bytes = 4;
 
228
                msg[3] = 3 << 4;
 
229
                break;
 
230
        }
 
231
 
 
232
        for (retry = 0; retry < 4; retry++) {
 
233
                ret = radeon_process_aux_ch(auxch,
 
234
                                            msg, msg_bytes, reply, reply_bytes, 0, &ack);
 
235
                if (ret < 0) {
 
236
                        DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 
237
                        return ret;
 
238
                }
 
239
 
 
240
                switch (ack & AUX_NATIVE_REPLY_MASK) {
 
241
                case AUX_NATIVE_REPLY_ACK:
 
242
                        /* I2C-over-AUX Reply field is only valid
 
243
                         * when paired with AUX ACK.
 
244
                         */
 
245
                        break;
 
246
                case AUX_NATIVE_REPLY_NACK:
 
247
                        DRM_DEBUG_KMS("aux_ch native nack\n");
 
248
                        return -EREMOTEIO;
 
249
                case AUX_NATIVE_REPLY_DEFER:
 
250
                        DRM_DEBUG_KMS("aux_ch native defer\n");
 
251
                        udelay(400);
 
252
                        continue;
 
253
                default:
 
254
                        DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 
255
                        return -EREMOTEIO;
 
256
                }
 
257
 
 
258
                switch (ack & AUX_I2C_REPLY_MASK) {
 
259
                case AUX_I2C_REPLY_ACK:
 
260
                        if (mode == MODE_I2C_READ)
 
261
                                *read_byte = reply[0];
 
262
                        return ret;
 
263
                case AUX_I2C_REPLY_NACK:
 
264
                        DRM_DEBUG_KMS("aux_i2c nack\n");
 
265
                        return -EREMOTEIO;
 
266
                case AUX_I2C_REPLY_DEFER:
 
267
                        DRM_DEBUG_KMS("aux_i2c defer\n");
 
268
                        udelay(400);
 
269
                        break;
 
270
                default:
 
271
                        DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 
272
                        return -EREMOTEIO;
 
273
                }
 
274
        }
 
275
 
 
276
        DRM_ERROR("aux i2c too many retries, giving up\n");
 
277
        return -EREMOTEIO;
 
278
}
 
279
 
 
280
/***** general DP utility functions *****/
197
281
 
198
282
static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199
283
{
242
326
        return true;
243
327
}
244
328
 
245
 
static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 
329
static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
246
330
                                        int lane)
247
331
 
248
332
{
255
339
        return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256
340
}
257
341
 
258
 
static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 
342
static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
259
343
                                             int lane)
260
344
{
261
345
        int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
267
351
        return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268
352
}
269
353
 
270
 
/* XXX fix me -- chip specific */
271
354
#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
272
 
static u8 dp_pre_emphasis_max(u8 voltage_swing)
273
 
{
274
 
        switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275
 
        case DP_TRAIN_VOLTAGE_SWING_400:
276
 
                return DP_TRAIN_PRE_EMPHASIS_6;
277
 
        case DP_TRAIN_VOLTAGE_SWING_600:
278
 
                return DP_TRAIN_PRE_EMPHASIS_6;
279
 
        case DP_TRAIN_VOLTAGE_SWING_800:
280
 
                return DP_TRAIN_PRE_EMPHASIS_3_5;
281
 
        case DP_TRAIN_VOLTAGE_SWING_1200:
282
 
        default:
283
 
                return DP_TRAIN_PRE_EMPHASIS_0;
284
 
        }
285
 
}
 
355
#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
286
356
 
287
357
static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288
358
                                int lane_count,
308
378
        }
309
379
 
310
380
        if (v >= DP_VOLTAGE_MAX)
311
 
                v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 
381
                v |= DP_TRAIN_MAX_SWING_REACHED;
312
382
 
313
 
        if (p >= dp_pre_emphasis_max(v))
314
 
                p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
383
        if (p >= DP_PRE_EMPHASIS_MAX)
 
384
                p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315
385
 
316
386
        DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
317
387
                  voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
321
391
                train_set[lane] = v | p;
322
392
}
323
393
 
324
 
union aux_channel_transaction {
325
 
        PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
326
 
        PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
327
 
};
328
 
 
329
 
/* radeon aux chan functions */
330
 
bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
331
 
                           int num_bytes, u8 *read_byte,
332
 
                           u8 read_buf_len, u8 delay)
333
 
{
334
 
        struct drm_device *dev = chan->dev;
335
 
        struct radeon_device *rdev = dev->dev_private;
336
 
        union aux_channel_transaction args;
337
 
        int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
338
 
        unsigned char *base;
339
 
        int retry_count = 0;
340
 
 
341
 
        memset(&args, 0, sizeof(args));
342
 
 
343
 
        base = (unsigned char *)rdev->mode_info.atom_context->scratch;
344
 
 
345
 
retry:
346
 
        memcpy(base, req_bytes, num_bytes);
347
 
 
348
 
        args.v1.lpAuxRequest = 0;
349
 
        args.v1.lpDataOut = 16;
350
 
        args.v1.ucDataOutLen = 0;
351
 
        args.v1.ucChannelID = chan->rec.i2c_id;
352
 
        args.v1.ucDelay = delay / 10;
353
 
        if (ASIC_IS_DCE4(rdev))
354
 
                args.v2.ucHPD_ID = chan->rec.hpd;
355
 
 
356
 
        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
357
 
 
358
 
        if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) {
359
 
                if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10)
360
 
                        goto retry;
361
 
                DRM_DEBUG_KMS("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
362
 
                          req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
363
 
                          chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count);
364
 
                return false;
365
 
        }
366
 
 
367
 
        if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
368
 
                if (read_buf_len < args.v1.ucDataOutLen) {
369
 
                        DRM_ERROR("Buffer to small for return answer %d %d\n",
370
 
                                  read_buf_len, args.v1.ucDataOutLen);
371
 
                        return false;
372
 
                }
373
 
                {
374
 
                        int len = min(read_buf_len, args.v1.ucDataOutLen);
375
 
                        memcpy(read_byte, base + 16, len);
376
 
                }
377
 
        }
378
 
        return true;
379
 
}
380
 
 
381
 
bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
382
 
                                uint8_t send_bytes, uint8_t *send)
383
 
{
384
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
385
 
        u8 msg[20];
386
 
        u8 msg_len, dp_msg_len;
387
 
        bool ret;
388
 
 
389
 
        dp_msg_len = 4;
390
 
        msg[0] = address;
391
 
        msg[1] = address >> 8;
392
 
        msg[2] = AUX_NATIVE_WRITE << 4;
393
 
        dp_msg_len += send_bytes;
394
 
        msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
395
 
 
396
 
        if (send_bytes > 16)
397
 
                return false;
398
 
 
399
 
        memcpy(&msg[4], send, send_bytes);
400
 
        msg_len = 4 + send_bytes;
401
 
        ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
402
 
        return ret;
403
 
}
404
 
 
405
 
bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
406
 
                               uint8_t delay, uint8_t expected_bytes,
407
 
                               uint8_t *read_p)
408
 
{
409
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
410
 
        u8 msg[20];
411
 
        u8 msg_len, dp_msg_len;
412
 
        bool ret = false;
413
 
        msg_len = 4;
414
 
        dp_msg_len = 4;
415
 
        msg[0] = address;
416
 
        msg[1] = address >> 8;
417
 
        msg[2] = AUX_NATIVE_READ << 4;
418
 
        msg[3] = (dp_msg_len) << 4;
419
 
        msg[3] |= expected_bytes - 1;
420
 
 
421
 
        ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
422
 
        return ret;
423
 
}
424
 
 
425
 
/* radeon dp functions */
426
 
static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
427
 
                                    uint8_t ucconfig, uint8_t lane_num)
 
394
/* convert bits per color to bits per pixel */
 
395
/* get bpc from the EDID */
 
396
static int convert_bpc_to_bpp(int bpc)
 
397
{
 
398
        if (bpc == 0)
 
399
                return 24;
 
400
        else
 
401
                return bpc * 3;
 
402
}
 
403
 
 
404
/* get the max pix clock supported by the link rate and lane num */
 
405
static int dp_get_max_dp_pix_clock(int link_rate,
 
406
                                   int lane_num,
 
407
                                   int bpp)
 
408
{
 
409
        return (link_rate * lane_num * 8) / bpp;
 
410
}
 
411
 
 
412
static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
 
413
{
 
414
        switch (dpcd[DP_MAX_LINK_RATE]) {
 
415
        case DP_LINK_BW_1_62:
 
416
        default:
 
417
                return 162000;
 
418
        case DP_LINK_BW_2_7:
 
419
                return 270000;
 
420
        case DP_LINK_BW_5_4:
 
421
                return 540000;
 
422
        }
 
423
}
 
424
 
 
425
static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
 
426
{
 
427
        return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
 
428
}
 
429
 
 
430
static u8 dp_get_dp_link_rate_coded(int link_rate)
 
431
{
 
432
        switch (link_rate) {
 
433
        case 162000:
 
434
        default:
 
435
                return DP_LINK_BW_1_62;
 
436
        case 270000:
 
437
                return DP_LINK_BW_2_7;
 
438
        case 540000:
 
439
                return DP_LINK_BW_5_4;
 
440
        }
 
441
}
 
442
 
 
443
/***** radeon specific DP functions *****/
 
444
 
 
445
/* First get the min lane# when low rate is used according to pixel clock
 
446
 * (prefer low rate), second check max lane# supported by DP panel,
 
447
 * if the max lane# < low rate lane# then use max lane# instead.
 
448
 */
 
449
static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 
450
                                        u8 dpcd[DP_DPCD_SIZE],
 
451
                                        int pix_clock)
 
452
{
 
453
        int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
 
454
        int max_link_rate = dp_get_max_link_rate(dpcd);
 
455
        int max_lane_num = dp_get_max_lane_number(dpcd);
 
456
        int lane_num;
 
457
        int max_dp_pix_clock;
 
458
 
 
459
        for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 
460
                max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 
461
                if (pix_clock <= max_dp_pix_clock)
 
462
                        break;
 
463
        }
 
464
 
 
465
        return lane_num;
 
466
}
 
467
 
 
468
static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 
469
                                       u8 dpcd[DP_DPCD_SIZE],
 
470
                                       int pix_clock)
 
471
{
 
472
        int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
 
473
        int lane_num, max_pix_clock;
 
474
 
 
475
        if (radeon_connector_encoder_is_dp_bridge(connector))
 
476
                return 270000;
 
477
 
 
478
        lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 
479
        max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 
480
        if (pix_clock <= max_pix_clock)
 
481
                return 162000;
 
482
        max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 
483
        if (pix_clock <= max_pix_clock)
 
484
                return 270000;
 
485
        if (radeon_connector_is_dp12_capable(connector)) {
 
486
                max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 
487
                if (pix_clock <= max_pix_clock)
 
488
                        return 540000;
 
489
        }
 
490
 
 
491
        return dp_get_max_link_rate(dpcd);
 
492
}
 
493
 
 
494
static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 
495
                                    int action, int dp_clock,
 
496
                                    u8 ucconfig, u8 lane_num)
428
497
{
429
498
        DP_ENCODER_SERVICE_PARAMETERS args;
430
499
        int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
454
523
{
455
524
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
456
525
        u8 msg[25];
457
 
        int ret;
 
526
        int ret, i;
458
527
 
459
 
        ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
460
 
        if (ret) {
 
528
        ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
 
529
        if (ret > 0) {
461
530
                memcpy(dig_connector->dpcd, msg, 8);
462
 
                {
463
 
                        int i;
464
 
                        DRM_DEBUG_KMS("DPCD: ");
465
 
                        for (i = 0; i < 8; i++)
466
 
                                DRM_DEBUG_KMS("%02x ", msg[i]);
467
 
                        DRM_DEBUG_KMS("\n");
468
 
                }
 
531
                DRM_DEBUG_KMS("DPCD: ");
 
532
                for (i = 0; i < 8; i++)
 
533
                        DRM_DEBUG_KMS("%02x ", msg[i]);
 
534
                DRM_DEBUG_KMS("\n");
469
535
                return true;
470
536
        }
471
537
        dig_connector->dpcd[0] = 0;
472
538
        return false;
473
539
}
474
540
 
 
541
static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
 
542
                                     struct drm_connector *connector)
 
543
{
 
544
        struct drm_device *dev = encoder->dev;
 
545
        struct radeon_device *rdev = dev->dev_private;
 
546
        int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 
547
 
 
548
        if (!ASIC_IS_DCE4(rdev))
 
549
                return;
 
550
 
 
551
        if (radeon_connector_encoder_is_dp_bridge(connector))
 
552
                panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 
553
 
 
554
        atombios_dig_encoder_setup(encoder,
 
555
                                   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
 
556
                                   panel_mode);
 
557
}
 
558
 
475
559
void radeon_dp_set_link_config(struct drm_connector *connector,
476
560
                               struct drm_display_mode *mode)
477
561
{
478
 
        struct radeon_connector *radeon_connector;
 
562
        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
479
563
        struct radeon_connector_atom_dig *dig_connector;
480
564
 
481
 
        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
482
 
            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
483
 
                return;
484
 
 
485
 
        radeon_connector = to_radeon_connector(connector);
486
565
        if (!radeon_connector->con_priv)
487
566
                return;
488
567
        dig_connector = radeon_connector->con_priv;
489
568
 
490
 
        dig_connector->dp_clock =
491
 
                dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
492
 
        dig_connector->dp_lane_count =
493
 
                dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
 
569
        if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 
570
            (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 
571
                dig_connector->dp_clock =
 
572
                        radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 
573
                dig_connector->dp_lane_count =
 
574
                        radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 
575
        }
494
576
}
495
577
 
496
 
int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
 
578
int radeon_dp_mode_valid_helper(struct drm_connector *connector,
497
579
                                struct drm_display_mode *mode)
498
580
{
499
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
500
 
 
501
 
        return dp_mode_valid(dig_connector->dpcd, mode->clock);
 
581
        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 
582
        struct radeon_connector_atom_dig *dig_connector;
 
583
        int dp_clock;
 
584
 
 
585
        if (!radeon_connector->con_priv)
 
586
                return MODE_CLOCK_HIGH;
 
587
        dig_connector = radeon_connector->con_priv;
 
588
 
 
589
        dp_clock =
 
590
                radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 
591
 
 
592
        if ((dp_clock == 540000) &&
 
593
            (!radeon_connector_is_dp12_capable(connector)))
 
594
                return MODE_CLOCK_HIGH;
 
595
 
 
596
        return MODE_OK;
502
597
}
503
598
 
504
 
static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
505
 
                                    u8 link_status[DP_LINK_STATUS_SIZE])
 
599
static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 
600
                                      u8 link_status[DP_LINK_STATUS_SIZE])
506
601
{
507
602
        int ret;
508
 
        ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
509
 
                                        DP_LINK_STATUS_SIZE, link_status);
510
 
        if (!ret) {
 
603
        ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 
604
                                        link_status, DP_LINK_STATUS_SIZE, 100);
 
605
        if (ret <= 0) {
511
606
                DRM_ERROR("displayport link status failed\n");
512
607
                return false;
513
608
        }
518
613
        return true;
519
614
}
520
615
 
521
 
bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
522
 
{
523
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
524
 
        u8 link_status[DP_LINK_STATUS_SIZE];
525
 
 
526
 
        if (!atom_dp_get_link_status(radeon_connector, link_status))
527
 
                return false;
528
 
        if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
529
 
                return false;
530
 
        return true;
531
 
}
532
 
 
533
 
static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
534
 
{
535
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
536
 
 
537
 
        if (dig_connector->dpcd[0] >= 0x11) {
538
 
                radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
539
 
                                           &power_state);
540
 
        }
541
 
}
542
 
 
543
 
static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
544
 
{
545
 
        radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
546
 
                                   &downspread);
547
 
}
548
 
 
549
 
static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
550
 
                                 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
551
 
{
552
 
        radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
553
 
                                   link_configuration);
554
 
}
555
 
 
556
 
static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
557
 
                                struct drm_encoder *encoder,
558
 
                                u8 train_set[4])
559
 
{
560
 
        struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
561
 
        int i;
562
 
 
563
 
        for (i = 0; i < dig_connector->dp_lane_count; i++)
564
 
                atombios_dig_transmitter_setup(encoder,
565
 
                                               ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
566
 
                                               i, train_set[i]);
567
 
 
568
 
        radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
569
 
                                   dig_connector->dp_lane_count, train_set);
570
 
}
571
 
 
572
 
static void dp_set_training(struct radeon_connector *radeon_connector,
573
 
                            u8 training)
574
 
{
575
 
        radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
576
 
                                   1, &training);
577
 
}
578
 
 
579
 
void dp_link_train(struct drm_encoder *encoder,
580
 
                   struct drm_connector *connector)
581
 
{
582
 
        struct drm_device *dev = encoder->dev;
583
 
        struct radeon_device *rdev = dev->dev_private;
584
 
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
585
 
        struct radeon_encoder_atom_dig *dig;
 
616
struct radeon_dp_link_train_info {
 
617
        struct radeon_device *rdev;
 
618
        struct drm_encoder *encoder;
 
619
        struct drm_connector *connector;
586
620
        struct radeon_connector *radeon_connector;
587
 
        struct radeon_connector_atom_dig *dig_connector;
588
 
        int enc_id = 0;
589
 
        bool clock_recovery, channel_eq;
590
 
        u8 link_status[DP_LINK_STATUS_SIZE];
591
 
        u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
592
 
        u8 tries, voltage;
 
621
        int enc_id;
 
622
        int dp_clock;
 
623
        int dp_lane_count;
 
624
        int rd_interval;
 
625
        bool tp3_supported;
 
626
        u8 dpcd[8];
593
627
        u8 train_set[4];
594
 
        int i;
595
 
 
596
 
        if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
597
 
            (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
598
 
                return;
599
 
 
600
 
        if (!radeon_encoder->enc_priv)
601
 
                return;
602
 
        dig = radeon_encoder->enc_priv;
603
 
 
604
 
        radeon_connector = to_radeon_connector(connector);
605
 
        if (!radeon_connector->con_priv)
606
 
                return;
607
 
        dig_connector = radeon_connector->con_priv;
608
 
 
609
 
        if (dig->dig_encoder)
610
 
                enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
611
 
        else
612
 
                enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
613
 
        if (dig->linkb)
614
 
                enc_id |= ATOM_DP_CONFIG_LINK_B;
615
 
        else
616
 
                enc_id |= ATOM_DP_CONFIG_LINK_A;
617
 
 
618
 
        memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
619
 
        if (dig_connector->dp_clock == 270000)
620
 
                link_configuration[0] = DP_LINK_BW_2_7;
621
 
        else
622
 
                link_configuration[0] = DP_LINK_BW_1_62;
623
 
        link_configuration[1] = dig_connector->dp_lane_count;
624
 
        if (dig_connector->dpcd[0] >= 0x11)
625
 
                link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 
628
        u8 link_status[DP_LINK_STATUS_SIZE];
 
629
        u8 tries;
 
630
};
 
631
 
 
632
static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 
633
{
 
634
        /* set the initial vs/emph on the source */
 
635
        atombios_dig_transmitter_setup(dp_info->encoder,
 
636
                                       ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 
637
                                       0, dp_info->train_set[0]); /* sets all lanes at once */
 
638
 
 
639
        /* set the vs/emph on the sink */
 
640
        radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 
641
                                   dp_info->train_set, dp_info->dp_lane_count, 0);
 
642
}
 
643
 
 
644
static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 
645
{
 
646
        int rtp = 0;
 
647
 
 
648
        /* set training pattern on the source */
 
649
        if (ASIC_IS_DCE4(dp_info->rdev)) {
 
650
                switch (tp) {
 
651
                case DP_TRAINING_PATTERN_1:
 
652
                        rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 
653
                        break;
 
654
                case DP_TRAINING_PATTERN_2:
 
655
                        rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 
656
                        break;
 
657
                case DP_TRAINING_PATTERN_3:
 
658
                        rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 
659
                        break;
 
660
                }
 
661
                atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 
662
        } else {
 
663
                switch (tp) {
 
664
                case DP_TRAINING_PATTERN_1:
 
665
                        rtp = 0;
 
666
                        break;
 
667
                case DP_TRAINING_PATTERN_2:
 
668
                        rtp = 1;
 
669
                        break;
 
670
                }
 
671
                radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 
672
                                          dp_info->dp_clock, dp_info->enc_id, rtp);
 
673
        }
 
674
 
 
675
        /* enable training pattern on the sink */
 
676
        radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 
677
}
 
678
 
 
679
static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 
680
{
 
681
        u8 tmp;
626
682
 
627
683
        /* power up the sink */
628
 
        dp_set_power(radeon_connector, DP_SET_POWER_D0);
629
 
        /* disable the training pattern on the sink */
630
 
        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
631
 
        /* set link bw and lanes on the sink */
632
 
        dp_set_link_bw_lanes(radeon_connector, link_configuration);
633
 
        /* disable downspread on the sink */
634
 
        dp_set_downspread(radeon_connector, 0);
635
 
        if (ASIC_IS_DCE4(rdev)) {
636
 
                /* start training on the source */
637
 
                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
638
 
                /* set training pattern 1 on the source */
639
 
                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
640
 
        } else {
641
 
                /* start training on the source */
642
 
                radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
643
 
                                          dig_connector->dp_clock, enc_id, 0);
644
 
                /* set training pattern 1 on the source */
645
 
                radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
646
 
                                          dig_connector->dp_clock, enc_id, 0);
647
 
        }
648
 
 
649
 
        /* set initial vs/emph */
650
 
        memset(train_set, 0, 4);
651
 
        udelay(400);
652
 
        /* set training pattern 1 on the sink */
653
 
        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
654
 
 
655
 
        dp_update_dpvs_emph(radeon_connector, encoder, train_set);
 
684
        if (dp_info->dpcd[0] >= 0x11)
 
685
                radeon_write_dpcd_reg(dp_info->radeon_connector,
 
686
                                      DP_SET_POWER, DP_SET_POWER_D0);
 
687
 
 
688
        /* possibly enable downspread on the sink */
 
689
        if (dp_info->dpcd[3] & 0x1)
 
690
                radeon_write_dpcd_reg(dp_info->radeon_connector,
 
691
                                      DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 
692
        else
 
693
                radeon_write_dpcd_reg(dp_info->radeon_connector,
 
694
                                      DP_DOWNSPREAD_CTRL, 0);
 
695
 
 
696
        radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector);
 
697
 
 
698
        /* set the lane count on the sink */
 
699
        tmp = dp_info->dp_lane_count;
 
700
        if (dp_info->dpcd[0] >= 0x11)
 
701
                tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 
702
        radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 
703
 
 
704
        /* set the link rate on the sink */
 
705
        tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
 
706
        radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 
707
 
 
708
        /* start training on the source */
 
709
        if (ASIC_IS_DCE4(dp_info->rdev))
 
710
                atombios_dig_encoder_setup(dp_info->encoder,
 
711
                                           ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 
712
        else
 
713
                radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 
714
                                          dp_info->dp_clock, dp_info->enc_id, 0);
 
715
 
 
716
        /* disable the training pattern on the sink */
 
717
        radeon_write_dpcd_reg(dp_info->radeon_connector,
 
718
                              DP_TRAINING_PATTERN_SET,
 
719
                              DP_TRAINING_PATTERN_DISABLE);
 
720
 
 
721
        return 0;
 
722
}
 
723
 
 
724
static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 
725
{
 
726
        udelay(400);
 
727
 
 
728
        /* disable the training pattern on the sink */
 
729
        radeon_write_dpcd_reg(dp_info->radeon_connector,
 
730
                              DP_TRAINING_PATTERN_SET,
 
731
                              DP_TRAINING_PATTERN_DISABLE);
 
732
 
 
733
        /* disable the training pattern on the source */
 
734
        if (ASIC_IS_DCE4(dp_info->rdev))
 
735
                atombios_dig_encoder_setup(dp_info->encoder,
 
736
                                           ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 
737
        else
 
738
                radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 
739
                                          dp_info->dp_clock, dp_info->enc_id, 0);
 
740
 
 
741
        return 0;
 
742
}
 
743
 
 
744
static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 
745
{
 
746
        bool clock_recovery;
 
747
        u8 voltage;
 
748
        int i;
 
749
 
 
750
        radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 
751
        memset(dp_info->train_set, 0, 4);
 
752
        radeon_dp_update_vs_emph(dp_info);
 
753
 
 
754
        udelay(400);
656
755
 
657
756
        /* clock recovery loop */
658
757
        clock_recovery = false;
659
 
        tries = 0;
 
758
        dp_info->tries = 0;
660
759
        voltage = 0xff;
661
 
        for (;;) {
662
 
                udelay(100);
663
 
                if (!atom_dp_get_link_status(radeon_connector, link_status))
 
760
        while (1) {
 
761
                if (dp_info->rd_interval == 0)
 
762
                        udelay(100);
 
763
                else
 
764
                        mdelay(dp_info->rd_interval * 4);
 
765
 
 
766
                if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
664
767
                        break;
665
768
 
666
 
                if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
 
769
                if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
667
770
                        clock_recovery = true;
668
771
                        break;
669
772
                }
670
773
 
671
 
                for (i = 0; i < dig_connector->dp_lane_count; i++) {
672
 
                        if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 
774
                for (i = 0; i < dp_info->dp_lane_count; i++) {
 
775
                        if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
673
776
                                break;
674
777
                }
675
 
                if (i == dig_connector->dp_lane_count) {
 
778
                if (i == dp_info->dp_lane_count) {
676
779
                        DRM_ERROR("clock recovery reached max voltage\n");
677
780
                        break;
678
781
                }
679
782
 
680
 
                if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
681
 
                        ++tries;
682
 
                        if (tries == 5) {
 
783
                if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 
784
                        ++dp_info->tries;
 
785
                        if (dp_info->tries == 5) {
683
786
                                DRM_ERROR("clock recovery tried 5 times\n");
684
787
                                break;
685
788
                        }
686
789
                } else
687
 
                        tries = 0;
 
790
                        dp_info->tries = 0;
688
791
 
689
 
                voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
792
                voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
690
793
 
691
794
                /* Compute new train_set as requested by sink */
692
 
                dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
693
 
                dp_update_dpvs_emph(radeon_connector, encoder, train_set);
 
795
                dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 
796
 
 
797
                radeon_dp_update_vs_emph(dp_info);
694
798
        }
695
 
        if (!clock_recovery)
 
799
        if (!clock_recovery) {
696
800
                DRM_ERROR("clock recovery failed\n");
697
 
        else
 
801
                return -1;
 
802
        } else {
698
803
                DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
699
 
                          train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
700
 
                          (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 
804
                          dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 
805
                          (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
701
806
                          DP_TRAIN_PRE_EMPHASIS_SHIFT);
702
 
 
703
 
 
704
 
        /* set training pattern 2 on the sink */
705
 
        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
706
 
        /* set training pattern 2 on the source */
707
 
        if (ASIC_IS_DCE4(rdev))
708
 
                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
 
807
                return 0;
 
808
        }
 
809
}
 
810
 
 
811
static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 
812
{
 
813
        bool channel_eq;
 
814
 
 
815
        if (dp_info->tp3_supported)
 
816
                radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
709
817
        else
710
 
                radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
711
 
                                          dig_connector->dp_clock, enc_id, 1);
 
818
                radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
712
819
 
713
820
        /* channel equalization loop */
714
 
        tries = 0;
 
821
        dp_info->tries = 0;
715
822
        channel_eq = false;
716
 
        for (;;) {
717
 
                udelay(400);
718
 
                if (!atom_dp_get_link_status(radeon_connector, link_status))
 
823
        while (1) {
 
824
                if (dp_info->rd_interval == 0)
 
825
                        udelay(400);
 
826
                else
 
827
                        mdelay(dp_info->rd_interval * 4);
 
828
 
 
829
                if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
719
830
                        break;
720
831
 
721
 
                if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
 
832
                if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
722
833
                        channel_eq = true;
723
834
                        break;
724
835
                }
725
836
 
726
837
                /* Try 5 times */
727
 
                if (tries > 5) {
 
838
                if (dp_info->tries > 5) {
728
839
                        DRM_ERROR("channel eq failed: 5 tries\n");
729
840
                        break;
730
841
                }
731
842
 
732
843
                /* Compute new train_set as requested by sink */
733
 
                dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
734
 
                dp_update_dpvs_emph(radeon_connector, encoder, train_set);
 
844
                dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
735
845
 
736
 
                tries++;
 
846
                radeon_dp_update_vs_emph(dp_info);
 
847
                dp_info->tries++;
737
848
        }
738
849
 
739
 
        if (!channel_eq)
 
850
        if (!channel_eq) {
740
851
                DRM_ERROR("channel eq failed\n");
741
 
        else
 
852
                return -1;
 
853
        } else {
742
854
                DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
743
 
                          train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
744
 
                          (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 
855
                          dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 
856
                          (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
745
857
                          >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
746
 
 
747
 
        /* disable the training pattern on the sink */
748
 
        dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
749
 
 
750
 
        /* disable the training pattern on the source */
751
 
        if (ASIC_IS_DCE4(rdev))
752
 
                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
753
 
        else
754
 
                radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
755
 
                                          dig_connector->dp_clock, enc_id, 0);
 
858
                return 0;
 
859
        }
756
860
}
757
861
 
758
 
int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
759
 
                         uint8_t write_byte, uint8_t *read_byte)
 
862
void radeon_dp_link_train(struct drm_encoder *encoder,
 
863
                          struct drm_connector *connector)
760
864
{
761
 
        struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
762
 
        struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
763
 
        int ret = 0;
764
 
        uint16_t address = algo_data->address;
765
 
        uint8_t msg[5];
766
 
        uint8_t reply[2];
767
 
        int msg_len, dp_msg_len;
768
 
        int reply_bytes;
769
 
 
770
 
        /* Set up the command byte */
771
 
        if (mode & MODE_I2C_READ)
772
 
                msg[2] = AUX_I2C_READ << 4;
773
 
        else
774
 
                msg[2] = AUX_I2C_WRITE << 4;
775
 
 
776
 
        if (!(mode & MODE_I2C_STOP))
777
 
                msg[2] |= AUX_I2C_MOT << 4;
778
 
 
779
 
        msg[0] = address;
780
 
        msg[1] = address >> 8;
781
 
 
782
 
        reply_bytes = 1;
783
 
 
784
 
        msg_len = 4;
785
 
        dp_msg_len = 3;
786
 
        switch (mode) {
787
 
        case MODE_I2C_WRITE:
788
 
                msg[4] = write_byte;
789
 
                msg_len++;
790
 
                dp_msg_len += 2;
791
 
                break;
792
 
        case MODE_I2C_READ:
793
 
                dp_msg_len += 1;
794
 
                break;
795
 
        default:
796
 
                break;
797
 
        }
798
 
 
799
 
        msg[3] = (dp_msg_len) << 4;
800
 
        ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
801
 
 
802
 
        if (ret) {
803
 
                if (read_byte)
804
 
                        *read_byte = reply[0];
805
 
                return reply_bytes;
806
 
        }
807
 
        return -EREMOTEIO;
 
865
        struct drm_device *dev = encoder->dev;
 
866
        struct radeon_device *rdev = dev->dev_private;
 
867
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 
868
        struct radeon_encoder_atom_dig *dig;
 
869
        struct radeon_connector *radeon_connector;
 
870
        struct radeon_connector_atom_dig *dig_connector;
 
871
        struct radeon_dp_link_train_info dp_info;
 
872
        u8 tmp;
 
873
 
 
874
        if (!radeon_encoder->enc_priv)
 
875
                return;
 
876
        dig = radeon_encoder->enc_priv;
 
877
 
 
878
        radeon_connector = to_radeon_connector(connector);
 
879
        if (!radeon_connector->con_priv)
 
880
                return;
 
881
        dig_connector = radeon_connector->con_priv;
 
882
 
 
883
        if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 
884
            (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 
885
                return;
 
886
 
 
887
        dp_info.enc_id = 0;
 
888
        if (dig->dig_encoder)
 
889
                dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 
890
        else
 
891
                dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 
892
        if (dig->linkb)
 
893
                dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 
894
        else
 
895
                dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 
896
 
 
897
        dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
 
898
        tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 
899
        if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 
900
                dp_info.tp3_supported = true;
 
901
        else
 
902
                dp_info.tp3_supported = false;
 
903
 
 
904
        memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
 
905
        dp_info.rdev = rdev;
 
906
        dp_info.encoder = encoder;
 
907
        dp_info.connector = connector;
 
908
        dp_info.radeon_connector = radeon_connector;
 
909
        dp_info.dp_lane_count = dig_connector->dp_lane_count;
 
910
        dp_info.dp_clock = dig_connector->dp_clock;
 
911
 
 
912
        if (radeon_dp_link_train_init(&dp_info))
 
913
                goto done;
 
914
        if (radeon_dp_link_train_cr(&dp_info))
 
915
                goto done;
 
916
        if (radeon_dp_link_train_ce(&dp_info))
 
917
                goto done;
 
918
done:
 
919
        if (radeon_dp_link_train_finish(&dp_info))
 
920
                return;
808
921
}
809