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Viewing changes to drivers/gpu/drm/radeon/evergreend.h

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
drivers/gpu/drm/radeon/evergreend.h
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#define GB_BACKEND_MAP                                  0x98FC
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#define DMIF_ADDR_CONFIG                                0xBD4
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#define HDP_ADDR_CONFIG                                 0x2F48
 
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#define HDP_MISC_CNTL                                   0x2F4C
 
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#define         HDP_FLUSH_INVALIDATE_CACHE              (1 << 0)
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#define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
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#define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
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#define         SE_DB_BUSY                                      (1 << 30)
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#define         SE_CB_BUSY                                      (1 << 31)
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/* evergreen */
 
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#define CG_THERMAL_CTRL                                 0x72c
 
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#define         TOFFSET_MASK                            0x00003FE0
 
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#define         TOFFSET_SHIFT                           5
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#define CG_MULT_THERMAL_STATUS                          0x740
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#define         ASIC_T(x)                               ((x) << 16)
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#define         ASIC_T_MASK                             0x7FF0000
 
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#define         ASIC_T_MASK                             0x07FF0000
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#define         ASIC_T_SHIFT                            16
 
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#define CG_TS0_STATUS                                   0x760
 
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#define         TS0_ADC_DOUT_MASK                       0x000003FF
 
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#define         TS0_ADC_DOUT_SHIFT                      0
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/* APU */
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#define CG_THERMAL_STATUS                               0x678
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#define         BURSTLENGTH_SHIFT                               9
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#define         BURSTLENGTH_MASK                                0x00000200
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#define         CHANSIZE_OVERRIDE                               (1 << 11)
 
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#define FUS_MC_ARB_RAMCFG                               0x2768
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#define MC_VM_AGP_TOP                                   0x2028
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#define MC_VM_AGP_BOT                                   0x202C
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#define MC_VM_AGP_BASE                                  0x2030
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#define MC_VM_MD_L1_TLB0_CNTL                           0x2654
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#define MC_VM_MD_L1_TLB1_CNTL                           0x2658
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#define MC_VM_MD_L1_TLB2_CNTL                           0x265C
 
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#define FUS_MC_VM_MD_L1_TLB0_CNTL                       0x265C
 
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#define FUS_MC_VM_MD_L1_TLB1_CNTL                       0x2660
 
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#define FUS_MC_VM_MD_L1_TLB2_CNTL                       0x2664
 
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#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
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#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
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#define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
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#define IH_RB_WPTR_ADDR_LO                                0x3e14
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#define IH_CNTL                                           0x3e18
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#       define ENABLE_INTR                                (1 << 0)
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#       define IH_MC_SWAP(x)                              ((x) << 2)
 
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#       define IH_MC_SWAP(x)                              ((x) << 1)
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#       define IH_MC_SWAP_NONE                            0
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#       define IH_MC_SWAP_16BIT                           1
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#       define IH_MC_SWAP_32BIT                           2
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#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
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#       define DC_HPD5_INTERRUPT                        (1 << 17)
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#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
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#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6050
 
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#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
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#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
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#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
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#       define DC_HPD6_INTERRUPT                        (1 << 17)
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#define SQ_CONST_MEM_BASE                               0x8df8
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#define SQ_ESGS_RING_BASE                               0x8c40
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#define SQ_ESGS_RING_SIZE                               0x8c44
 
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#define SQ_GSVS_RING_BASE                               0x8c48
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#define SQ_GSVS_RING_SIZE                               0x8c4c
 
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#define SQ_ESTMP_RING_BASE                              0x8c50
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#define SQ_ESTMP_RING_SIZE                              0x8c54
 
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#define SQ_GSTMP_RING_BASE                              0x8c58
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#define SQ_GSTMP_RING_SIZE                              0x8c5c
 
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#define SQ_VSTMP_RING_BASE                              0x8c60
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#define SQ_VSTMP_RING_SIZE                              0x8c64
 
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#define SQ_PSTMP_RING_BASE                              0x8c68
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#define SQ_PSTMP_RING_SIZE                              0x8c6c
 
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#define SQ_LSTMP_RING_BASE                              0x8e10
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#define SQ_LSTMP_RING_SIZE                              0x8e14
 
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#define SQ_HSTMP_RING_BASE                              0x8e18
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#define SQ_HSTMP_RING_SIZE                              0x8e1c
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#define VGT_TF_RING_SIZE                                0x8988
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#define SQ_TEX_RESOURCE_WORD6_0                         0x30018
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#define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
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/* cayman 3D regs */
 
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#define CAYMAN_VGT_OFFCHIP_LDS_BASE                     0x89B0
 
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#define CAYMAN_DB_EQAA                                  0x28804
 
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#define CAYMAN_DB_DEPTH_INFO                            0x2803C
 
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#define CAYMAN_PA_SC_AA_CONFIG                          0x28BE0
 
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#define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0
 
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#define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7
 
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/* cayman packet3 addition */
 
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#define CAYMAN_PACKET3_DEALLOC_STATE                    0x14
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#endif