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Viewing changes to arch/arm/mach-mxs/clock-mx28.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/arm/mach-mxs/clock-mx28.c
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        unsigned long diff, parent_rate, calc_rate;                     \
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        int i;                                                          \
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                                                                        \
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        parent_rate = clk_get_rate(clk->parent);                        \
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        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
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        bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
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                                                                        \
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        if (clk->parent == &ref_xtal_clk) {                             \
 
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                parent_rate = clk_get_rate(clk->parent);                \
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                div = DIV_ROUND_UP(parent_rate, rate);                  \
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                if (clk == &cpu_clk) {                                  \
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                        div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
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                if (div == 0 || div > div_max)                          \
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                        return -EINVAL;                                 \
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        } else {                                                        \
 
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                /*                                                      \
 
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                 * hack alert: this block modifies clk->parent, too,    \
 
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                 * so the base to use it the grand parent.              \
 
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                 */                                                     \
 
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                parent_rate = clk_get_rate(clk->parent->parent);        \
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                rate >>= PARENT_RATE_SHIFT;                             \
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                parent_rate >>= PARENT_RATE_SHIFT;                      \
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                diff = parent_rate;                                     \
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        _REGISTER_CLOCK("pll2", NULL, pll2_clk)
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        _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
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        _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
 
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        _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
 
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        _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
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        _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
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        _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
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        _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
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        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
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        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
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        /*
 
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         * 480 MHz seems too high to be ssp clock source directly,
 
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         * so set frac0 to get a 288 MHz ref_io0.
 
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         */
 
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        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 
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        reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
 
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        reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
 
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        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 
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        return 0;
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}
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{
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        clk_misc_init();
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        /*
 
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         * source ssp clock from ref_io0 than ref_xtal,
 
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         * as ref_xtal only provides 24 MHz as maximum.
 
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         */
 
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        clk_set_parent(&ssp0_clk, &ref_io0_clk);
 
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        clk_set_parent(&ssp1_clk, &ref_io0_clk);
 
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        clk_enable(&cpu_clk);
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        clk_enable(&hbus_clk);
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        clk_enable(&xbus_clk);