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Viewing changes to arch/arm/mach-omap2/omap4-common.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/mach-omap2/omap4-common.c
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#include <mach/hardware.h>
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#include <mach/omap4-common.h>
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#include "omap4-sar-layout.h"
 
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#ifdef CONFIG_CACHE_L2X0
 
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#define L2X0_POR_OFFSET_VALUE           0x9
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void __iomem *l2cache_base;
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#endif
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void __iomem *gic_dist_base_addr;
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static void __iomem *gic_cpu_base;
 
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static void __iomem *sar_ram_base;
 
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void __iomem *omap4_get_gic_dist_base(void)
 
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{
 
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        return gic_dist_base_addr;
 
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}
 
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void __iomem *omap4_get_gic_cpu_base(void)
 
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{
 
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        return gic_cpu_base;
 
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}
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void __init gic_init_irq(void)
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{
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        void __iomem *gic_cpu_base;
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        /* Static mapping, never released */
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        gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *omap4_get_l2cache_base(void)
 
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{
 
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        return l2cache_base;
 
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}
 
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static void omap4_l2x0_disable(void)
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{
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        /* Disable PL310 L2 Cache controller */
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static int __init omap_l2_cache_init(void)
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{
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        u32 aux_ctrl = 0;
 
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        u32 por_ctrl = 0;
 
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        u32 lockdown = 0;
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        /*
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         * To avoid code running on other OMAPs in
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         * Way size - 32KB (es1.0)
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         * Way size - 64KB (es2.0 +)
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         */
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        aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
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                        (0x1 << 25) |
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                        (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
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                        (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
 
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        aux_ctrl = readl_relaxed(l2cache_base + L2X0_AUX_CTRL);
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        if (omap_rev() == OMAP4430_REV_ES1_0) {
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                aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
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        } else {
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                aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
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                        (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
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                        (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
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                        (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
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                        (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
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        }
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        if (omap_rev() != OMAP4430_REV_ES1_0)
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                omap_smc1(0x109, aux_ctrl);
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                goto skip_aux_por_api;
 
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        }
 
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        /*
 
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         * Drop instruction prefetch hint since it degrades the
 
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         * the performance.
 
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         */
 
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        aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
 
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                (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 
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                (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 
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                (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
 
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        omap_smc1(0x109, aux_ctrl);
 
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        /* Setup POR Control register */
 
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        por_ctrl = readl_relaxed(l2cache_base + L2X0_PREFETCH_CTRL);
 
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        /*
 
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         * Double linefill is available only on OMAP4460 L2X0.
 
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         * Undocumented bit 25 is set for better performance.
 
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         */
 
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        if (cpu_is_omap446x())
 
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                por_ctrl |= ((1 << L2X0_PREFETCH_DATA_PREFETCH_SHIFT) |
 
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                        (1 << L2X0_PREFETCH_DOUBLE_LINEFILL_SHIFT) |
 
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                        (1 << 25));
 
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        if (cpu_is_omap446x() || (omap_rev() >= OMAP4430_REV_ES2_2)) {
 
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                por_ctrl |= L2X0_POR_OFFSET_VALUE;
 
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                omap_smc1(0x113, por_ctrl);
 
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        }
 
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        if (cpu_is_omap446x()) {
 
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                writel_relaxed(0xa5a5, l2cache_base + 0x900);
 
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                writel_relaxed(0xa5a5, l2cache_base + 0x908);
 
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                writel_relaxed(0xa5a5, l2cache_base + 0x904);
 
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                writel_relaxed(0xa5a5, l2cache_base + 0x90C);
 
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        }
 
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        /*
 
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         * FIXME: Temporary WA for OMAP4460 stability issue.
 
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         * Lock-down specific L2 cache ways which  makes effective
 
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         * L2 size as 512 KB instead of 1 MB
 
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         */
 
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        if (cpu_is_omap446x()) {
 
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                lockdown = 0xa5a5;
 
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                writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_D0);
 
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                writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_D1);
 
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                writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_I0);
 
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                writel_relaxed(lockdown, l2cache_base + L2X0_LOCKDOWN_WAY_I1);
 
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        }
 
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skip_aux_por_api:
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        /* Enable PL310 L2 Cache controller */
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        omap_smc1(0x102, 0x1);
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}
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early_initcall(omap_l2_cache_init);
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#endif
 
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void __iomem *omap4_get_sar_ram_base(void)
 
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{
 
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        return sar_ram_base;
 
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}
 
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/*
 
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 * SAR RAM used to save and restore the HW
 
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 * context in low power modes
 
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 */
 
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static int __init omap4_sar_ram_init(void)
 
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{
 
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        /*
 
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         * To avoid code running on other OMAPs in
 
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         * multi-omap builds
 
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         */
 
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        if (!cpu_is_omap44xx())
 
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                return -ENODEV;
 
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        /* Static mapping, never released */
 
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        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_8K);
 
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        if (WARN_ON(!sar_ram_base))
 
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                return -ENODEV;
 
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        return 0;
 
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}
 
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early_initcall(omap4_sar_ram_init);