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Viewing changes to arch/powerpc/kernel/setup_64.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/powerpc/kernel/setup_64.c
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#include <asm/udbg.h>
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#include <asm/kexec.h>
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#include <asm/mmu_context.h>
 
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#include <asm/code-patching.h>
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#include "setup.h"
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#endif
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int boot_cpuid = 0;
 
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int __initdata boot_cpu_count;
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u64 ppc64_pft_size;
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/* Pick defaults since we might want to patch instructions
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void smp_release_cpus(void)
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{
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        unsigned long *ptr;
 
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        int i;
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        DBG(" -> smp_release_cpus()\n");
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        ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
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                        - PHYSICAL_START);
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        *ptr = __pa(generic_secondary_smp_init);
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        mb();
 
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        /* And wait a bit for them to catch up */
 
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        for (i = 0; i < 100000; i++) {
 
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                mb();
 
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                HMT_low();
 
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                if (boot_cpu_count == 0)
 
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                        break;
 
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                udelay(1);
 
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        }
 
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        DBG("boot_cpu_count = %d\n", boot_cpu_count);
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        DBG(" <- smp_release_cpus()\n");
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}
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        DBG(" <- setup_system()\n");
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}
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static u64 slb0_limit(void)
 
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/* This returns the limit below which memory accesses to the linear
 
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 * mapping are guarnateed not to cause a TLB or SLB miss. This is
 
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 * used to allocate interrupt or emergency stacks for which our
 
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 * exception entry path doesn't deal with being interrupted.
 
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 */
 
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static u64 safe_stack_limit(void)
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{
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        if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
 
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#ifdef CONFIG_PPC_BOOK3E
 
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        /* Freescale BookE bolts the entire linear mapping */
 
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        if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 
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                return linear_map_top;
 
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        /* Other BookE, we assume the first GB is bolted */
 
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        return 1ul << 30;
 
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#else
 
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        /* BookS, the first segment is bolted */
 
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        if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
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                return 1UL << SID_SHIFT_1T;
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        }
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        return 1UL << SID_SHIFT;
 
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#endif
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}
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static void __init irqstack_early_init(void)
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{
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        u64 limit = slb0_limit();
 
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        u64 limit = safe_stack_limit();
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        unsigned int i;
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        /*
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#ifdef CONFIG_PPC_BOOK3E
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static void __init exc_lvl_early_init(void)
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{
 
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        extern unsigned int interrupt_base_book3e;
 
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        extern unsigned int exc_debug_debug_book3e;
 
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        unsigned int i;
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        for_each_possible_cpu(i) {
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                mcheckirq_ctx[i] = (struct thread_info *)
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                        __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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        }
 
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        if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 
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                patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
 
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                             (unsigned long)&exc_debug_debug_book3e, 0);
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}
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#else
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#define exc_lvl_early_init()
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         * bringup, we need to get at them in real mode. This means they
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         * must also be within the RMO region.
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         */
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        limit = min(slb0_limit(), ppc64_rma_size);
 
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        limit = min(safe_stack_limit(), ppc64_rma_size);
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        for_each_possible_cpu(i) {
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                unsigned long sp;