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Viewing changes to arch/arm/mach-omap2/pm44xx.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/arm/mach-omap2/pm44xx.c
15
15
#include <linux/list.h>
16
16
#include <linux/err.h>
17
17
#include <linux/slab.h>
18
 
 
 
18
#include <linux/clk.h>
 
19
#include <linux/gpio.h>
 
20
#include <linux/interrupt.h>
 
21
#include <linux/delay.h>
 
22
 
 
23
#include <plat/serial.h>
 
24
 
 
25
#include "pm.h"
19
26
#include "powerdomain.h"
 
27
#include "clockdomain.h"
 
28
#include "clock.h"
 
29
#include "cminst44xx.h"
 
30
#include "prcm44xx.h"
 
31
#include "cm1_44xx.h"
 
32
#include "cm2_44xx.h"
 
33
#include "prm44xx.h"
 
34
#include "prminst44xx.h"
 
35
 
20
36
#include <mach/omap4-common.h>
 
37
#include <plat/common.h>
 
38
 
 
39
#include "prm-regbits-44xx.h"
 
40
#include "cm-regbits-44xx.h"
21
41
 
22
42
struct power_state {
23
43
        struct powerdomain *pwrdm;
30
50
 
31
51
static LIST_HEAD(pwrst_list);
32
52
 
 
53
#define MAX_IOPAD_LATCH_TIME 1000
 
54
void omap4_trigger_ioctrl(void)
 
55
{
 
56
        int i = 0;
 
57
 
 
58
        /* Trigger WUCLKIN enable */
 
59
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, OMAP4430_WUCLK_CTRL_MASK,
 
60
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
 
61
        omap_test_timeout(
 
62
                ((omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET)
 
63
                >> OMAP4430_WUCLK_STATUS_SHIFT) == 1),
 
64
                MAX_IOPAD_LATCH_TIME, i);
 
65
        /* Trigger WUCLKIN disable */
 
66
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
 
67
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
 
68
        return;
 
69
}
 
70
 
33
71
#ifdef CONFIG_SUSPEND
 
72
/* This is a common low power function called from suspend and
 
73
 * cpuidle
 
74
 */
 
75
void omap4_enter_sleep(void)
 
76
{
 
77
        u32 cpu_id = smp_processor_id();
 
78
 
 
79
        omap_uart_prepare_idle(0);
 
80
        omap_uart_prepare_idle(1);
 
81
        omap_uart_prepare_idle(2);
 
82
        omap_uart_prepare_idle(3);
 
83
        omap2_gpio_prepare_for_idle(0);
 
84
        omap4_trigger_ioctrl();
 
85
 
 
86
        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
 
87
 
 
88
        omap2_gpio_resume_after_idle();
 
89
        omap_uart_resume_idle(0);
 
90
        omap_uart_resume_idle(1);
 
91
        omap_uart_resume_idle(2);
 
92
        omap_uart_resume_idle(3);
 
93
 
 
94
        return;
 
95
}
 
96
 
34
97
static int omap4_pm_suspend(void)
35
98
{
36
99
        do_wfi();
87
150
        pwrst->next_state = PWRDM_POWER_ON;
88
151
        list_add(&pwrst->node, &pwrst_list);
89
152
 
90
 
        return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
91
 
}
 
153
        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 
154
}
 
155
 
 
156
static void __init prcm_setup_regs(void)
 
157
{
 
158
        struct clk *dpll_abe_ck, *dpll_core_ck, *dpll_iva_ck;
 
159
        struct clk *dpll_mpu_ck, *dpll_per_ck, *dpll_usb_ck;
 
160
        struct clk *dpll_unipro_ck;
 
161
        /*Enable all the DPLL autoidle */
 
162
        dpll_abe_ck = clk_get(NULL, "dpll_abe_ck");
 
163
        omap3_dpll_allow_idle(dpll_abe_ck);
 
164
        dpll_core_ck = clk_get(NULL, "dpll_core_ck");
 
165
        omap3_dpll_allow_idle(dpll_core_ck);
 
166
        dpll_iva_ck = clk_get(NULL, "dpll_iva_ck");
 
167
        omap3_dpll_allow_idle(dpll_iva_ck);
 
168
        if (cpu_is_omap446x())
 
169
                dpll_mpu_ck = clk_get(NULL, "virt_dpll_mpu_ck");
 
170
        else
 
171
                dpll_mpu_ck = clk_get(NULL, "dpll_mpu_ck");
 
172
        omap3_dpll_allow_idle(dpll_mpu_ck);
 
173
        dpll_per_ck = clk_get(NULL, "dpll_per_ck");
 
174
        omap3_dpll_allow_idle(dpll_per_ck);
 
175
        dpll_usb_ck = clk_get(NULL, "dpll_usb_ck");
 
176
        omap3_dpll_allow_idle(dpll_usb_ck);
 
177
        dpll_unipro_ck = clk_get(NULL, "dpll_unipro_ck");
 
178
        omap3_dpll_allow_idle(dpll_unipro_ck);
 
179
        /* Enable autogating for all DPLL post dividers */
 
180
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK, 0x0,
 
181
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET);
 
182
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK, 0x0,
 
183
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET);
 
184
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK, 0x0,
 
185
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET);
 
186
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK, 0x0,
 
187
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET);
 
188
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK, 0x0,
 
189
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET);
 
190
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK, 0x0,
 
191
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET);
 
192
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK, 0x0,
 
193
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET);
 
194
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK, 0x0,
 
195
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET);
 
196
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK, 0x0,
 
197
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET);
 
198
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK, 0x0,
 
199
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_PER_OFFSET);
 
200
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK, 0x0,
 
201
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_PER_OFFSET);
 
202
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK, 0x0,
 
203
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M3_DPLL_PER_OFFSET);
 
204
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK, 0x0,
 
205
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M4_DPLL_PER_OFFSET);
 
206
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK, 0x0,
 
207
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M5_DPLL_PER_OFFSET);
 
208
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK, 0x0,
 
209
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M6_DPLL_PER_OFFSET);
 
210
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK, 0x0,
 
211
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M7_DPLL_PER_OFFSET);
 
212
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK, 0x0,
 
213
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET);
 
214
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK, 0x0,
 
215
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET);
 
216
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK, 0x0,
 
217
                OMAP4430_CM1_PARTITION, OMAP4430_CM1_CKGEN_INST, OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET);
 
218
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK, 0x0,
 
219
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_USB_OFFSET);
 
220
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK, 0x0,
 
221
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET);
 
222
        omap4_cminst_rmw_inst_reg_bits(OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK, 0x0,
 
223
                OMAP4430_CM2_PARTITION, OMAP4430_CM2_CKGEN_INST, OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET);
 
224
        /* Enable IO_ST interrupt */
 
225
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_IO_ST_MASK, OMAP4430_IO_ST_MASK,
 
226
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_OCP_SOCKET_INST, OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 
227
 
 
228
        /* Enable GLOBAL_WUEN */
 
229
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_GLOBAL_WUEN_MASK,
 
230
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
 
231
        /*
 
232
         * Errata ID: i608 Impacted OMAP4430 ES 1.0,2.0,2.1,2.2
 
233
         * On OMAP4, Retention-Till-Access Memory feature is not working
 
234
         * reliably and hardware recommondation is keep it disabled by
 
235
         * default
 
236
         */
 
237
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_DISABLE_RTA_EXPORT_MASK,
 
238
                0x1 << OMAP4430_DISABLE_RTA_EXPORT_SHIFT,
 
239
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET);
 
240
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_DISABLE_RTA_EXPORT_MASK,
 
241
                0x1 << OMAP4430_DISABLE_RTA_EXPORT_SHIFT,
 
242
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET);
 
243
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_DISABLE_RTA_EXPORT_MASK,
 
244
                0x1 << OMAP4430_DISABLE_RTA_EXPORT_SHIFT,
 
245
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET);
 
246
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_DISABLE_RTA_EXPORT_MASK,
 
247
                0x1 << OMAP4430_DISABLE_RTA_EXPORT_SHIFT,
 
248
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET);
 
249
        /* Toggle CLKREQ in RET and OFF states */
 
250
        omap4_prminst_write_inst_reg(0x2, OMAP4430_PRM_PARTITION,
 
251
                OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_CLKREQCTRL_OFFSET);
 
252
        /*
 
253
         * De-assert PWRREQ signal in Device OFF state
 
254
         *      0x3: PWRREQ is de-asserted if all voltage domain are in
 
255
         *      OFF state. Conversely, PWRREQ is asserted upon any
 
256
         *      voltage domain entering or staying in ON or SLEEP or
 
257
         *      RET state.
 
258
         */
 
259
        omap4_prminst_write_inst_reg(0x3, OMAP4430_PRM_PARTITION,
 
260
                OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_PWRREQCTRL_OFFSET);
 
261
}
 
262
 
 
263
int omap4_can_sleep(void)
 
264
{
 
265
        if (!omap_uart_can_sleep())
 
266
                return -1;
 
267
        return 0;
 
268
}
 
269
 
 
270
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 
271
{
 
272
        u32 irqenable_mpu, irqstatus_mpu;
 
273
 
 
274
        irqenable_mpu = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 
275
                                         OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 
276
        irqstatus_mpu = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 
277
                                         OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 
278
 
 
279
        /* Check if a IO_ST interrupt */
 
280
        if (irqstatus_mpu & OMAP4430_IO_ST_MASK) {
 
281
                omap4_trigger_ioctrl();
 
282
        }
 
283
 
 
284
        /* Clear the interrupt */
 
285
        irqstatus_mpu &= irqenable_mpu;
 
286
        omap4_prm_write_inst_reg(irqstatus_mpu, OMAP4430_PRM_OCP_SOCKET_INST,
 
287
                                        OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 
288
 
 
289
        return IRQ_HANDLED;
 
290
}
 
291
 
92
292
 
93
293
/**
94
294
 * omap4_pm_init - Init routine for OMAP4 PM
105
305
 
106
306
        pr_err("Power Management for TI OMAP4.\n");
107
307
 
108
 
#ifdef CONFIG_PM
 
308
        /* Enable IO_ST interrupt */
 
309
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_IO_ST_MASK, OMAP4430_IO_ST_MASK,
 
310
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_OCP_SOCKET_INST, OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 
311
 
 
312
        /* Enable GLOBAL_WUEN */
 
313
        omap4_prminst_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, OMAP4430_GLOBAL_WUEN_MASK,
 
314
                OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_IO_PMCTRL_OFFSET);
 
315
 
 
316
        ret = request_irq(OMAP44XX_IRQ_PRCM,
 
317
                          (irq_handler_t)prcm_interrupt_handler,
 
318
                          IRQF_DISABLED, "prcm", NULL);
 
319
        if (ret) {
 
320
                printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 
321
                       OMAP44XX_IRQ_PRCM);
 
322
                goto err2;
 
323
        }
109
324
        ret = pwrdm_for_each(pwrdms_setup, NULL);
110
325
        if (ret) {
111
326
                pr_err("Failed to setup powerdomains\n");
112
327
                goto err2;
113
328
        }
114
 
#endif
 
329
 
 
330
        ret = omap4_mpuss_init();
 
331
        if (ret) {
 
332
                pr_err("Failed to initialise OMAP4 MPUSS\n");
 
333
                goto err2;
 
334
        }
115
335
 
116
336
#ifdef CONFIG_SUSPEND
117
337
        suspend_set_ops(&omap_pm_ops);