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Viewing changes to arch/x86/kernel/cpu/intel_cacheinfo.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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Lines of Context:
arch/x86/kernel/cpu/intel_cacheinfo.c
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struct _cache_attr {
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        struct attribute attr;
307
 
        ssize_t (*show)(struct _cpuid4_info *, char *);
308
 
        ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
 
307
        ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int);
 
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        ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count,
 
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                         unsigned int);
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};
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#ifdef CONFIG_AMD_NB
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        l3->subcaches[2] = sc2 = !(val & BIT(8))  + !(val & BIT(9));
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        l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
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        l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
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        l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}
332
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400
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#define SHOW_CACHE_DISABLE(slot)                                        \
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static ssize_t                                                          \
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show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf)    \
 
403
show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf,    \
 
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                          unsigned int cpu)                             \
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{                                                                       \
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        return show_cache_disable(this_leaf, buf, slot);                \
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}
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{
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        int ret = 0;
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455
 
#define SUBCACHE_MASK   (3UL << 20)
456
 
#define SUBCACHE_INDEX  0xfff
457
 
 
458
 
        /*
459
 
         * check whether this slot is already used or
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         * the index is already disabled
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         */
 
456
        /*  check if @slot is already used or the index is already disabled */
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        ret = amd_get_l3_disable_slot(l3, slot);
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        if (ret >= 0)
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                return -EINVAL;
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466
 
        /*
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         * check whether the other slot has disabled the
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         * same index already
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         */
 
461
        if (index > l3->indices)
 
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                return -EINVAL;
 
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        /* check whether the other slot has disabled the same index already */
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        if (index == amd_get_l3_disable_slot(l3, !slot))
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                return -EINVAL;
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473
 
        /* do not allow writes outside of allowed bits */
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        if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
475
 
            ((index & SUBCACHE_INDEX) > l3->indices))
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                return -EINVAL;
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        amd_l3_disable_index(l3, cpu, slot, index);
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        return 0;
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#define STORE_CACHE_DISABLE(slot)                                       \
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static ssize_t                                                          \
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store_cache_disable_##slot(struct _cpuid4_info *this_leaf,              \
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                           const char *buf, size_t count)               \
 
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                           const char *buf, size_t count,               \
 
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                           unsigned int cpu)                            \
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{                                                                       \
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        return store_cache_disable(this_leaf, buf, count, slot);        \
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}
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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                show_cache_disable_1, store_cache_disable_1);
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static ssize_t
 
519
show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu)
 
520
{
 
521
        if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 
522
                return -EINVAL;
 
523
 
 
524
        return sprintf(buf, "%x\n", amd_get_subcaches(cpu));
 
525
}
 
526
 
 
527
static ssize_t
 
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store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count,
 
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                unsigned int cpu)
 
530
{
 
531
        unsigned long val;
 
532
 
 
533
        if (!capable(CAP_SYS_ADMIN))
 
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                return -EPERM;
 
535
 
 
536
        if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 
537
                return -EINVAL;
 
538
 
 
539
        if (strict_strtoul(buf, 16, &val) < 0)
 
540
                return -EINVAL;
 
541
 
 
542
        if (amd_set_subcaches(cpu, val))
 
543
                return -EINVAL;
 
544
 
 
545
        return count;
 
546
}
 
547
 
 
548
static struct _cache_attr subcaches =
 
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        __ATTR(subcaches, 0644, show_subcaches, store_subcaches);
 
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#else   /* CONFIG_AMD_NB */
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#define amd_init_l3_cache(x, y)
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#endif /* CONFIG_AMD_NB */
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__cpuinit cpuid4_cache_lookup_regs(int index,
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                                   struct _cpuid4_info_regs *this_leaf)
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{
535
 
        union _cpuid4_leaf_eax  eax;
536
 
        union _cpuid4_leaf_ebx  ebx;
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        union _cpuid4_leaf_ecx  ecx;
 
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        union _cpuid4_leaf_eax  eax;
 
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        union _cpuid4_leaf_ebx  ebx;
 
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        union _cpuid4_leaf_ecx  ecx;
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        unsigned                edx;
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        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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        struct cpuinfo_x86 *c = &cpu_data(cpu);
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        if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
735
 
                for_each_cpu(i, c->llc_shared_map) {
 
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                for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
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                        if (!per_cpu(ici_cpuid4_info, i))
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                                continue;
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                        this_leaf = CPUID4_INFO_IDX(i, index);
739
 
                        for_each_cpu(sibling, c->llc_shared_map) {
 
763
                        for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) {
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                                if (!cpu_online(sibling))
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                                        continue;
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                                set_bit(sibling, this_leaf->shared_cpu_map);
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#define INDEX_KOBJECT_PTR(x, y)         (&((per_cpu(ici_index_kobject, x))[y]))
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#define show_one_plus(file_name, object, val)                           \
873
 
static ssize_t show_##file_name                                         \
874
 
                        (struct _cpuid4_info *this_leaf, char *buf)     \
 
897
static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \
 
898
                                unsigned int cpu)                       \
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{                                                                       \
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        return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
877
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}
882
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show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
883
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show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
884
908
 
885
 
static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
 
909
static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf,
 
910
                         unsigned int cpu)
886
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{
887
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        return sprintf(buf, "%luK\n", this_leaf->size / 1024);
888
913
}
906
931
        return n;
907
932
}
908
933
 
909
 
static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
 
934
static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf,
 
935
                                          unsigned int cpu)
910
936
{
911
937
        return show_shared_cpu_map_func(leaf, 0, buf);
912
938
}
913
939
 
914
 
static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
 
940
static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf,
 
941
                                           unsigned int cpu)
915
942
{
916
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        return show_shared_cpu_map_func(leaf, 1, buf);
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}
918
945
 
919
 
static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 
946
static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf,
 
947
                         unsigned int cpu)
920
948
{
921
949
        switch (this_leaf->eax.split.type) {
922
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        case CACHE_TYPE_DATA:
974
1002
        if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
975
1003
                n += 2;
976
1004
 
 
1005
        if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 
1006
                n += 1;
 
1007
 
977
1008
        attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL);
978
1009
        if (attrs == NULL)
979
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                return attrs = default_attrs;
986
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                attrs[n++] = &cache_disable_1.attr;
987
1018
        }
988
1019
 
 
1020
        if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
 
1021
                attrs[n++] = &subcaches.attr;
 
1022
 
989
1023
        return attrs;
990
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}
991
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#endif
998
1032
 
999
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        ret = fattr->show ?
1000
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                fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
1001
 
                        buf) :
 
1035
                        buf, this_leaf->cpu) :
1002
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                0;
1003
1037
        return ret;
1004
1038
}
1012
1046
 
1013
1047
        ret = fattr->store ?
1014
1048
                fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
1015
 
                        buf, count) :
 
1049
                        buf, count, this_leaf->cpu) :
1016
1050
                0;
1017
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        return ret;
1018
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}