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#ifndef _BF537_IRQ_H_
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#define _BF537_IRQ_H_
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* Interrupt source definitions
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* Event Source Core Event Name
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* Events (highest priority) EMU 0
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* Hardware Error IVHW 5
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* (lowest priority) IVG15
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#define NR_PERI_INTS 32
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/* The ABSTRACT IRQ definitions */
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/** the first seven of the following are fixed, the rest you change if you need to **/
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#define IRQ_EMU 0 /*Emulation */
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#define IRQ_RST 1 /*reset */
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#define IRQ_NMI 2 /*Non Maskable */
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#define IRQ_EVX 3 /*Exception */
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#define IRQ_UNUSED 4 /*- unused interrupt*/
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#define IRQ_HWERR 5 /*Hardware Error */
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#define IRQ_CORETMR 6 /*Core timer */
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#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
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#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
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#define IRQ_RTC 10 /*RTC Interrupt */
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#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
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#define IRQ_TWI 16 /*TWI Interrupt */
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#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
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#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
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#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
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#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
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#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
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#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
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#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
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#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
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#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
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#define IRQ_TIMER0 26 /*Timer 0 */
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#define IRQ_TIMER1 27 /*Timer 1 */
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#define IRQ_TIMER2 28 /*Timer 2 */
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#define IRQ_TIMER3 29 /*Timer 3 */
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#define IRQ_TIMER4 30 /*Timer 4 */
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#define IRQ_TIMER5 31 /*Timer 5 */
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#define IRQ_TIMER6 32 /*Timer 6 */
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#define IRQ_TIMER7 33 /*Timer 7 */
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#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
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#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
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#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
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#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
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#define IRQ_WATCH 38 /*Watch Dog Timer */
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#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
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#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
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#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
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#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
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#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
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#define GPIO_IRQ_BASE IRQ_PF0
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#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
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#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
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#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
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#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
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#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
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#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
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#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
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#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
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#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
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#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA_ERROR_POS 4
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#define IRQ_ERROR_POS 8
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#define IRQ_RTC_POS 12
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#define IRQ_PPI_POS 16
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#define IRQ_SPORT0_RX_POS 20
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#define IRQ_SPORT0_TX_POS 24
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#define IRQ_SPORT1_RX_POS 28
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#define IRQ_SPORT1_TX_POS 0
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#define IRQ_TWI_POS 4
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#define IRQ_SPI_POS 8
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#define IRQ_UART0_RX_POS 12
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#define IRQ_UART0_TX_POS 16
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#define IRQ_UART1_RX_POS 20
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#define IRQ_UART1_TX_POS 24
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#define IRQ_CAN_RX_POS 28
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MAC_RX_POS 4
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#define IRQ_MAC_TX_POS 8
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#define IRQ_TIMER0_POS 12
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#define IRQ_TIMER1_POS 16
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#define IRQ_TIMER2_POS 20
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#define IRQ_TIMER3_POS 24
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#define IRQ_TIMER4_POS 28
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#define IRQ_TIMER5_POS 0
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#define IRQ_TIMER6_POS 4
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#define IRQ_TIMER7_POS 8
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#define IRQ_PROG_INTA_POS 12
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#define IRQ_PORTG_INTB_POS 16
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#define IRQ_MEM_DMA0_POS 20
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#define IRQ_MEM_DMA1_POS 24
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#define IRQ_WATCH_POS 28
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#endif /* _BF537_IRQ_H_ */
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#include <mach-common/irq.h>
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#define NR_PERI_INTS 32
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#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
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#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
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#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
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#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
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#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
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#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
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#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
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#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
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#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
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#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
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#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
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#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
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#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
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#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
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#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
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#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
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#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
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#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
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#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
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#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
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#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
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#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
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#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
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#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
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#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
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#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
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#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
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#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
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#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
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#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
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#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
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#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
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#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
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#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
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#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
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#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
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#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
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#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
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#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
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#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
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#define GPIO_IRQ_BASE IRQ_PF0
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#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
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#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
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#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
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#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
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#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
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#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
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#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
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#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
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#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
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#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
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#if 0 /* No Interrupt B support (yet) */
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#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
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#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
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#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
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#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
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#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
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#if 0 /* No Interrupt B support (yet) */
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#define IRQ_WATCH 112 /* Watchdog Timer */
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#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
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#define IRQ_WATCH IRQ_PF_INTB_WATCH
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#define NR_MACH_IRQS (113 + 1)
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/* IAR0 BIT FIELDS */
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#define IRQ_PLL_WAKEUP_POS 0
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#define IRQ_DMA_ERROR_POS 4
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#define IRQ_ERROR_POS 8
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#define IRQ_RTC_POS 12
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#define IRQ_PPI_POS 16
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#define IRQ_SPORT0_RX_POS 20
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#define IRQ_SPORT0_TX_POS 24
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#define IRQ_SPORT1_RX_POS 28
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/* IAR1 BIT FIELDS */
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#define IRQ_SPORT1_TX_POS 0
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#define IRQ_TWI_POS 4
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#define IRQ_SPI_POS 8
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#define IRQ_UART0_RX_POS 12
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#define IRQ_UART0_TX_POS 16
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#define IRQ_UART1_RX_POS 20
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#define IRQ_UART1_TX_POS 24
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#define IRQ_CAN_RX_POS 28
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/* IAR2 BIT FIELDS */
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#define IRQ_CAN_TX_POS 0
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#define IRQ_MAC_RX_POS 4
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#define IRQ_MAC_TX_POS 8
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#define IRQ_TIMER0_POS 12
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#define IRQ_TIMER1_POS 16
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#define IRQ_TIMER2_POS 20
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#define IRQ_TIMER3_POS 24
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#define IRQ_TIMER4_POS 28
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/* IAR3 BIT FIELDS */
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#define IRQ_TIMER5_POS 0
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#define IRQ_TIMER6_POS 4
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#define IRQ_TIMER7_POS 8
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#define IRQ_PROG_INTA_POS 12
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#define IRQ_PORTG_INTB_POS 16
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#define IRQ_MEM_DMA0_POS 20
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#define IRQ_MEM_DMA1_POS 24
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#define IRQ_WATCH_POS 28
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#define init_mach_irq init_mach_irq