74
74
interrupt-parent = <&mpic>;
75
75
phy-handle = <&phy0>
78
* Gianfar PTP clock nodes
82
- compatible Should be "fsl,etsec-ptp"
83
- reg Offset and length of the register set for the device
84
- interrupts There should be at least two interrupts. Some devices
85
have as many as four PTP related interrupts.
89
- fsl,tclk-period Timer reference clock period in nanoseconds.
90
- fsl,tmr-prsc Prescaler, divides the output clock.
91
- fsl,tmr-add Frequency compensation value.
92
- fsl,tmr-fiper1 Fixed interval period pulse generator.
93
- fsl,tmr-fiper2 Fixed interval period pulse generator.
94
- fsl,max-adj Maximum frequency adjustment in parts per billion.
96
These properties set the operational parameters for the PTP
97
clock. You must choose these carefully for the clock to work right.
98
Here is how to figure good values:
100
TimerOsc = system clock MHz
101
tclk_period = desired clock period nanoseconds
102
NominalFreq = 1000 / tclk_period MHz
103
FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
104
tmr_add = ceil(2^32 / FreqDivRatio)
105
OutputClock = NominalFreq / tmr_prsc MHz
106
PulseWidth = 1 / OutputClock microseconds
107
FiperFreq1 = desired frequency in Hz
108
FiperDiv1 = 1000000 * OutputClock / FiperFreq1
109
tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
110
max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
112
The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
113
driver expects that tmr_fiper1 will be correctly set to produce a 1
114
Pulse Per Second (PPS) signal, since this will be offered to the PPS
115
subsystem to synchronize the Linux clock.
120
compatible = "fsl,etsec-ptp";
121
reg = <0x24E00 0xB0>;
122
interrupts = <12 0x8 13 0x8>;
123
interrupt-parent = < &ipic >;
124
fsl,tclk-period = <10>;
125
fsl,tmr-prsc = <100>;
126
fsl,tmr-add = <0x999999A4>;
127
fsl,tmr-fiper1 = <0x3B9AC9F6>;
128
fsl,tmr-fiper2 = <0x00018696>;
129
fsl,max-adj = <659999998>;