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Viewing changes to arch/mips/pmc-sierra/msp71xx/msp_irq.c

  • Committer: Bazaar Package Importer
  • Author(s): Paolo Pisati
  • Date: 2011-06-29 15:23:51 UTC
  • mfrom: (26.1.1 natty-proposed)
  • Revision ID: james.westby@ubuntu.com-20110629152351-xs96tm303d95rpbk
Tags: 3.0.0-1200.2
* Rebased against 3.0.0-6.7
* BSP from TI based on 3.0.0

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arch/mips/pmc-sierra/msp71xx/msp_irq.c
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#include <msp_int.h>
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extern void msp_int_handle(void);
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/* SLP bases systems */
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extern void msp_slp_irq_init(void);
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extern void msp_slp_irq_dispatch(void);
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extern void msp_cic_irq_init(void);
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extern void msp_cic_irq_dispatch(void);
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/* VSMP support init */
 
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extern void msp_vsmp_int_init(void);
 
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/* vectored interrupt implementation */
 
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/* SW0/1 interrupts are used for SMP/SMTC */
 
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static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
 
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static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
 
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static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
 
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static inline void usb_int_dispatch(void)  { do_IRQ(MSP_INT_USB);  }
 
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static inline void sec_int_dispatch(void)  { do_IRQ(MSP_INT_SEC);  }
 
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/*
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 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
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 * hierarchical system.  The first level are the direct MIPS interrupts
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                do_IRQ(MSP_INT_SW1);
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}
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static struct irqaction cascade_msp = {
 
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static struct irqaction cic_cascade_msp = {
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        .handler = no_action,
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        .name    = "MSP cascade"
 
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        .name    = "MSP CIC cascade"
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};
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static struct irqaction per_cascade_msp = {
 
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        .handler = no_action,
 
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        .name    = "MSP PER cascade"
 
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};
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void __init arch_init_irq(void)
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{
 
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        /* assume we'll be using vectored interrupt mode except in UP mode*/
 
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#ifdef CONFIG_MIPS_MT
 
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        BUG_ON(!cpu_has_vint);
 
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#endif
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        /* initialize the 1st-level CPU based interrupt controller */
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        mips_cpu_irq_init();
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#ifdef CONFIG_IRQ_MSP_CIC
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        msp_cic_irq_init();
 
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#ifdef CONFIG_MIPS_MT
 
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        set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
 
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        set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
 
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        set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
 
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        set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
 
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        set_vi_handler(MSP_INT_USB, usb_int_dispatch);
 
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        set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
 
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#ifdef CONFIG_MIPS_MT_SMP
 
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        msp_vsmp_int_init();
 
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#elif defined CONFIG_MIPS_MT_SMTC
 
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        /*Set hwmask for all platform devices */
 
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        irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
 
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        irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
 
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        irq_hwmask[MSP_INT_USB] = C_IRQ2;
 
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        irq_hwmask[MSP_INT_SAR] = C_IRQ3;
 
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        irq_hwmask[MSP_INT_SEC] = C_IRQ5;
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#endif  /* CONFIG_MIPS_MT_SMP */
 
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#endif  /* CONFIG_MIPS_MT */
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        /* setup the cascaded interrupts */
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        setup_irq(MSP_INT_CIC, &cascade_msp);
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        setup_irq(MSP_INT_PER, &cascade_msp);
 
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        setup_irq(MSP_INT_CIC, &cic_cascade_msp);
 
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        setup_irq(MSP_INT_PER, &per_cascade_msp);
 
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#else
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        /* setup the 2nd-level SLP register based interrupt controller */
 
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        /* VSMP /SMTC support support is not enabled for SLP */
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        msp_slp_irq_init();
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        /* setup the cascaded SLP/PER interrupts */
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        setup_irq(MSP_INT_SLP, &cascade_msp);
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        setup_irq(MSP_INT_PER, &cascade_msp);
 
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        setup_irq(MSP_INT_SLP, &cic_cascade_msp);
 
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        setup_irq(MSP_INT_PER, &per_cascade_msp);
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#endif
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}