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Viewing changes to arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h

  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno, Martin Michlmayr
  • Date: 2011-04-06 13:53:30 UTC
  • mfrom: (43.1.5 sid)
  • Revision ID: james.westby@ubuntu.com-20110406135330-wjufxhd0tvn3zx4z
Tags: 2.6.38-3
http://bugs.debian.org/620124
http://bugs.debian.org/620284
http://bugs.debian.org/620204
[ Ben Hutchings ]
* [ppc64] Add to linux-tools package architectures (Closes: #620124)
* [amd64] Save cr4 to mmu_cr4_features at boot time (Closes: #620284)
* appletalk: Fix bugs introduced when removing use of BKL
* ALSA: Fix yet another race in disconnection
* cciss: Fix lost command issue
* ath9k: Fix kernel panic in AR2427
* ses: Avoid kernel panic when lun 0 is not mapped
* PCI/ACPI: Report ASPM support to BIOS if not disabled from command line

[ Aurelien Jarno ]
* rtlwifi: fix build when PCI is not enabled.

[ Martin Michlmayr ]
* rtlwifi: Eliminate udelay calls with too large values (Closes: #620204)

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arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
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/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
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 *
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 * Copyright 2008 Openmoko, Inc.
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 * Copyright 2008 Simtec Electronics
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 *      http://armlinux.simtec.co.uk/
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 *      Ben Dooks <ben@simtec.co.uk>
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 *
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 * S3C - USB2.0 Highspeed/OtG device PHY registers
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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*/
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/* Note, this is a seperate header file as some of the clock framework
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 * needs to touch this if the clk_48m is used as the USB OHCI or other
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 * peripheral source.
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*/
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#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
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#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
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/* S3C64XX_PA_USB_HSPHY */
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#define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
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#define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
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#define SRC_PHYPWR_OTG_DISABLE                  (1 << 4)
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#define SRC_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
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#define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
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#define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
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#define S3C_PHYCLK_MODE_USB11                   (1 << 6)
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#define S3C_PHYCLK_EXT_OSC                      (1 << 5)
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#define S3C_PHYCLK_CLK_FORCE                    (1 << 4)
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#define S3C_PHYCLK_ID_PULL                      (1 << 2)
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#define S3C_PHYCLK_CLKSEL_MASK                  (0x3 << 0)
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#define S3C_PHYCLK_CLKSEL_SHIFT                 (0)
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#define S3C_PHYCLK_CLKSEL_48M                   (0x0 << 0)
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#define S3C_PHYCLK_CLKSEL_12M                   (0x2 << 0)
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#define S3C_PHYCLK_CLKSEL_24M                   (0x3 << 0)
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#define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
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#define S3C_RSTCON_PHYCLK                       (1 << 2)
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#define S3C_RSTCON_HCLK                         (1 << 2)
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#define S3C_RSTCON_PHY                          (1 << 0)
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#define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
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#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */