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#ifndef __CVMX_CIU_DEFS_H__
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#define __CVMX_CIU_DEFS_H__
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#define CVMX_CIU_BIST \
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CVMX_ADD_IO_SEG(0x0001070000000730ull)
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#define CVMX_CIU_DINT \
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CVMX_ADD_IO_SEG(0x0001070000000720ull)
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#define CVMX_CIU_FUSE \
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CVMX_ADD_IO_SEG(0x0001070000000728ull)
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#define CVMX_CIU_GSTOP \
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CVMX_ADD_IO_SEG(0x0001070000000710ull)
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#define CVMX_CIU_INTX_EN0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN0_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN0_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN1_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
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#define CVMX_CIU_INTX_EN4_0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
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CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
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CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
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#define CVMX_CIU_INTX_SUM0(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
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#define CVMX_CIU_INTX_SUM4(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
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#define CVMX_CIU_INT_SUM1 \
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CVMX_ADD_IO_SEG(0x0001070000000108ull)
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#define CVMX_CIU_MBOX_CLRX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
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#define CVMX_CIU_MBOX_SETX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
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#define CVMX_CIU_NMI \
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CVMX_ADD_IO_SEG(0x0001070000000718ull)
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#define CVMX_CIU_PCI_INTA \
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CVMX_ADD_IO_SEG(0x0001070000000750ull)
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#define CVMX_CIU_PP_DBG \
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CVMX_ADD_IO_SEG(0x0001070000000708ull)
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#define CVMX_CIU_PP_POKEX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
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#define CVMX_CIU_PP_RST \
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CVMX_ADD_IO_SEG(0x0001070000000700ull)
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#define CVMX_CIU_QLM_DCOK \
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CVMX_ADD_IO_SEG(0x0001070000000760ull)
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#define CVMX_CIU_QLM_JTGC \
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CVMX_ADD_IO_SEG(0x0001070000000768ull)
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#define CVMX_CIU_QLM_JTGD \
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CVMX_ADD_IO_SEG(0x0001070000000770ull)
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#define CVMX_CIU_SOFT_BIST \
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CVMX_ADD_IO_SEG(0x0001070000000738ull)
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#define CVMX_CIU_SOFT_PRST \
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CVMX_ADD_IO_SEG(0x0001070000000748ull)
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#define CVMX_CIU_SOFT_PRST1 \
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CVMX_ADD_IO_SEG(0x0001070000000758ull)
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#define CVMX_CIU_SOFT_RST \
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CVMX_ADD_IO_SEG(0x0001070000000740ull)
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#define CVMX_CIU_TIMX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
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#define CVMX_CIU_WDOGX(offset) \
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CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
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#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
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#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
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#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
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#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
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#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
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#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
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#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
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#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
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#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
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#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
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#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
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#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
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#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
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#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
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#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
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#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
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#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
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#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
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#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
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#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
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#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
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#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
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#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
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#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
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#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
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#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
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#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
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#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
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#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
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#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
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#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
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union cvmx_ciu_bist {
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struct cvmx_ciu_bist_s {
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uint64_t reserved_5_63:59;
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struct cvmx_ciu_bist_cn30xx {
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uint64_t reserved_4_63:60;
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struct cvmx_ciu_bist_s cn30xx;
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struct cvmx_ciu_bist_s cn31xx;
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struct cvmx_ciu_bist_s cn38xx;
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struct cvmx_ciu_bist_s cn38xxp2;
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struct cvmx_ciu_bist_cn30xx cn31xx;
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struct cvmx_ciu_bist_cn30xx cn38xx;
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struct cvmx_ciu_bist_cn30xx cn38xxp2;
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struct cvmx_ciu_bist_cn50xx {
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uint64_t reserved_2_63:62;
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struct cvmx_ciu_bist_cn52xx cn52xxp1;
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struct cvmx_ciu_bist_s cn56xx;
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struct cvmx_ciu_bist_s cn56xxp1;
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struct cvmx_ciu_bist_s cn58xx;
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struct cvmx_ciu_bist_s cn58xxp1;
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struct cvmx_ciu_bist_cn30xx cn56xx;
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struct cvmx_ciu_bist_cn30xx cn56xxp1;
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struct cvmx_ciu_bist_cn30xx cn58xx;
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struct cvmx_ciu_bist_cn30xx cn58xxp1;
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struct cvmx_ciu_bist_s cn63xx;
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struct cvmx_ciu_bist_s cn63xxp1;
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union cvmx_ciu_block_int {
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struct cvmx_ciu_block_int_s {
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uint64_t reserved_43_63:21;
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uint64_t reserved_34_39:6;
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uint64_t reserved_31_31:1;
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uint64_t reserved_29_29:1;
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uint64_t reserved_27_27:1;
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uint64_t reserved_23_24:2;
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uint64_t reserved_21_21:1;
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uint64_t reserved_18_19:2;
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uint64_t reserved_15_15:1;
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uint64_t reserved_8_8:1;
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uint64_t reserved_2_2:1;
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struct cvmx_ciu_block_int_s cn63xx;
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struct cvmx_ciu_block_int_s cn63xxp1;
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union cvmx_ciu_dint {
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struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
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struct cvmx_ciu_pp_rst_s cn58xx;
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struct cvmx_ciu_pp_rst_s cn58xxp1;
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struct cvmx_ciu_pp_rst_cn63xx {
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uint64_t reserved_6_63:58;
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struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
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union cvmx_ciu_qlm0 {
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struct cvmx_ciu_qlm0_s {
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uint64_t g2bypass:1;
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uint64_t reserved_53_62:10;
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uint64_t g2deemph:5;
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uint64_t reserved_45_47:3;
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uint64_t g2margin:5;
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uint64_t reserved_32_39:8;
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uint64_t txbypass:1;
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uint64_t reserved_21_30:10;
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uint64_t txdeemph:5;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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struct cvmx_ciu_qlm0_s cn63xx;
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struct cvmx_ciu_qlm0_cn63xxp1 {
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uint64_t reserved_32_63:32;
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uint64_t txbypass:1;
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uint64_t reserved_20_30:11;
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uint64_t txdeemph:4;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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union cvmx_ciu_qlm1 {
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struct cvmx_ciu_qlm1_s {
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uint64_t g2bypass:1;
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uint64_t reserved_53_62:10;
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uint64_t g2deemph:5;
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uint64_t reserved_45_47:3;
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uint64_t g2margin:5;
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uint64_t reserved_32_39:8;
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uint64_t txbypass:1;
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uint64_t reserved_21_30:10;
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uint64_t txdeemph:5;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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struct cvmx_ciu_qlm1_s cn63xx;
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struct cvmx_ciu_qlm1_cn63xxp1 {
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uint64_t reserved_32_63:32;
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uint64_t txbypass:1;
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uint64_t reserved_20_30:11;
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uint64_t txdeemph:4;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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union cvmx_ciu_qlm2 {
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struct cvmx_ciu_qlm2_s {
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uint64_t reserved_32_63:32;
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uint64_t txbypass:1;
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uint64_t reserved_21_30:10;
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uint64_t txdeemph:5;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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struct cvmx_ciu_qlm2_s cn63xx;
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struct cvmx_ciu_qlm2_cn63xxp1 {
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uint64_t reserved_32_63:32;
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uint64_t txbypass:1;
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uint64_t reserved_20_30:11;
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uint64_t txdeemph:4;
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uint64_t reserved_13_15:3;
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uint64_t txmargin:5;
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uint64_t reserved_4_7:4;
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union cvmx_ciu_qlm_dcok {