86
123
struct rio_msg_regs {
124
u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
125
u32 osr; /* 0xD_3004 - Outbound message 0 status register */
127
u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
128
dequeue pointer address register */
130
u32 osar; /* 0xD_3014 - Outbound message 0 source address
132
u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
134
u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
136
u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
139
u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
140
enqueue pointer address register */
142
u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
143
u32 isr; /* 0xD_3064 - Inbound message 0 status register */
145
u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
146
pointer address register*/
148
u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
149
pointer address register */
151
u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
152
u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
154
u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
156
u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
159
u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
160
configuration register */
162
u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
163
u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
165
u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
168
u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
171
u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
172
u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
173
u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
175
u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
127
179
struct rio_tx_desc {
171
231
struct rio_dbell_ring dbell_ring;
172
232
struct rio_msg_tx_ring msg_tx_ring;
173
233
struct rio_msg_rx_ring msg_rx_ring;
234
struct rio_port_write_msg port_write_msg;
239
struct work_struct pw_work;
240
struct kfifo pw_fifo;
241
spinlock_t pw_fifo_lock;
244
#define __fsl_read_rio_config(x, addr, err, op) \
245
__asm__ __volatile__( \
246
"1: "op" %1,0(%2)\n" \
249
".section .fixup,\"ax\"\n" \
253
".section __ex_table,\"a\"\n" \
257
: "=r" (err), "=r" (x) \
258
: "b" (addr), "i" (-EFAULT), "0" (err))
260
static void __iomem *rio_regs_win;
263
static int (*saved_mcheck_exception)(struct pt_regs *regs);
265
static int fsl_rio_mcheck_exception(struct pt_regs *regs)
267
const struct exception_table_entry *entry = NULL;
268
unsigned long reason = mfspr(SPRN_MCSR);
270
if (reason & MCSR_BUS_RBERR) {
271
reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
272
if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
273
/* Check if we are prepared to handle this fault */
274
entry = search_exception_tables(regs->nip);
276
pr_debug("RIO: %s - MC Exception handled\n",
278
out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
281
regs->nip = entry->fixup;
287
if (saved_mcheck_exception)
288
return saved_mcheck_exception(regs);
290
return cur_cpu_spec->machine_check(regs);
180
295
* fsl_rio_doorbell_send - Send a MPC85xx doorbell message
181
296
* @mport: RapidIO master port info
277
392
struct rio_priv *priv = mport->priv;
281
397
("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
282
398
index, destid, hopcount, offset, len);
400
/* 16MB maintenance window possible */
401
/* allow only aligned access to maintenance registers */
402
if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
283
405
out_be32(&priv->maint_atmu_regs->rowtar,
284
(destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
406
(destid << 22) | (hopcount << 12) | (offset >> 12));
407
out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
286
data = (u8 *) priv->maint_win + offset;
409
data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
289
*val = in_8((u8 *) data);
412
__fsl_read_rio_config(rval, data, err, "lbz");
292
*val = in_be16((u16 *) data);
415
__fsl_read_rio_config(rval, data, err, "lhz");
418
__fsl_read_rio_config(rval, data, err, "lwz");
295
*val = in_be32((u32 *) data);
425
pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
426
err, destid, hopcount, offset);
1073
* fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1074
* @irq: Linux interrupt number
1075
* @dev_instance: Pointer to interrupt-specific data
1077
* Handles port write interrupts. Parses a list of registered
1078
* port write event handlers and executes a matching event handler.
1081
fsl_rio_port_write_handler(int irq, void *dev_instance)
1084
struct rio_mport *port = (struct rio_mport *)dev_instance;
1085
struct rio_priv *priv = port->priv;
1088
epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1089
if (!(epwisr & RIO_EPWISR_PW))
1092
ipwmr = in_be32(&priv->msg_regs->pwmr);
1093
ipwsr = in_be32(&priv->msg_regs->pwsr);
1096
pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1097
if (ipwsr & RIO_IPWSR_QF)
1099
if (ipwsr & RIO_IPWSR_TE)
1101
if (ipwsr & RIO_IPWSR_QFI)
1103
if (ipwsr & RIO_IPWSR_PWD)
1105
if (ipwsr & RIO_IPWSR_PWB)
1109
/* Schedule deferred processing if PW was received */
1110
if (ipwsr & RIO_IPWSR_QFI) {
1111
/* Save PW message (if there is room in FIFO),
1112
* otherwise discard it.
1114
if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1115
priv->port_write_msg.msg_count++;
1116
kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1119
priv->port_write_msg.discard_count++;
1120
pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1121
priv->port_write_msg.discard_count);
1123
/* Clear interrupt and issue Clear Queue command. This allows
1124
* another port-write to be received.
1126
out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1127
out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1129
schedule_work(&priv->pw_work);
1132
if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1133
priv->port_write_msg.err_count++;
1134
pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1135
priv->port_write_msg.err_count);
1136
/* Clear Transaction Error: port-write controller should be
1137
* disabled when clearing this error
1139
out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1140
out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1141
out_be32(&priv->msg_regs->pwmr, ipwmr);
1144
if (ipwsr & RIO_IPWSR_PWD) {
1145
priv->port_write_msg.discard_count++;
1146
pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1147
priv->port_write_msg.discard_count);
1148
out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1152
if (epwisr & RIO_EPWISR_PINT) {
1153
tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1154
pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1155
out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1161
static void fsl_pw_dpc(struct work_struct *work)
1163
struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1164
unsigned long flags;
1165
u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1168
* Process port-write messages
1170
spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1171
while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1173
/* Process one message */
1174
spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1178
pr_debug("%s : Port-Write Message:", __func__);
1179
for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1181
pr_debug("\n0x%02x: 0x%08x", i*4,
1184
pr_debug(" 0x%08x", msg_buffer[i]);
1189
/* Pass the port-write message to RIO core for processing */
1190
rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1191
spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1193
spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1197
* fsl_rio_pw_enable - enable/disable port-write interface init
1198
* @mport: Master port implementing the port write unit
1199
* @enable: 1=enable; 0=disable port-write message handling
1201
static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1203
struct rio_priv *priv = mport->priv;
1206
rval = in_be32(&priv->msg_regs->pwmr);
1209
rval |= RIO_IPWMR_PWE;
1211
rval &= ~RIO_IPWMR_PWE;
1213
out_be32(&priv->msg_regs->pwmr, rval);
1219
* fsl_rio_port_write_init - MPC85xx port write interface init
1220
* @mport: Master port implementing the port write unit
1222
* Initializes port write unit hardware and DMA buffer
1223
* ring. Called from fsl_rio_setup(). Returns %0 on success
1224
* or %-ENOMEM on failure.
1226
static int fsl_rio_port_write_init(struct rio_mport *mport)
1228
struct rio_priv *priv = mport->priv;
1231
/* Following configurations require a disabled port write controller */
1232
out_be32(&priv->msg_regs->pwmr,
1233
in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1235
/* Initialize port write */
1236
priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1238
&priv->port_write_msg.phys, GFP_KERNEL);
1239
if (!priv->port_write_msg.virt) {
1240
pr_err("RIO: unable allocate port write queue\n");
1244
priv->port_write_msg.err_count = 0;
1245
priv->port_write_msg.discard_count = 0;
1247
/* Point dequeue/enqueue pointers at first entry */
1248
out_be32(&priv->msg_regs->epwqbar, 0);
1249
out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1251
pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1252
in_be32(&priv->msg_regs->epwqbar),
1253
in_be32(&priv->msg_regs->pwqbar));
1255
/* Clear interrupt status IPWSR */
1256
out_be32(&priv->msg_regs->pwsr,
1257
(RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1259
/* Configure port write contoller for snooping enable all reporting,
1261
out_be32(&priv->msg_regs->pwmr,
1262
RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1265
/* Hook up port-write handler */
1266
rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1267
"port-write", (void *)mport);
1269
pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1273
INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1274
spin_lock_init(&priv->pw_fifo_lock);
1275
if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1276
pr_err("FIFO allocation failed\n");
1281
pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1282
in_be32(&priv->msg_regs->pwmr),
1283
in_be32(&priv->msg_regs->pwsr));
1288
free_irq(IRQ_RIO_PW(mport), (void *)mport);
1290
dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1291
priv->port_write_msg.virt,
1292
priv->port_write_msg.phys);
932
1296
static char *cmdline = NULL;
934
1298
static int fsl_rio_get_hdid(int index)
1014
1378
u64 law_start, law_size;
1015
1379
int paw, aw, sw;
1381
if (!dev->dev.of_node) {
1018
1382
dev_err(&dev->dev, "Device OF-Node is NULL");
1019
1383
return -EFAULT;
1022
rc = of_address_to_resource(dev->node, 0, ®s);
1386
rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
1024
1388
dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1025
dev->node->full_name);
1389
dev->dev.of_node->full_name);
1026
1390
return -EFAULT;
1028
dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
1392
dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1029
1393
dev_info(&dev->dev, "Regs: %pR\n", ®s);
1031
dt_range = of_get_property(dev->node, "ranges", &rlen);
1395
dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1032
1396
if (!dt_range) {
1033
1397
dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1034
dev->node->full_name);
1398
dev->dev.of_node->full_name);
1035
1399
return -EFAULT;
1038
1402
/* Get node address wide */
1039
cell = of_get_property(dev->node, "#address-cells", NULL);
1403
cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1043
aw = of_n_addr_cells(dev->node);
1407
aw = of_n_addr_cells(dev->dev.of_node);
1044
1408
/* Get node size wide */
1045
cell = of_get_property(dev->node, "#size-cells", NULL);
1409
cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1049
sw = of_n_size_cells(dev->node);
1413
sw = of_n_size_cells(dev->dev.of_node);
1050
1414
/* Get parent address wide wide */
1051
paw = of_n_addr_cells(dev->node);
1415
paw = of_n_addr_cells(dev->dev.of_node);
1053
1417
law_start = of_read_number(dt_range + aw, paw);
1054
1418
law_size = of_read_number(dt_range + aw + paw, sw);
1088
1453
port->iores.flags = IORESOURCE_MEM;
1089
1454
port->iores.name = "rio_io_win";
1091
priv->bellirq = irq_of_parse_and_map(dev->node, 2);
1092
priv->txirq = irq_of_parse_and_map(dev->node, 3);
1093
priv->rxirq = irq_of_parse_and_map(dev->node, 4);
1094
dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
1095
priv->txirq, priv->rxirq);
1456
priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1457
priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1458
priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1459
priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1460
dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1461
priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1097
1463
rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1098
1464
rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);