← Back to branch summary

~ubuntu-branches/debian/wheezy/linux-2.6/wheezy

« back to all changes in this revision

Viewing changes to drivers/net/wireless/ath/ath9k/eeprom_def.c

  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno, Martin Michlmayr
  • Date: 2011-04-06 13:53:30 UTC
  • mfrom: (43.1.5 sid)
  • Revision ID: james.westby@ubuntu.com-20110406135330-wjufxhd0tvn3zx4z
Tags: 2.6.38-3
http://bugs.debian.org/620124
http://bugs.debian.org/620284
http://bugs.debian.org/620204
[ Ben Hutchings ]
* [ppc64] Add to linux-tools package architectures (Closes: #620124)
* [amd64] Save cr4 to mmu_cr4_features at boot time (Closes: #620284)
* appletalk: Fix bugs introduced when removing use of BKL
* ALSA: Fix yet another race in disconnection
* cciss: Fix lost command issue
* ath9k: Fix kernel panic in AR2427
* ses: Avoid kernel panic when lun 0 is not mapped
* PCI/ACPI: Report ASPM support to BIOS if not disabled from command line

[ Aurelien Jarno ]
* rtlwifi: fix build when PCI is not enabled.

[ Martin Michlmayr ]
* rtlwifi: Eliminate udelay calls with too large values (Closes: #620204)

Show diffs side-by-side

added added

removed removed

Lines of Context:
drivers/net/wireless/ath/ath9k/eeprom_def.c
14
14
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15
15
 */
16
16
 
17
 
#include "ath9k.h"
 
17
#include "hw.h"
 
18
#include "ar9002_phy.h"
18
19
 
19
20
static void ath9k_get_txgain_index(struct ath_hw *ah,
20
21
                struct ath9k_channel *chan,
49
50
                i++;
50
51
 
51
52
        *pcdacIdx = i;
52
 
        return;
53
53
}
54
54
 
55
55
static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
89
89
static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90
90
{
91
91
#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
 
92
        struct ath_common *common = ath9k_hw_common(ah);
92
93
        u16 *eep_data = (u16 *)&ah->eeprom.def;
93
94
        int addr, ar5416_eep_start_loc = 0x100;
94
95
 
95
96
        for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96
 
                if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
 
97
                if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
97
98
                                         eep_data)) {
98
 
                        DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 
99
                        ath_err(ath9k_hw_common(ah),
99
100
                                "Unable to read eeprom region\n");
100
101
                        return false;
101
102
                }
109
110
{
110
111
        struct ar5416_eeprom_def *eep =
111
112
                (struct ar5416_eeprom_def *) &ah->eeprom.def;
 
113
        struct ath_common *common = ath9k_hw_common(ah);
112
114
        u16 *eepdata, temp, magic, magic2;
113
115
        u32 sum = 0, el;
114
116
        bool need_swap = false;
115
117
        int i, addr, size;
116
118
 
117
 
        if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118
 
                DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
 
119
        if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 
120
                ath_err(common, "Reading Magic # failed\n");
119
121
                return false;
120
122
        }
121
123
 
122
124
        if (!ath9k_hw_use_flash(ah)) {
123
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
125
                ath_dbg(common, ATH_DBG_EEPROM,
124
126
                        "Read Magic = 0x%04X\n", magic);
125
127
 
126
128
                if (magic != AR5416_EEPROM_MAGIC) {
137
139
                                        eepdata++;
138
140
                                }
139
141
                        } else {
140
 
                                DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
141
 
                                        "Invalid EEPROM Magic. "
142
 
                                        "Endianness mismatch.\n");
 
142
                                ath_err(common,
 
143
                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
143
144
                                return -EINVAL;
144
145
                        }
145
146
                }
146
147
        }
147
148
 
148
 
        DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 
149
        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
149
150
                need_swap ? "True" : "False");
150
151
 
151
152
        if (need_swap)
167
168
                u32 integer, j;
168
169
                u16 word;
169
170
 
170
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
171
                ath_dbg(common, ATH_DBG_EEPROM,
171
172
                        "EEPROM Endianness is not native.. Changing.\n");
172
173
 
173
174
                word = swab16(eep->baseEepHeader.length);
205
206
                                pModal->antCtrlChain[i] = integer;
206
207
                        }
207
208
 
208
 
                        for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 
209
                        for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
209
210
                                word = swab16(pModal->spurChans[i].spurChan);
210
211
                                pModal->spurChans[i].spurChan = word;
211
212
                        }
214
215
 
215
216
        if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216
217
            ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217
 
                DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
218
 
                        "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 
218
                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219
219
                        sum, ah->eep_ops->get_eeprom_ver(ah));
220
220
                return -EINVAL;
221
221
        }
222
222
 
 
223
        /* Enable fixup for AR_AN_TOP2 if necessary */
 
224
        if (AR_SREV_9280_20_OR_LATER(ah) &&
 
225
            (eep->baseEepHeader.version & 0xff) > 0x0a &&
 
226
            eep->baseEepHeader.pwdclkind == 0)
 
227
                ah->need_an_top2_fixup = 1;
 
228
 
 
229
        if ((common->bus_ops->ath_bus_type == ATH_USB) &&
 
230
            (AR_SREV_9280(ah)))
 
231
                eep->modalHeader[0].xpaBiasLvl = 0;
 
232
 
223
233
        return 0;
224
234
}
225
235
 
235
245
                return pModal[0].noiseFloorThreshCh[0];
236
246
        case EEP_NFTHRESH_2:
237
247
                return pModal[1].noiseFloorThreshCh[0];
238
 
        case AR_EEPROM_MAC(0):
 
248
        case EEP_MAC_LSW:
239
249
                return pBase->macAddr[0] << 8 | pBase->macAddr[1];
240
 
        case AR_EEPROM_MAC(1):
 
250
        case EEP_MAC_MID:
241
251
                return pBase->macAddr[2] << 8 | pBase->macAddr[3];
242
 
        case AR_EEPROM_MAC(2):
 
252
        case EEP_MAC_MSW:
243
253
                return pBase->macAddr[4] << 8 | pBase->macAddr[5];
244
254
        case EEP_REG_0:
245
255
                return pBase->regDmn[0];
265
275
                return pBase->txMask;
266
276
        case EEP_RX_MASK:
267
277
                return pBase->rxMask;
 
278
        case EEP_FSTCLK_5G:
 
279
                return pBase->fastClk5g;
268
280
        case EEP_RXGAIN_TYPE:
269
281
                return pBase->rxGainType;
270
282
        case EEP_TXGAIN_TYPE:
289
301
                        return pBase->frac_n_5g;
290
302
                else
291
303
                        return 0;
 
304
        case EEP_PWR_TABLE_OFFSET:
 
305
                if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 
306
                        return pBase->pwr_table_offset;
 
307
                else
 
308
                        return AR5416_PWR_TABLE_OFFSET_DB;
292
309
        default:
293
310
                return 0;
294
311
        }
302
319
        if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
303
320
                txRxAttenLocal = pModal->txRxAttenCh[i];
304
321
 
305
 
                if (AR_SREV_9280_10_OR_LATER(ah)) {
 
322
                if (AR_SREV_9280_20_OR_LATER(ah)) {
306
323
                        REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
307
324
                              AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
308
325
                              pModal->bswMargin[i]);
329
346
                }
330
347
        }
331
348
 
332
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
 
349
        if (AR_SREV_9280_20_OR_LATER(ah)) {
333
350
                REG_RMW_FIELD(ah,
334
351
                      AR_PHY_RXGAIN + regChainOffset,
335
352
                      AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
361
378
        pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
362
379
        txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
363
380
 
364
 
        REG_WRITE(ah, AR_PHY_SWITCH_COM,
365
 
                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 
381
        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
366
382
 
367
383
        for (i = 0; i < AR5416_MAX_CHAINS; i++) {
368
384
                if (AR_SREV_9280(ah)) {
393
409
                                              regChainOffset, i);
394
410
        }
395
411
 
396
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
 
412
        if (AR_SREV_9280_20_OR_LATER(ah)) {
397
413
                if (IS_CHAN_2GHZ(chan)) {
398
414
                        ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
399
415
                                                  AR_AN_RF2G1_CH0_OB,
436
452
                ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
437
453
                                          AR_AN_TOP2_LOCALBIAS,
438
454
                                          AR_AN_TOP2_LOCALBIAS_S,
439
 
                                          pModal->local_bias);
 
455
                                          !!(pModal->lna_ctl &
 
456
                                             LNA_CTL_LOCAL_BIAS));
440
457
                REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
441
 
                              pModal->force_xpaon);
 
458
                              !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
442
459
        }
443
460
 
444
461
        REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
446
463
        REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
447
464
                      pModal->adcDesiredSize);
448
465
 
449
 
        if (!AR_SREV_9280_10_OR_LATER(ah))
 
466
        if (!AR_SREV_9280_20_OR_LATER(ah))
450
467
                REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
451
468
                              AR_PHY_DESIRED_SZ_PGA,
452
469
                              pModal->pgaDesiredSize);
463
480
        REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
464
481
                      pModal->txEndToRxOn);
465
482
 
466
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
 
483
        if (AR_SREV_9280_20_OR_LATER(ah)) {
467
484
                REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
468
485
                              pModal->thresh62);
469
486
                REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
574
591
#undef XPA_LVL_FREQ
575
592
}
576
593
 
577
 
static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
578
 
                                struct ath9k_channel *chan,
579
 
                                struct cal_data_per_freq *pRawDataSet,
580
 
                                u8 *bChans, u16 availPiers,
581
 
                                u16 tPdGainOverlap, int16_t *pMinCalPower,
582
 
                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
583
 
                                u16 numXpdGains)
584
 
{
585
 
        int i, j, k;
586
 
        int16_t ss;
587
 
        u16 idxL = 0, idxR = 0, numPiers;
588
 
        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
589
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
590
 
        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
591
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
592
 
        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
593
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
594
 
 
595
 
        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
596
 
        u8 minPwrT4[AR5416_NUM_PD_GAINS];
597
 
        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
598
 
        int16_t vpdStep;
599
 
        int16_t tmpVal;
600
 
        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
601
 
        bool match;
602
 
        int16_t minDelta = 0;
603
 
        struct chan_centers centers;
604
 
 
605
 
        ath9k_hw_get_channel_centers(ah, chan, &centers);
606
 
 
607
 
        for (numPiers = 0; numPiers < availPiers; numPiers++) {
608
 
                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
609
 
                        break;
610
 
        }
611
 
 
612
 
        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
613
 
                                                             IS_CHAN_2GHZ(chan)),
614
 
                                               bChans, numPiers, &idxL, &idxR);
615
 
 
616
 
        if (match) {
617
 
                for (i = 0; i < numXpdGains; i++) {
618
 
                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
619
 
                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
620
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
621
 
                                        pRawDataSet[idxL].pwrPdg[i],
622
 
                                        pRawDataSet[idxL].vpdPdg[i],
623
 
                                        AR5416_PD_GAIN_ICEPTS,
624
 
                                        vpdTableI[i]);
625
 
                }
626
 
        } else {
627
 
                for (i = 0; i < numXpdGains; i++) {
628
 
                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
629
 
                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
630
 
                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
631
 
                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
632
 
 
633
 
                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
634
 
 
635
 
                        maxPwrT4[i] =
636
 
                                min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
637
 
                                    pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
638
 
 
639
 
 
640
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
641
 
                                                pPwrL, pVpdL,
642
 
                                                AR5416_PD_GAIN_ICEPTS,
643
 
                                                vpdTableL[i]);
644
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
645
 
                                                pPwrR, pVpdR,
646
 
                                                AR5416_PD_GAIN_ICEPTS,
647
 
                                                vpdTableR[i]);
648
 
 
649
 
                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
650
 
                                vpdTableI[i][j] =
651
 
                                        (u8)(ath9k_hw_interpolate((u16)
652
 
                                             FREQ2FBIN(centers.
653
 
                                                       synth_center,
654
 
                                                       IS_CHAN_2GHZ
655
 
                                                       (chan)),
656
 
                                             bChans[idxL], bChans[idxR],
657
 
                                             vpdTableL[i][j], vpdTableR[i][j]));
658
 
                        }
659
 
                }
660
 
        }
661
 
 
662
 
        *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
663
 
 
664
 
        k = 0;
665
 
 
666
 
        for (i = 0; i < numXpdGains; i++) {
667
 
                if (i == (numXpdGains - 1))
668
 
                        pPdGainBoundaries[i] =
669
 
                                (u16)(maxPwrT4[i] / 2);
670
 
                else
671
 
                        pPdGainBoundaries[i] =
672
 
                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
673
 
 
674
 
                pPdGainBoundaries[i] =
675
 
                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
676
 
 
677
 
                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
678
 
                        minDelta = pPdGainBoundaries[0] - 23;
679
 
                        pPdGainBoundaries[0] = 23;
680
 
                } else {
681
 
                        minDelta = 0;
682
 
                }
683
 
 
684
 
                if (i == 0) {
685
 
                        if (AR_SREV_9280_10_OR_LATER(ah))
686
 
                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
687
 
                        else
688
 
                                ss = 0;
689
 
                } else {
690
 
                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
691
 
                                        (minPwrT4[i] / 2)) -
692
 
                                       tPdGainOverlap + 1 + minDelta);
693
 
                }
694
 
                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
695
 
                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
696
 
 
697
 
                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
698
 
                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
699
 
                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
700
 
                        ss++;
701
 
                }
702
 
 
703
 
                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
704
 
                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
705
 
                                (minPwrT4[i] / 2));
706
 
                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
707
 
                        tgtIndex : sizeCurrVpdTable;
708
 
 
709
 
                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
710
 
                        pPDADCValues[k++] = vpdTableI[i][ss++];
711
 
                }
712
 
 
713
 
                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
714
 
                                    vpdTableI[i][sizeCurrVpdTable - 2]);
715
 
                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
716
 
 
717
 
                if (tgtIndex > maxIndex) {
718
 
                        while ((ss <= tgtIndex) &&
719
 
                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
720
 
                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
721
 
                                                    (ss - maxIndex + 1) * vpdStep));
722
 
                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
723
 
                                                         255 : tmpVal);
724
 
                                ss++;
725
 
                        }
726
 
                }
727
 
        }
728
 
 
729
 
        while (i < AR5416_PD_GAINS_IN_MASK) {
730
 
                pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
731
 
                i++;
732
 
        }
733
 
 
734
 
        while (k < AR5416_NUM_PDADC_VALUES) {
735
 
                pPDADCValues[k] = pPDADCValues[k - 1];
736
 
                k++;
737
 
        }
738
 
 
739
 
        return;
 
594
static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 
595
                                u16 *gb,
 
596
                                u16 numXpdGain,
 
597
                                u16 pdGainOverlap_t2,
 
598
                                int8_t pwr_table_offset,
 
599
                                int16_t *diff)
 
600
 
 
601
{
 
602
        u16 k;
 
603
 
 
604
        /* Prior to writing the boundaries or the pdadc vs. power table
 
605
         * into the chip registers the default starting point on the pdadc
 
606
         * vs. power table needs to be checked and the curve boundaries
 
607
         * adjusted accordingly
 
608
         */
 
609
        if (AR_SREV_9280_20_OR_LATER(ah)) {
 
610
                u16 gb_limit;
 
611
 
 
612
                if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 
613
                        /* get the difference in dB */
 
614
                        *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 
615
                        /* get the number of half dB steps */
 
616
                        *diff *= 2;
 
617
                        /* change the original gain boundary settings
 
618
                         * by the number of half dB steps
 
619
                         */
 
620
                        for (k = 0; k < numXpdGain; k++)
 
621
                                gb[k] = (u16)(gb[k] - *diff);
 
622
                }
 
623
                /* Because of a hardware limitation, ensure the gain boundary
 
624
                 * is not larger than (63 - overlap)
 
625
                 */
 
626
                gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 
627
 
 
628
                for (k = 0; k < numXpdGain; k++)
 
629
                        gb[k] = (u16)min(gb_limit, gb[k]);
 
630
        }
 
631
 
 
632
        return *diff;
 
633
}
 
634
 
 
635
static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 
636
                                      int8_t pwr_table_offset,
 
637
                                      int16_t diff,
 
638
                                      u8 *pdadcValues)
 
639
{
 
640
#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 
641
        u16 k;
 
642
 
 
643
        /* If this is a board that has a pwrTableOffset that differs from
 
644
         * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 
645
         * pdadc vs pwr table needs to be adjusted prior to writing to the
 
646
         * chip.
 
647
         */
 
648
        if (AR_SREV_9280_20_OR_LATER(ah)) {
 
649
                if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 
650
                        /* shift the table to start at the new offset */
 
651
                        for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 
652
                                pdadcValues[k] = pdadcValues[k + diff];
 
653
                        }
 
654
 
 
655
                        /* fill the back of the table */
 
656
                        for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 
657
                                pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 
658
                        }
 
659
                }
 
660
        }
 
661
#undef NUM_PDADC
740
662
}
741
663
 
742
664
static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
746
668
#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
747
669
#define SM_PDGAIN_B(x, y) \
748
670
                SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
749
 
 
 
671
        struct ath_common *common = ath9k_hw_common(ah);
750
672
        struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
751
673
        struct cal_data_per_freq *pRawDataset;
752
674
        u8 *pCalBChans = NULL;
754
676
        static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
755
677
        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
756
678
        u16 numPiers, i, j;
757
 
        int16_t tMinCalPower;
 
679
        int16_t diff = 0;
758
680
        u16 numXpdGain, xpdMask;
759
681
        u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
760
682
        u32 reg32, regOffset, regChainOffset;
761
683
        int16_t modalIdx;
 
684
        int8_t pwr_table_offset;
762
685
 
763
686
        modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
764
687
        xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
765
688
 
 
689
        pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 
690
 
766
691
        if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
767
692
            AR5416_EEP_MINOR_VER_2) {
768
693
                pdGainOverlap_t2 =
832
757
                                ath9k_olc_get_pdadcs(ah, pcdacIdx,
833
758
                                                     txPower/2, pdadcValues);
834
759
                        } else {
835
 
                                ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
 
760
                                ath9k_hw_get_gain_boundaries_pdadcs(ah,
836
761
                                                        chan, pRawDataset,
837
762
                                                        pCalBChans, numPiers,
838
763
                                                        pdGainOverlap_t2,
839
 
                                                        &tMinCalPower,
840
764
                                                        gainBoundaries,
841
765
                                                        pdadcValues,
842
766
                                                        numXpdGain);
843
767
                        }
844
768
 
 
769
                        diff = ath9k_change_gain_boundary_setting(ah,
 
770
                                                           gainBoundaries,
 
771
                                                           numXpdGain,
 
772
                                                           pdGainOverlap_t2,
 
773
                                                           pwr_table_offset,
 
774
                                                           &diff);
 
775
 
845
776
                        if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
846
777
                                if (OLC_FOR_AR9280_20_LATER) {
847
778
                                        REG_WRITE(ah,
862
793
                                }
863
794
                        }
864
795
 
 
796
 
 
797
                        ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 
798
                                                  diff, pdadcValues);
 
799
 
865
800
                        regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
866
801
                        for (j = 0; j < 32; j++) {
867
802
                                reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
870
805
                                        ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871
806
                                REG_WRITE(ah, regOffset, reg32);
872
807
 
873
 
                                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
808
                                ath_dbg(common, ATH_DBG_EEPROM,
874
809
                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
875
810
                                        i, regChainOffset, regOffset,
876
811
                                        reg32);
877
 
                                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
812
                                ath_dbg(common, ATH_DBG_EEPROM,
878
813
                                        "PDADC: Chain %d | PDADC %3d "
879
814
                                        "Value %3d | PDADC %3d Value %3d | "
880
815
                                        "PDADC %3d Value %3d | PDADC %3d "
882
817
                                        i, 4 * j, pdadcValues[4 * j],
883
818
                                        4 * j + 1, pdadcValues[4 * j + 1],
884
819
                                        4 * j + 2, pdadcValues[4 * j + 2],
885
 
                                        4 * j + 3,
886
 
                                        pdadcValues[4 * j + 3]);
 
820
                                        4 * j + 3, pdadcValues[4 * j + 3]);
887
821
 
888
822
                                regOffset += 4;
889
823
                        }
908
842
 
909
843
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
910
844
        struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
911
 
        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
845
        u16 twiceMaxEdgePower = MAX_RATE_POWER;
912
846
        static const u16 tpScaleReductionTable[5] =
913
 
                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 
847
                { 0, 3, 6, 9, MAX_RATE_POWER };
914
848
 
915
849
        int i;
916
850
        int16_t twiceLargestAntenna;
926
860
                0, {0, 0, 0, 0}
927
861
        };
928
862
        u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
929
 
        u16 ctlModesFor11a[] =
930
 
                { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
931
 
        u16 ctlModesFor11g[] =
932
 
                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
933
 
                  CTL_2GHT40
934
 
                };
935
 
        u16 numCtlModes, *pCtlMode, ctlMode, freq;
 
863
        static const u16 ctlModesFor11a[] = {
 
864
                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
 
865
        };
 
866
        static const u16 ctlModesFor11g[] = {
 
867
                CTL_11B, CTL_11G, CTL_2GHT20,
 
868
                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 
869
        };
 
870
        u16 numCtlModes;
 
871
        const u16 *pCtlMode;
 
872
        u16 ctlMode, freq;
936
873
        struct chan_centers centers;
937
874
        int tx_chainmask;
938
875
        u16 twiceMinEdgePower;
967
904
        case 1:
968
905
                break;
969
906
        case 2:
970
 
                scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 
907
                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
 
908
                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
 
909
                else
 
910
                        scaledPower = 0;
971
911
                break;
972
912
        case 3:
973
 
                scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 
913
                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
 
914
                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
 
915
                else
 
916
                        scaledPower = 0;
974
917
                break;
975
918
        }
976
919
 
977
 
        scaledPower = max((u16)0, scaledPower);
978
 
 
979
920
        if (IS_CHAN_2GHZ(chan)) {
980
921
                numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
981
922
                        SUB_NUM_CTL_MODES_AT_2G_40;
1048
989
 
1049
990
                if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1050
991
                    ah->eep_ops->get_eeprom_rev(ah) <= 2)
1051
 
                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
992
                        twiceMaxEdgePower = MAX_RATE_POWER;
1052
993
 
1053
994
                for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1054
995
                        if ((((cfgCtl & ~CTL_MODE_M) |
1163
1104
                                    u16 cfgCtl,
1164
1105
                                    u8 twiceAntennaReduction,
1165
1106
                                    u8 twiceMaxRegulatoryPower,
1166
 
                                    u8 powerLimit)
 
1107
                                    u8 powerLimit, bool test)
1167
1108
{
1168
1109
#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1169
1110
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1190
1131
 
1191
1132
        ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1192
1133
 
 
1134
        regulatory->max_power_level = 0;
1193
1135
        for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1194
1136
                ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1195
 
                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1196
 
                        ratesArray[i] = AR5416_MAX_RATE_POWER;
1197
 
        }
1198
 
 
1199
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
1200
 
                for (i = 0; i < Ar5416RateSize; i++)
1201
 
                        ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
 
1137
                if (ratesArray[i] > MAX_RATE_POWER)
 
1138
                        ratesArray[i] = MAX_RATE_POWER;
 
1139
                if (ratesArray[i] > regulatory->max_power_level)
 
1140
                        regulatory->max_power_level = ratesArray[i];
 
1141
        }
 
1142
 
 
1143
        if (!test) {
 
1144
                i = rate6mb;
 
1145
 
 
1146
                if (IS_CHAN_HT40(chan))
 
1147
                        i = rateHt40_0;
 
1148
                else if (IS_CHAN_HT20(chan))
 
1149
                        i = rateHt20_0;
 
1150
 
 
1151
                regulatory->max_power_level = ratesArray[i];
 
1152
        }
 
1153
 
 
1154
        switch(ar5416_get_ntxchains(ah->txchainmask)) {
 
1155
        case 1:
 
1156
                break;
 
1157
        case 2:
 
1158
                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
 
1159
                break;
 
1160
        case 3:
 
1161
                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
 
1162
                break;
 
1163
        default:
 
1164
                ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
 
1165
                        "Invalid chainmask configuration\n");
 
1166
                break;
 
1167
        }
 
1168
 
 
1169
        if (test)
 
1170
                return;
 
1171
 
 
1172
        if (AR_SREV_9280_20_OR_LATER(ah)) {
 
1173
                for (i = 0; i < Ar5416RateSize; i++) {
 
1174
                        int8_t pwr_table_offset;
 
1175
 
 
1176
                        pwr_table_offset = ah->eep_ops->get_eeprom(ah,
 
1177
                                                        EEP_PWR_TABLE_OFFSET);
 
1178
                        ratesArray[i] -= pwr_table_offset * 2;
 
1179
                }
1202
1180
        }
1203
1181
 
1204
1182
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1287
1265
        REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1288
1266
                  ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1289
1267
                  | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1290
 
 
1291
 
        i = rate6mb;
1292
 
 
1293
 
        if (IS_CHAN_HT40(chan))
1294
 
                i = rateHt40_0;
1295
 
        else if (IS_CHAN_HT20(chan))
1296
 
                i = rateHt20_0;
1297
 
 
1298
 
        if (AR_SREV_9280_10_OR_LATER(ah))
1299
 
                regulatory->max_power_level =
1300
 
                        ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1301
 
        else
1302
 
                regulatory->max_power_level = ratesArray[i];
1303
 
 
1304
 
        switch(ar5416_get_ntxchains(ah->txchainmask)) {
1305
 
        case 1:
1306
 
                break;
1307
 
        case 2:
1308
 
                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1309
 
                break;
1310
 
        case 3:
1311
 
                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312
 
                break;
1313
 
        default:
1314
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1315
 
                        "Invalid chainmask configuration\n");
1316
 
                break;
1317
 
        }
1318
 
}
1319
 
 
1320
 
static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1321
 
                                          enum ieee80211_band freq_band)
1322
 
{
1323
 
        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1324
 
        struct modal_eep_header *pModal =
1325
 
                &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1326
 
        struct base_eep_header *pBase = &eep->baseEepHeader;
1327
 
        u8 num_ant_config;
1328
 
 
1329
 
        num_ant_config = 1;
1330
 
 
1331
 
        if (pBase->version >= 0x0E0D)
1332
 
                if (pModal->useAnt1)
1333
 
                        num_ant_config += 1;
1334
 
 
1335
 
        return num_ant_config;
1336
 
}
1337
 
 
1338
 
static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1339
 
                                               struct ath9k_channel *chan)
1340
 
{
1341
 
        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1342
 
        struct modal_eep_header *pModal =
1343
 
                &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1344
 
 
1345
 
        return pModal->antCtrlCommon & 0xFFFF;
1346
1268
}
1347
1269
 
1348
1270
static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1349
1271
{
1350
1272
#define EEP_DEF_SPURCHAN \
1351
1273
        (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
 
1274
        struct ath_common *common = ath9k_hw_common(ah);
1352
1275
 
1353
1276
        u16 spur_val = AR_NO_SPUR;
1354
1277
 
1355
 
        DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1356
 
                "Getting spur idx %d is2Ghz. %d val %x\n",
 
1278
        ath_dbg(common, ATH_DBG_ANI,
 
1279
                "Getting spur idx:%d is2Ghz:%d val:%x\n",
1357
1280
                i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358
1281
 
1359
1282
        switch (ah->config.spurmode) {
1361
1284
                break;
1362
1285
        case SPUR_ENABLE_IOCTL:
1363
1286
                spur_val = ah->config.spurchans[i][is2GHz];
1364
 
                DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 
1287
                ath_dbg(common, ATH_DBG_ANI,
1365
1288
                        "Getting spur val from new loc. %d\n", spur_val);
1366
1289
                break;
1367
1290
        case SPUR_ENABLE_EEPROM:
1380
1303
        .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1381
1304
        .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1382
1305
        .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1383
 
        .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1384
 
        .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1385
1306
        .set_board_values       = ath9k_hw_def_set_board_values,
1386
1307
        .set_addac              = ath9k_hw_def_set_addac,
1387
1308
        .set_txpower            = ath9k_hw_def_set_txpower,