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/* linux/drivers/serial/samsuing.c
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* Driver core for Samsung SoC onboard UARTs.
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* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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/* Hote on 2410 error handling
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* The s3c2410 manual has a love/hate affair with the contents of the
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* UERSTAT register in the UART blocks, and keeps marking some of the
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* error bits as reserved. Having checked with the s3c2410x01,
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* it copes with BREAKs properly, so I am happy to ignore the RESERVED
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* feature from the latter versions of the manual.
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* If it becomes aparrent that latter versions of the 2410 remove these
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* bits, then action will have to be taken to differentiate the versions
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* and change the policy on BREAK
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#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/sysrq.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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/* UART name and device definitions */
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#define S3C24XX_SERIAL_NAME "ttySAC"
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#define S3C24XX_SERIAL_MAJOR 204
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#define S3C24XX_SERIAL_MINOR 64
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/* macros to change one thing to another */
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#define tx_enabled(port) ((port)->unused[0])
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#define rx_enabled(port) ((port)->unused[1])
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/* flag to ignore all characters comming in */
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#define RXSTAT_DUMMY_READ (0x10000000)
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static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
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return container_of(port, struct s3c24xx_uart_port, port);
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/* translate a port to the device name */
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static inline const char *s3c24xx_serial_portname(struct uart_port *port)
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return to_platform_device(port->dev)->name;
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static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
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return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
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static void s3c24xx_serial_rx_enable(struct uart_port *port)
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unsigned int ucon, ufcon;
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spin_lock_irqsave(&port->lock, flags);
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while (--count && !s3c24xx_serial_txempty_nofifo(port))
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ufcon = rd_regl(port, S3C2410_UFCON);
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ufcon |= S3C2410_UFCON_RESETRX;
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wr_regl(port, S3C2410_UFCON, ufcon);
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ucon = rd_regl(port, S3C2410_UCON);
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ucon |= S3C2410_UCON_RXIRQMODE;
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wr_regl(port, S3C2410_UCON, ucon);
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rx_enabled(port) = 1;
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spin_unlock_irqrestore(&port->lock, flags);
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static void s3c24xx_serial_rx_disable(struct uart_port *port)
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spin_lock_irqsave(&port->lock, flags);
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ucon = rd_regl(port, S3C2410_UCON);
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ucon &= ~S3C2410_UCON_RXIRQMODE;
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wr_regl(port, S3C2410_UCON, ucon);
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rx_enabled(port) = 0;
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spin_unlock_irqrestore(&port->lock, flags);
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static void s3c24xx_serial_stop_tx(struct uart_port *port)
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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if (tx_enabled(port)) {
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disable_irq_nosync(ourport->tx_irq);
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tx_enabled(port) = 0;
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if (port->flags & UPF_CONS_FLOW)
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s3c24xx_serial_rx_enable(port);
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static void s3c24xx_serial_start_tx(struct uart_port *port)
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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if (!tx_enabled(port)) {
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if (port->flags & UPF_CONS_FLOW)
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s3c24xx_serial_rx_disable(port);
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enable_irq(ourport->tx_irq);
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tx_enabled(port) = 1;
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static void s3c24xx_serial_stop_rx(struct uart_port *port)
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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if (rx_enabled(port)) {
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dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
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disable_irq_nosync(ourport->rx_irq);
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rx_enabled(port) = 0;
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static void s3c24xx_serial_enable_ms(struct uart_port *port)
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static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
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return to_ourport(port)->info;
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static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
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if (port->dev == NULL)
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return (struct s3c2410_uartcfg *)port->dev->platform_data;
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static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
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unsigned long ufstat)
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struct s3c24xx_uart_info *info = ourport->info;
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if (ufstat & info->rx_fifofull)
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return info->fifosize;
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return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
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/* ? - where has parity gone?? */
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#define S3C2410_UERSTAT_PARITY (0x1000)
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s3c24xx_serial_rx_chars(int irq, void *dev_id)
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struct s3c24xx_uart_port *ourport = dev_id;
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struct uart_port *port = &ourport->port;
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struct tty_struct *tty = port->state->port.tty;
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unsigned int ufcon, ch, flag, ufstat, uerstat;
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while (max_count-- > 0) {
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ufcon = rd_regl(port, S3C2410_UFCON);
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ufstat = rd_regl(port, S3C2410_UFSTAT);
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if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
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uerstat = rd_regl(port, S3C2410_UERSTAT);
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ch = rd_regb(port, S3C2410_URXH);
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if (port->flags & UPF_CONS_FLOW) {
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int txe = s3c24xx_serial_txempty_nofifo(port);
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if (rx_enabled(port)) {
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rx_enabled(port) = 0;
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ufcon |= S3C2410_UFCON_RESETRX;
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wr_regl(port, S3C2410_UFCON, ufcon);
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rx_enabled(port) = 1;
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/* insert the character into the buffer */
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if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
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dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
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/* check for break */
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if (uerstat & S3C2410_UERSTAT_BREAK) {
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if (uart_handle_break(port))
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if (uerstat & S3C2410_UERSTAT_FRAME)
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port->icount.frame++;
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if (uerstat & S3C2410_UERSTAT_OVERRUN)
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port->icount.overrun++;
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uerstat &= port->read_status_mask;
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if (uerstat & S3C2410_UERSTAT_BREAK)
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else if (uerstat & S3C2410_UERSTAT_PARITY)
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else if (uerstat & (S3C2410_UERSTAT_FRAME |
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S3C2410_UERSTAT_OVERRUN))
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if (uart_handle_sysrq_char(port, ch))
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uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
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tty_flip_buffer_push(tty);
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static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
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struct s3c24xx_uart_port *ourport = id;
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struct uart_port *port = &ourport->port;
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struct circ_buf *xmit = &port->state->xmit;
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wr_regb(port, S3C2410_UTXH, port->x_char);
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/* if there isnt anything more to transmit, or the uart is now
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* stopped, disable the uart and exit
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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s3c24xx_serial_stop_tx(port);
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/* try and drain the buffer... */
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while (!uart_circ_empty(xmit) && count-- > 0) {
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if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
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wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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if (uart_circ_empty(xmit))
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s3c24xx_serial_stop_tx(port);
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static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
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unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
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if (ufcon & S3C2410_UFCON_FIFOMODE) {
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if ((ufstat & info->tx_fifomask) != 0 ||
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(ufstat & info->tx_fifofull))
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return s3c24xx_serial_txempty_nofifo(port);
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/* no modem control lines */
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static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
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unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
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if (umstat & S3C2410_UMSTAT_CTS)
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
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return TIOCM_CAR | TIOCM_DSR;
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static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
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/* todo - possibly remove AFC and do manual CTS */
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static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
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spin_lock_irqsave(&port->lock, flags);
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ucon = rd_regl(port, S3C2410_UCON);
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ucon |= S3C2410_UCON_SBREAK;
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ucon &= ~S3C2410_UCON_SBREAK;
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wr_regl(port, S3C2410_UCON, ucon);
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spin_unlock_irqrestore(&port->lock, flags);
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static void s3c24xx_serial_shutdown(struct uart_port *port)
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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if (ourport->tx_claimed) {
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free_irq(ourport->tx_irq, ourport);
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tx_enabled(port) = 0;
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ourport->tx_claimed = 0;
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if (ourport->rx_claimed) {
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free_irq(ourport->rx_irq, ourport);
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ourport->rx_claimed = 0;
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rx_enabled(port) = 0;
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static int s3c24xx_serial_startup(struct uart_port *port)
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
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port->mapbase, port->membase);
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rx_enabled(port) = 1;
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ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
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s3c24xx_serial_portname(port), ourport);
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printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
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ourport->rx_claimed = 1;
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dbg("requesting tx irq...\n");
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tx_enabled(port) = 1;
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ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
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s3c24xx_serial_portname(port), ourport);
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printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
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ourport->tx_claimed = 1;
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dbg("s3c24xx_serial_startup ok\n");
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/* the port reset code should have done the correct
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* register setup for the port controls */
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s3c24xx_serial_shutdown(port);
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/* power power management control */
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static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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ourport->pm_level = level;
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if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
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clk_disable(ourport->baudclk);
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clk_disable(ourport->clk);
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clk_enable(ourport->clk);
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if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
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clk_enable(ourport->baudclk);
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printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
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/* baud rate calculation
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* The UARTs on the S3C2410/S3C2440 can take their clocks from a number
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* of different sources, including the peripheral clock ("pclk") and an
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* external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
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* with a programmable extra divisor.
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* The following code goes through the clock sources, and calculates the
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* baud clocks (and the resultant actual baud rates) and then tries to
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* pick the closest one and select that.
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static struct s3c24xx_uart_clksrc tmp_clksrc = {
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s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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return (info->get_clksrc)(port, c);
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s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
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struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
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return (info->set_clksrc)(port, c);
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struct s3c24xx_uart_clksrc *clksrc;
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unsigned int divslot;
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static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
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struct uart_port *port,
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struct s3c24xx_uart_clksrc *clksrc,
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struct s3c24xx_uart_port *ourport = to_ourport(port);
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calc->src = clk_get(port->dev, clksrc->name);
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if (calc->src == NULL || IS_ERR(calc->src))
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rate = clk_get_rate(calc->src);
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rate /= clksrc->divisor;
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calc->clksrc = clksrc;
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if (ourport->info->has_divslot) {
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unsigned long div = rate / baud;
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/* The UDIVSLOT register on the newer UARTs allows us to
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* get a divisor adjustment of 1/16th on the baud clock.
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* We don't keep the UDIVSLOT value (the 16ths we calculated
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* by not multiplying the baud by 16) as it is easy enough
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calc->quot = div / 16;
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calc->calc = rate / div;
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calc->quot = (rate + (8 * baud)) / (16 * baud);
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calc->calc = (rate / (calc->quot * 16));
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static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
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struct s3c24xx_uart_clksrc **clksrc,
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struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
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struct s3c24xx_uart_clksrc *clkp;
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struct baud_calc res[MAX_CLKS];
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struct baud_calc *resptr, *best, *sptr;
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if (cfg->clocks_size < 2) {
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if (cfg->clocks_size == 0)
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/* check to see if we're sourcing fclk, and if so we're
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* going to have to update the clock source
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if (strcmp(clkp->name, "fclk") == 0) {
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struct s3c24xx_uart_clksrc src;
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s3c24xx_serial_getsource(port, &src);
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/* check that the port already using fclk, and if
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* not, then re-select fclk
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if (strcmp(src.name, clkp->name) == 0) {
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s3c24xx_serial_setsource(port, clkp);
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s3c24xx_serial_getsource(port, &src);
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clkp->divisor = src.divisor;
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s3c24xx_serial_calcbaud(res, port, clkp, baud);
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for (i = 0; i < cfg->clocks_size; i++, clkp++) {
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if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
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/* ok, we now need to select the best clock we found */
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unsigned int deviation = (1<<30)|((1<<30)-1);
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for (sptr = res; sptr < resptr; sptr++) {
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calc_deviation = baud - sptr->calc;
614
if (calc_deviation < 0)
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calc_deviation = -calc_deviation;
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if (calc_deviation < deviation) {
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deviation = calc_deviation;
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/* store results to pass back */
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*clksrc = best->clksrc;
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* This table takes the fractional value of the baud divisor and gives
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* the recommended setting for the UDIVSLOT register.
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static u16 udivslot_table[16] = {
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static void s3c24xx_serial_set_termios(struct uart_port *port,
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struct ktermios *termios,
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struct ktermios *old)
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struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
661
struct s3c24xx_uart_port *ourport = to_ourport(port);
662
struct s3c24xx_uart_clksrc *clksrc = NULL;
663
struct clk *clk = NULL;
665
unsigned int baud, quot;
668
unsigned int udivslot = 0;
671
* We don't support modem control lines.
673
termios->c_cflag &= ~(HUPCL | CMSPAR);
674
termios->c_cflag |= CLOCAL;
677
* Ask the core to calculate the divisor for us.
680
baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
682
if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
683
quot = port->custom_divisor;
685
quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
687
/* check to see if we need to change clock source */
689
if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
690
dbg("selecting clock %p\n", clk);
691
s3c24xx_serial_setsource(port, clksrc);
693
if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
694
clk_disable(ourport->baudclk);
695
ourport->baudclk = NULL;
700
ourport->clksrc = clksrc;
701
ourport->baudclk = clk;
702
ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
705
if (ourport->info->has_divslot) {
706
unsigned int div = ourport->baudclk_rate / baud;
708
if (cfg->has_fracval) {
709
udivslot = (div & 15);
710
dbg("fracval = %04x\n", udivslot);
712
udivslot = udivslot_table[div & 15];
713
dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
717
switch (termios->c_cflag & CSIZE) {
719
dbg("config: 5bits/char\n");
720
ulcon = S3C2410_LCON_CS5;
723
dbg("config: 6bits/char\n");
724
ulcon = S3C2410_LCON_CS6;
727
dbg("config: 7bits/char\n");
728
ulcon = S3C2410_LCON_CS7;
732
dbg("config: 8bits/char\n");
733
ulcon = S3C2410_LCON_CS8;
737
/* preserve original lcon IR settings */
738
ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
740
if (termios->c_cflag & CSTOPB)
741
ulcon |= S3C2410_LCON_STOPB;
743
umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
745
if (termios->c_cflag & PARENB) {
746
if (termios->c_cflag & PARODD)
747
ulcon |= S3C2410_LCON_PODD;
749
ulcon |= S3C2410_LCON_PEVEN;
751
ulcon |= S3C2410_LCON_PNONE;
754
spin_lock_irqsave(&port->lock, flags);
756
dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
757
ulcon, quot, udivslot);
759
wr_regl(port, S3C2410_ULCON, ulcon);
760
wr_regl(port, S3C2410_UBRDIV, quot);
761
wr_regl(port, S3C2410_UMCON, umcon);
763
if (ourport->info->has_divslot)
764
wr_regl(port, S3C2443_DIVSLOT, udivslot);
766
dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
767
rd_regl(port, S3C2410_ULCON),
768
rd_regl(port, S3C2410_UCON),
769
rd_regl(port, S3C2410_UFCON));
772
* Update the per-port timeout.
774
uart_update_timeout(port, termios->c_cflag, baud);
777
* Which character status flags are we interested in?
779
port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
780
if (termios->c_iflag & INPCK)
781
port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
784
* Which character status flags should we ignore?
786
port->ignore_status_mask = 0;
787
if (termios->c_iflag & IGNPAR)
788
port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
789
if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
790
port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
793
* Ignore all characters if CREAD is not set.
795
if ((termios->c_cflag & CREAD) == 0)
796
port->ignore_status_mask |= RXSTAT_DUMMY_READ;
798
spin_unlock_irqrestore(&port->lock, flags);
801
static const char *s3c24xx_serial_type(struct uart_port *port)
803
switch (port->type) {
817
#define MAP_SIZE (0x100)
819
static void s3c24xx_serial_release_port(struct uart_port *port)
821
release_mem_region(port->mapbase, MAP_SIZE);
824
static int s3c24xx_serial_request_port(struct uart_port *port)
826
const char *name = s3c24xx_serial_portname(port);
827
return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
830
static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
832
struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
834
if (flags & UART_CONFIG_TYPE &&
835
s3c24xx_serial_request_port(port) == 0)
836
port->type = info->type;
840
* verify the new serial_struct (for TIOCSSERIAL).
843
s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
845
struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
847
if (ser->type != PORT_UNKNOWN && ser->type != info->type)
854
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
856
static struct console s3c24xx_serial_console;
858
#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
860
#define S3C24XX_SERIAL_CONSOLE NULL
863
static struct uart_ops s3c24xx_serial_ops = {
864
.pm = s3c24xx_serial_pm,
865
.tx_empty = s3c24xx_serial_tx_empty,
866
.get_mctrl = s3c24xx_serial_get_mctrl,
867
.set_mctrl = s3c24xx_serial_set_mctrl,
868
.stop_tx = s3c24xx_serial_stop_tx,
869
.start_tx = s3c24xx_serial_start_tx,
870
.stop_rx = s3c24xx_serial_stop_rx,
871
.enable_ms = s3c24xx_serial_enable_ms,
872
.break_ctl = s3c24xx_serial_break_ctl,
873
.startup = s3c24xx_serial_startup,
874
.shutdown = s3c24xx_serial_shutdown,
875
.set_termios = s3c24xx_serial_set_termios,
876
.type = s3c24xx_serial_type,
877
.release_port = s3c24xx_serial_release_port,
878
.request_port = s3c24xx_serial_request_port,
879
.config_port = s3c24xx_serial_config_port,
880
.verify_port = s3c24xx_serial_verify_port,
884
static struct uart_driver s3c24xx_uart_drv = {
885
.owner = THIS_MODULE,
886
.driver_name = "s3c2410_serial",
887
.nr = CONFIG_SERIAL_SAMSUNG_UARTS,
888
.cons = S3C24XX_SERIAL_CONSOLE,
889
.dev_name = S3C24XX_SERIAL_NAME,
890
.major = S3C24XX_SERIAL_MAJOR,
891
.minor = S3C24XX_SERIAL_MINOR,
894
static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
897
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
899
.irq = IRQ_S3CUART_RX0,
902
.ops = &s3c24xx_serial_ops,
903
.flags = UPF_BOOT_AUTOCONF,
909
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
911
.irq = IRQ_S3CUART_RX1,
914
.ops = &s3c24xx_serial_ops,
915
.flags = UPF_BOOT_AUTOCONF,
919
#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
923
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
925
.irq = IRQ_S3CUART_RX2,
928
.ops = &s3c24xx_serial_ops,
929
.flags = UPF_BOOT_AUTOCONF,
934
#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
937
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
939
.irq = IRQ_S3CUART_RX3,
942
.ops = &s3c24xx_serial_ops,
943
.flags = UPF_BOOT_AUTOCONF,
950
/* s3c24xx_serial_resetport
952
* wrapper to call the specific reset for this port (reset the fifos
956
static inline int s3c24xx_serial_resetport(struct uart_port *port,
957
struct s3c2410_uartcfg *cfg)
959
struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
961
return (info->reset_port)(port, cfg);
965
#ifdef CONFIG_CPU_FREQ
967
static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
968
unsigned long val, void *data)
970
struct s3c24xx_uart_port *port;
971
struct uart_port *uport;
973
port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
976
/* check to see if port is enabled */
978
if (port->pm_level != 0)
981
/* try and work out if the baudrate is changing, we can detect
982
* a change in rate, but we do not have support for detecting
983
* a disturbance in the clock-rate over the change.
986
if (IS_ERR(port->clk))
989
if (port->baudclk_rate == clk_get_rate(port->clk))
992
if (val == CPUFREQ_PRECHANGE) {
993
/* we should really shut the port down whilst the
994
* frequency change is in progress. */
996
} else if (val == CPUFREQ_POSTCHANGE) {
997
struct ktermios *termios;
998
struct tty_struct *tty;
1000
if (uport->state == NULL)
1003
tty = uport->state->port.tty;
1008
termios = tty->termios;
1010
if (termios == NULL) {
1011
printk(KERN_WARNING "%s: no termios?\n", __func__);
1015
s3c24xx_serial_set_termios(uport, termios, NULL);
1022
static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1024
port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1026
return cpufreq_register_notifier(&port->freq_transition,
1027
CPUFREQ_TRANSITION_NOTIFIER);
1030
static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1032
cpufreq_unregister_notifier(&port->freq_transition,
1033
CPUFREQ_TRANSITION_NOTIFIER);
1037
static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1042
static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1047
/* s3c24xx_serial_init_port
1049
* initialise a single serial port from the platform device given
1052
static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1053
struct s3c24xx_uart_info *info,
1054
struct platform_device *platdev)
1056
struct uart_port *port = &ourport->port;
1057
struct s3c2410_uartcfg *cfg;
1058
struct resource *res;
1061
dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1063
if (platdev == NULL)
1066
cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1068
if (port->mapbase != 0)
1071
if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1072
printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1073
cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1077
/* setup info for port */
1078
port->dev = &platdev->dev;
1079
ourport->info = info;
1081
/* copy the info in from provided structure */
1082
ourport->port.fifosize = info->fifosize;
1084
dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1088
if (cfg->uart_flags & UPF_CONS_FLOW) {
1089
dbg("s3c24xx_serial_init_port: enabling flow control\n");
1090
port->flags |= UPF_CONS_FLOW;
1093
/* sort our the physical and virtual addresses for each UART */
1095
res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1097
printk(KERN_ERR "failed to find memory resource for uart\n");
1101
dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1103
port->mapbase = res->start;
1104
port->membase = S3C_VA_UART + (res->start & 0xfffff);
1105
ret = platform_get_irq(platdev, 0);
1110
ourport->rx_irq = ret;
1111
ourport->tx_irq = ret + 1;
1114
ret = platform_get_irq(platdev, 1);
1116
ourport->tx_irq = ret;
1118
ourport->clk = clk_get(&platdev->dev, "uart");
1120
dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1121
port->mapbase, port->membase, port->irq,
1122
ourport->rx_irq, ourport->tx_irq, port->uartclk);
1124
/* reset the fifos (and setup the uart) */
1125
s3c24xx_serial_resetport(port, cfg);
1129
static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1130
struct device_attribute *attr,
1133
struct uart_port *port = s3c24xx_dev_to_port(dev);
1134
struct s3c24xx_uart_port *ourport = to_ourport(port);
1136
return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1139
static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1141
/* Device driver serial port probe */
1143
static int probe_index;
1145
int s3c24xx_serial_probe(struct platform_device *dev,
1146
struct s3c24xx_uart_info *info)
1148
struct s3c24xx_uart_port *ourport;
1151
dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1153
ourport = &s3c24xx_serial_ports[probe_index];
1156
dbg("%s: initialising port %p...\n", __func__, ourport);
1158
ret = s3c24xx_serial_init_port(ourport, info, dev);
1162
dbg("%s: adding port\n", __func__);
1163
uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1164
platform_set_drvdata(dev, &ourport->port);
1166
ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1168
printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1170
ret = s3c24xx_serial_cpufreq_register(ourport);
1172
dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1180
EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1182
int __devexit s3c24xx_serial_remove(struct platform_device *dev)
1184
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1187
s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1188
device_remove_file(&dev->dev, &dev_attr_clock_source);
1189
uart_remove_one_port(&s3c24xx_uart_drv, port);
1195
EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1197
/* UART power management code */
1201
static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1203
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1206
uart_suspend_port(&s3c24xx_uart_drv, port);
1211
static int s3c24xx_serial_resume(struct platform_device *dev)
1213
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1214
struct s3c24xx_uart_port *ourport = to_ourport(port);
1217
clk_enable(ourport->clk);
1218
s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1219
clk_disable(ourport->clk);
1221
uart_resume_port(&s3c24xx_uart_drv, port);
1228
int s3c24xx_serial_init(struct platform_driver *drv,
1229
struct s3c24xx_uart_info *info)
1231
dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1234
drv->suspend = s3c24xx_serial_suspend;
1235
drv->resume = s3c24xx_serial_resume;
1238
return platform_driver_register(drv);
1241
EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1243
/* module initialisation code */
1245
static int __init s3c24xx_serial_modinit(void)
1249
ret = uart_register_driver(&s3c24xx_uart_drv);
1251
printk(KERN_ERR "failed to register UART driver\n");
1258
static void __exit s3c24xx_serial_modexit(void)
1260
uart_unregister_driver(&s3c24xx_uart_drv);
1263
module_init(s3c24xx_serial_modinit);
1264
module_exit(s3c24xx_serial_modexit);
1268
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1270
static struct uart_port *cons_uart;
1273
s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1275
struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1276
unsigned long ufstat, utrstat;
1278
if (ufcon & S3C2410_UFCON_FIFOMODE) {
1279
/* fifo mode - check amount of data in fifo registers... */
1281
ufstat = rd_regl(port, S3C2410_UFSTAT);
1282
return (ufstat & info->tx_fifofull) ? 0 : 1;
1285
/* in non-fifo mode, we go and use the tx buffer empty */
1287
utrstat = rd_regl(port, S3C2410_UTRSTAT);
1288
return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1292
s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1294
unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1295
while (!s3c24xx_serial_console_txrdy(port, ufcon))
1297
wr_regb(cons_uart, S3C2410_UTXH, ch);
1301
s3c24xx_serial_console_write(struct console *co, const char *s,
1304
uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1308
s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1309
int *parity, int *bits)
1311
struct s3c24xx_uart_clksrc clksrc;
1315
unsigned int ubrdiv;
1318
ulcon = rd_regl(port, S3C2410_ULCON);
1319
ucon = rd_regl(port, S3C2410_UCON);
1320
ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1322
dbg("s3c24xx_serial_get_options: port=%p\n"
1323
"registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1324
port, ulcon, ucon, ubrdiv);
1326
if ((ucon & 0xf) != 0) {
1327
/* consider the serial port configured if the tx/rx mode set */
1329
switch (ulcon & S3C2410_LCON_CSMASK) {
1330
case S3C2410_LCON_CS5:
1333
case S3C2410_LCON_CS6:
1336
case S3C2410_LCON_CS7:
1340
case S3C2410_LCON_CS8:
1345
switch (ulcon & S3C2410_LCON_PMASK) {
1346
case S3C2410_LCON_PEVEN:
1350
case S3C2410_LCON_PODD:
1354
case S3C2410_LCON_PNONE:
1359
/* now calculate the baud rate */
1361
s3c24xx_serial_getsource(port, &clksrc);
1363
clk = clk_get(port->dev, clksrc.name);
1364
if (!IS_ERR(clk) && clk != NULL)
1365
rate = clk_get_rate(clk) / clksrc.divisor;
1370
*baud = rate / (16 * (ubrdiv + 1));
1371
dbg("calculated baud %d\n", *baud);
1376
/* s3c24xx_serial_init_ports
1378
* initialise the serial ports from the machine provided initialisation
1382
static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info)
1384
struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1385
struct platform_device **platdev_ptr;
1388
dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1390
platdev_ptr = s3c24xx_uart_devs;
1392
for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
1393
s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr);
1400
s3c24xx_serial_console_setup(struct console *co, char *options)
1402
struct uart_port *port;
1408
dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1409
co, co->index, options);
1411
/* is this a valid port */
1413
if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1416
port = &s3c24xx_serial_ports[co->index].port;
1418
/* is the port configured? */
1420
if (port->mapbase == 0x0) {
1422
port = &s3c24xx_serial_ports[co->index].port;
1427
dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1430
* Check whether an invalid uart number has been specified, and
1431
* if so, search for the first available port that does have
1435
uart_parse_options(options, &baud, &parity, &bits, &flow);
1437
s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1439
dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1441
return uart_set_options(port, co, baud, parity, bits, flow);
1444
/* s3c24xx_serial_initconsole
1446
* initialise the console from one of the uart drivers
1449
static struct console s3c24xx_serial_console = {
1450
.name = S3C24XX_SERIAL_NAME,
1451
.device = uart_console_device,
1452
.flags = CON_PRINTBUFFER,
1454
.write = s3c24xx_serial_console_write,
1455
.setup = s3c24xx_serial_console_setup
1458
int s3c24xx_serial_initconsole(struct platform_driver *drv,
1459
struct s3c24xx_uart_info **info)
1462
struct platform_device *dev = s3c24xx_uart_devs[0];
1464
dbg("s3c24xx_serial_initconsole\n");
1466
/* select driver based on the cpu */
1469
printk(KERN_ERR "s3c24xx: no devices for console init\n");
1473
if (strcmp(dev->name, drv->driver.name) != 0)
1476
s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1477
s3c24xx_serial_init_ports(info);
1479
register_console(&s3c24xx_serial_console);
1483
#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1485
MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1486
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1487
MODULE_LICENSE("GPL v2");