2
* linux/drivers/video/omap2/dss/rfbi.c
4
* Copyright (C) 2009 Nokia Corporation
5
* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7
* Some code and ideas taken from drivers/video/omap/ driver
10
* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
12
* the Free Software Foundation.
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* This program is distributed in the hope that it will be useful, but WITHOUT
15
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19
* You should have received a copy of the GNU General Public License along with
20
* this program. If not, see <http://www.gnu.org/licenses/>.
23
#define DSS_SUBSYS_NAME "RFBI"
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/vmalloc.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/kfifo.h>
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#include <linux/ktime.h>
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#include <linux/hrtimer.h>
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#include <linux/seq_file.h>
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#include <plat/display.h>
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#define RFBI_BASE 0x48050800
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struct rfbi_reg { u16 idx; };
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#define RFBI_REG(idx) ((const struct rfbi_reg) { idx })
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#define RFBI_REVISION RFBI_REG(0x0000)
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#define RFBI_SYSCONFIG RFBI_REG(0x0010)
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#define RFBI_SYSSTATUS RFBI_REG(0x0014)
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#define RFBI_CONTROL RFBI_REG(0x0040)
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#define RFBI_PIXEL_CNT RFBI_REG(0x0044)
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#define RFBI_LINE_NUMBER RFBI_REG(0x0048)
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#define RFBI_CMD RFBI_REG(0x004c)
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#define RFBI_PARAM RFBI_REG(0x0050)
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#define RFBI_DATA RFBI_REG(0x0054)
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#define RFBI_READ RFBI_REG(0x0058)
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#define RFBI_STATUS RFBI_REG(0x005c)
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#define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18)
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#define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18)
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#define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18)
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#define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18)
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#define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18)
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#define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18)
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#define RFBI_VSYNC_WIDTH RFBI_REG(0x0090)
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#define RFBI_HSYNC_WIDTH RFBI_REG(0x0094)
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#define REG_FLD_MOD(idx, val, start, end) \
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rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
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/* To work around an RFBI transfer rate limitation */
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#define OMAP_RFBI_RATE_LIMIT 1
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enum omap_rfbi_cycleformat {
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OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
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OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
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OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2,
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OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3,
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enum omap_rfbi_datatype {
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OMAP_DSS_RFBI_DATATYPE_12 = 0,
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OMAP_DSS_RFBI_DATATYPE_16 = 1,
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OMAP_DSS_RFBI_DATATYPE_18 = 2,
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OMAP_DSS_RFBI_DATATYPE_24 = 3,
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enum omap_rfbi_parallelmode {
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OMAP_DSS_RFBI_PARALLELMODE_8 = 0,
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OMAP_DSS_RFBI_PARALLELMODE_9 = 1,
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OMAP_DSS_RFBI_PARALLELMODE_12 = 2,
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OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
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static int rfbi_convert_timings(struct rfbi_timings *t);
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static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
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unsigned long l4_khz;
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enum omap_rfbi_datatype datatype;
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enum omap_rfbi_parallelmode parallelmode;
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enum omap_rfbi_te_mode te_mode;
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void (*framedone_callback)(void *data);
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void *framedone_callback_data;
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struct omap_dss_device *dssdev[2];
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struct kfifo cmd_fifo;
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struct completion cmd_done;
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atomic_t cmd_fifo_full;
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atomic_t cmd_pending;
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struct update_region {
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static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
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__raw_writel(val, rfbi.base + idx.idx);
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static inline u32 rfbi_read_reg(const struct rfbi_reg idx)
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return __raw_readl(rfbi.base + idx.idx);
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static void rfbi_enable_clocks(bool enable)
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
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void omap_rfbi_write_command(const void *buf, u32 len)
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rfbi_enable_clocks(1);
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switch (rfbi.parallelmode) {
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case OMAP_DSS_RFBI_PARALLELMODE_8:
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rfbi_write_reg(RFBI_CMD, *b++);
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case OMAP_DSS_RFBI_PARALLELMODE_16:
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for (; len; len -= 2)
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rfbi_write_reg(RFBI_CMD, *w++);
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case OMAP_DSS_RFBI_PARALLELMODE_9:
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case OMAP_DSS_RFBI_PARALLELMODE_12:
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rfbi_enable_clocks(0);
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EXPORT_SYMBOL(omap_rfbi_write_command);
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void omap_rfbi_read_data(void *buf, u32 len)
182
rfbi_enable_clocks(1);
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switch (rfbi.parallelmode) {
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case OMAP_DSS_RFBI_PARALLELMODE_8:
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rfbi_write_reg(RFBI_READ, 0);
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*b++ = rfbi_read_reg(RFBI_READ);
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case OMAP_DSS_RFBI_PARALLELMODE_16:
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for (; len; len -= 2) {
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rfbi_write_reg(RFBI_READ, 0);
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*w++ = rfbi_read_reg(RFBI_READ);
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case OMAP_DSS_RFBI_PARALLELMODE_9:
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case OMAP_DSS_RFBI_PARALLELMODE_12:
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rfbi_enable_clocks(0);
212
EXPORT_SYMBOL(omap_rfbi_read_data);
214
void omap_rfbi_write_data(const void *buf, u32 len)
216
rfbi_enable_clocks(1);
217
switch (rfbi.parallelmode) {
218
case OMAP_DSS_RFBI_PARALLELMODE_8:
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rfbi_write_reg(RFBI_PARAM, *b++);
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case OMAP_DSS_RFBI_PARALLELMODE_16:
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for (; len; len -= 2)
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rfbi_write_reg(RFBI_PARAM, *w++);
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case OMAP_DSS_RFBI_PARALLELMODE_9:
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case OMAP_DSS_RFBI_PARALLELMODE_12:
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rfbi_enable_clocks(0);
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EXPORT_SYMBOL(omap_rfbi_write_data);
245
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
249
int start_offset = scr_width * y + x;
250
int horiz_offset = scr_width - w;
253
rfbi_enable_clocks(1);
255
if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
256
rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
257
const u16 __iomem *pd = buf;
261
for (i = 0; i < w; ++i) {
262
const u8 __iomem *b = (const u8 __iomem *)pd;
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rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
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rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
269
} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 &&
270
rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
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const u32 __iomem *pd = buf;
275
for (i = 0; i < w; ++i) {
276
const u8 __iomem *b = (const u8 __iomem *)pd;
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rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2));
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rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1));
279
rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0));
284
} else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
285
rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) {
286
const u16 __iomem *pd = buf;
290
for (i = 0; i < w; ++i) {
291
rfbi_write_reg(RFBI_PARAM, __raw_readw(pd));
300
rfbi_enable_clocks(0);
302
EXPORT_SYMBOL(omap_rfbi_write_pixels);
304
void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
305
u16 height, void (*callback)(void *data), void *data)
309
/*BUG_ON(callback == 0);*/
310
BUG_ON(rfbi.framedone_callback != NULL);
312
DSSDBG("rfbi_transfer_area %dx%d\n", width, height);
314
dispc_set_lcd_size(dssdev->manager->id, width, height);
316
dispc_enable_channel(dssdev->manager->id, true);
318
rfbi.framedone_callback = callback;
319
rfbi.framedone_callback_data = data;
321
rfbi_enable_clocks(1);
323
rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
325
l = rfbi_read_reg(RFBI_CONTROL);
326
l = FLD_MOD(l, 1, 0, 0); /* enable */
327
if (!rfbi.te_enabled)
328
l = FLD_MOD(l, 1, 4, 4); /* ITE */
330
rfbi_write_reg(RFBI_CONTROL, l);
333
static void framedone_callback(void *data, u32 mask)
335
void (*callback)(void *data);
337
DSSDBG("FRAMEDONE\n");
339
REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
341
rfbi_enable_clocks(0);
343
callback = rfbi.framedone_callback;
344
rfbi.framedone_callback = NULL;
346
if (callback != NULL)
347
callback(rfbi.framedone_callback_data);
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atomic_set(&rfbi.cmd_pending, 0);
353
static void rfbi_print_timings(void)
358
l = rfbi_read_reg(RFBI_CONFIG(0));
359
time = 1000000000 / rfbi.l4_khz;
363
DSSDBG("Tick time %u ps\n", time);
364
l = rfbi_read_reg(RFBI_ONOFF_TIME(0));
365
DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, "
366
"REONTIME %d, REOFFTIME %d\n",
367
l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f,
368
(l >> 20) & 0x0f, (l >> 24) & 0x3f);
370
l = rfbi_read_reg(RFBI_CYCLE_TIME(0));
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DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, "
373
(l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f,
377
static void rfbi_print_timings(void) {}
383
static u32 extif_clk_period;
385
static inline unsigned long round_to_extif_ticks(unsigned long ps, int div)
387
int bus_tick = extif_clk_period * div;
388
return (ps + bus_tick - 1) / bus_tick * bus_tick;
391
static int calc_reg_timing(struct rfbi_timings *t, int div)
395
t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div);
397
t->we_on_time = round_to_extif_ticks(t->we_on_time, div);
398
t->we_off_time = round_to_extif_ticks(t->we_off_time, div);
399
t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div);
401
t->re_on_time = round_to_extif_ticks(t->re_on_time, div);
402
t->re_off_time = round_to_extif_ticks(t->re_off_time, div);
403
t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div);
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t->access_time = round_to_extif_ticks(t->access_time, div);
406
t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div);
407
t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div);
409
DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n",
410
t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
411
DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n",
412
t->we_on_time, t->we_off_time, t->re_cycle_time,
414
DSSDBG("[reg]rdaccess %d cspulse %d\n",
415
t->access_time, t->cs_pulse_width);
417
return rfbi_convert_timings(t);
420
static int calc_extif_timings(struct rfbi_timings *t)
425
rfbi_get_clk_info(&extif_clk_period, &max_clk_div);
426
for (div = 1; div <= max_clk_div; div++) {
427
if (calc_reg_timing(t, div) == 0)
431
if (div <= max_clk_div)
434
DSSERR("can't setup timings\n");
439
void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
444
r = calc_extif_timings(t);
446
DSSERR("Failed to calc timings\n");
449
BUG_ON(!t->converted);
451
rfbi_enable_clocks(1);
452
rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
453
rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
455
/* TIMEGRANULARITY */
456
REG_FLD_MOD(RFBI_CONFIG(rfbi_module),
457
(t->tim[2] ? 1 : 0), 4, 4);
459
rfbi_print_timings();
460
rfbi_enable_clocks(0);
463
static int ps_to_rfbi_ticks(int time, int div)
465
unsigned long tick_ps;
468
/* Calculate in picosecs to yield more exact results */
469
tick_ps = 1000000000 / (rfbi.l4_khz) * div;
471
ret = (time + tick_ps - 1) / tick_ps;
476
#ifdef OMAP_RFBI_RATE_LIMIT
477
unsigned long rfbi_get_max_tx_rate(void)
479
unsigned long l4_rate, dss1_rate;
480
int min_l4_ticks = 0;
483
/* According to TI this can't be calculated so make the
484
* adjustments for a couple of known frequencies and warn for
487
static const struct {
488
unsigned long l4_clk; /* HZ */
489
unsigned long dss1_clk; /* HZ */
490
unsigned long min_l4_ticks;
492
{ 55, 132, 7, }, /* 7.86 MPix/s */
493
{ 110, 110, 12, }, /* 9.16 MPix/s */
494
{ 110, 132, 10, }, /* 11 Mpix/s */
495
{ 120, 120, 10, }, /* 12 Mpix/s */
496
{ 133, 133, 10, }, /* 13.3 Mpix/s */
499
l4_rate = rfbi.l4_khz / 1000;
500
dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000;
502
for (i = 0; i < ARRAY_SIZE(ftab); i++) {
503
/* Use a window instead of an exact match, to account
504
* for different DPLL multiplier / divider pairs.
506
if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
507
abs(ftab[i].dss1_clk - dss1_rate) < 3) {
508
min_l4_ticks = ftab[i].min_l4_ticks;
512
if (i == ARRAY_SIZE(ftab)) {
513
/* Can't be sure, return anyway the maximum not
514
* rate-limited. This might cause a problem only for the
515
* tearing synchronisation.
517
DSSERR("can't determine maximum RFBI transfer rate\n");
518
return rfbi.l4_khz * 1000;
520
return rfbi.l4_khz * 1000 / min_l4_ticks;
523
int rfbi_get_max_tx_rate(void)
525
return rfbi.l4_khz * 1000;
529
static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
531
*clk_period = 1000000000 / rfbi.l4_khz;
535
static int rfbi_convert_timings(struct rfbi_timings *t)
538
int reon, reoff, weon, weoff, cson, csoff, cs_pulse;
539
int actim, recyc, wecyc;
540
int div = t->clk_div;
542
if (div <= 0 || div > 2)
545
/* Make sure that after conversion it still holds that:
546
* weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff,
547
* csoff > cson, csoff >= max(weoff, reoff), actim > reon
549
weon = ps_to_rfbi_ticks(t->we_on_time, div);
550
weoff = ps_to_rfbi_ticks(t->we_off_time, div);
558
reon = ps_to_rfbi_ticks(t->re_on_time, div);
559
reoff = ps_to_rfbi_ticks(t->re_off_time, div);
567
cson = ps_to_rfbi_ticks(t->cs_on_time, div);
568
csoff = ps_to_rfbi_ticks(t->cs_off_time, div);
571
if (csoff < max(weoff, reoff))
572
csoff = max(weoff, reoff);
587
actim = ps_to_rfbi_ticks(t->access_time, div);
593
wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div);
599
recyc = ps_to_rfbi_ticks(t->re_cycle_time, div);
605
cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div);
623
/* xxx FIX module selection missing */
624
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
625
unsigned hs_pulse_time, unsigned vs_pulse_time,
626
int hs_pol_inv, int vs_pol_inv, int extif_div)
632
hs = ps_to_rfbi_ticks(hs_pulse_time, 1);
633
vs = ps_to_rfbi_ticks(vs_pulse_time, 1);
636
if (mode == OMAP_DSS_RFBI_TE_MODE_2)
638
else /* OMAP_DSS_RFBI_TE_MODE_1 */
645
DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
646
mode, hs, vs, hs_pol_inv, vs_pol_inv);
648
rfbi_enable_clocks(1);
649
rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
650
rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
652
l = rfbi_read_reg(RFBI_CONFIG(0));
661
rfbi_enable_clocks(0);
665
EXPORT_SYMBOL(omap_rfbi_setup_te);
667
/* xxx FIX module selection missing */
668
int omap_rfbi_enable_te(bool enable, unsigned line)
672
DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode);
673
if (line > (1 << 11) - 1)
676
rfbi_enable_clocks(1);
677
l = rfbi_read_reg(RFBI_CONFIG(0));
681
l |= rfbi.te_mode << 2;
684
rfbi_write_reg(RFBI_CONFIG(0), l);
685
rfbi_write_reg(RFBI_LINE_NUMBER, line);
686
rfbi_enable_clocks(0);
690
EXPORT_SYMBOL(omap_rfbi_enable_te);
693
static void rfbi_enable_config(int enable1, int enable2)
703
rfbi_enable_clocks(1);
705
l = rfbi_read_reg(RFBI_CONTROL);
707
l = FLD_MOD(l, cs, 3, 2);
708
l = FLD_MOD(l, 0, 1, 1);
710
rfbi_write_reg(RFBI_CONTROL, l);
713
l = rfbi_read_reg(RFBI_CONFIG(0));
714
l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
715
/*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
716
/*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
718
l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
719
l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
720
l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
722
l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
723
rfbi_write_reg(RFBI_CONFIG(0), l);
725
rfbi_enable_clocks(0);
729
int rfbi_configure(int rfbi_module, int bpp, int lines)
732
int cycle1 = 0, cycle2 = 0, cycle3 = 0;
733
enum omap_rfbi_cycleformat cycleformat;
734
enum omap_rfbi_datatype datatype;
735
enum omap_rfbi_parallelmode parallelmode;
739
datatype = OMAP_DSS_RFBI_DATATYPE_12;
742
datatype = OMAP_DSS_RFBI_DATATYPE_16;
745
datatype = OMAP_DSS_RFBI_DATATYPE_18;
748
datatype = OMAP_DSS_RFBI_DATATYPE_24;
754
rfbi.datatype = datatype;
758
parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8;
761
parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9;
764
parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12;
767
parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16;
773
rfbi.parallelmode = parallelmode;
775
if ((bpp % lines) == 0) {
776
switch (bpp / lines) {
778
cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1;
781
cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1;
784
cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1;
790
} else if ((2 * bpp % lines) == 0) {
791
if ((2 * bpp / lines) == 3)
792
cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2;
802
switch (cycleformat) {
803
case OMAP_DSS_RFBI_CYCLEFORMAT_1_1:
807
case OMAP_DSS_RFBI_CYCLEFORMAT_2_1:
812
case OMAP_DSS_RFBI_CYCLEFORMAT_3_1:
818
case OMAP_DSS_RFBI_CYCLEFORMAT_3_2:
820
cycle2 = (lines / 2) | ((lines / 2) << 16);
821
cycle3 = (lines << 16);
825
rfbi_enable_clocks(1);
827
REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
830
l |= FLD_VAL(parallelmode, 1, 0);
831
l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */
832
l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */
833
l |= FLD_VAL(datatype, 6, 5);
834
/* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
835
l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */
836
l |= FLD_VAL(cycleformat, 10, 9);
837
l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */
838
l |= FLD_VAL(0, 16, 16); /* A0POLARITY */
839
l |= FLD_VAL(0, 17, 17); /* REPOLARITY */
840
l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */
841
l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */
842
l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */
843
l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */
844
rfbi_write_reg(RFBI_CONFIG(rfbi_module), l);
846
rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1);
847
rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2);
848
rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3);
851
l = rfbi_read_reg(RFBI_CONTROL);
852
l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */
853
l = FLD_MOD(l, 0, 1, 1); /* clear bypass */
854
rfbi_write_reg(RFBI_CONTROL, l);
857
DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
858
bpp, lines, cycle1, cycle2, cycle3);
860
rfbi_enable_clocks(0);
864
EXPORT_SYMBOL(rfbi_configure);
866
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
867
u16 *x, u16 *y, u16 *w, u16 *h)
871
dssdev->driver->get_resolution(dssdev, &dw, &dh);
873
if (*x > dw || *y > dh)
885
if (*w == 0 || *h == 0)
888
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
889
dss_setup_partial_planes(dssdev, x, y, w, h, true);
890
dispc_set_lcd_size(dssdev->manager->id, *w, *h);
895
EXPORT_SYMBOL(omap_rfbi_prepare_update);
897
int omap_rfbi_update(struct omap_dss_device *dssdev,
898
u16 x, u16 y, u16 w, u16 h,
899
void (*callback)(void *), void *data)
901
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
902
rfbi_transfer_area(dssdev, w, h, callback, data);
904
struct omap_overlay *ovl;
908
ovl = dssdev->manager->overlays[0];
909
scr_width = ovl->info.screen_width;
910
addr = ovl->info.vaddr;
912
omap_rfbi_write_pixels(addr, scr_width, x, y, w, h);
919
EXPORT_SYMBOL(omap_rfbi_update);
921
void rfbi_dump_regs(struct seq_file *s)
923
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r))
925
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
927
DUMPREG(RFBI_REVISION);
928
DUMPREG(RFBI_SYSCONFIG);
929
DUMPREG(RFBI_SYSSTATUS);
930
DUMPREG(RFBI_CONTROL);
931
DUMPREG(RFBI_PIXEL_CNT);
932
DUMPREG(RFBI_LINE_NUMBER);
937
DUMPREG(RFBI_STATUS);
939
DUMPREG(RFBI_CONFIG(0));
940
DUMPREG(RFBI_ONOFF_TIME(0));
941
DUMPREG(RFBI_CYCLE_TIME(0));
942
DUMPREG(RFBI_DATA_CYCLE1(0));
943
DUMPREG(RFBI_DATA_CYCLE2(0));
944
DUMPREG(RFBI_DATA_CYCLE3(0));
946
DUMPREG(RFBI_CONFIG(1));
947
DUMPREG(RFBI_ONOFF_TIME(1));
948
DUMPREG(RFBI_CYCLE_TIME(1));
949
DUMPREG(RFBI_DATA_CYCLE1(1));
950
DUMPREG(RFBI_DATA_CYCLE2(1));
951
DUMPREG(RFBI_DATA_CYCLE3(1));
953
DUMPREG(RFBI_VSYNC_WIDTH);
954
DUMPREG(RFBI_HSYNC_WIDTH);
956
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
965
spin_lock_init(&rfbi.cmd_lock);
967
init_completion(&rfbi.cmd_done);
968
atomic_set(&rfbi.cmd_fifo_full, 0);
969
atomic_set(&rfbi.cmd_pending, 0);
971
rfbi.base = ioremap(RFBI_BASE, SZ_256);
973
DSSERR("can't ioremap RFBI\n");
977
rfbi_enable_clocks(1);
981
rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000;
983
/* Enable autoidle and smart-idle */
984
l = rfbi_read_reg(RFBI_SYSCONFIG);
985
l |= (1 << 0) | (2 << 3);
986
rfbi_write_reg(RFBI_SYSCONFIG, l);
988
rev = rfbi_read_reg(RFBI_REVISION);
989
printk(KERN_INFO "OMAP RFBI rev %d.%d\n",
990
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
992
rfbi_enable_clocks(0);
999
DSSDBG("rfbi_exit\n");
1004
int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev)
1008
r = omap_dss_start_device(dssdev);
1010
DSSERR("failed to start device\n");
1014
r = omap_dispc_register_isr(framedone_callback, NULL,
1015
DISPC_IRQ_FRAMEDONE);
1017
DSSERR("can't get FRAMEDONE irq\n");
1021
dispc_set_lcd_display_type(dssdev->manager->id,
1022
OMAP_DSS_LCD_DISPLAY_TFT);
1024
dispc_set_parallel_interface_mode(dssdev->manager->id,
1025
OMAP_DSS_PARALLELMODE_RFBI);
1027
dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
1029
rfbi_configure(dssdev->phy.rfbi.channel,
1030
dssdev->ctrl.pixel_size,
1031
dssdev->phy.rfbi.data_lines);
1033
rfbi_set_timings(dssdev->phy.rfbi.channel,
1034
&dssdev->ctrl.rfbi_timings);
1039
omap_dss_stop_device(dssdev);
1043
EXPORT_SYMBOL(omapdss_rfbi_display_enable);
1045
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
1047
omap_dispc_unregister_isr(framedone_callback, NULL,
1048
DISPC_IRQ_FRAMEDONE);
1049
omap_dss_stop_device(dssdev);
1051
EXPORT_SYMBOL(omapdss_rfbi_display_disable);
1053
int rfbi_init_display(struct omap_dss_device *dssdev)
1055
rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
1056
dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;