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*************************************************************************
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* 5F., No.36, Taiyuan St., Jhubei City,
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* (c) Copyright 2002-2007, Ralink Technology, Inc.
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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*************************************************************************
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Ralink Wireless Chip related definition & structures
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-------- ---------- ----------------------------------------------
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#ifndef __RTMP_CHIP_H__
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#define __RTMP_CHIP_H__
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#include "rtmp_type.h"
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// We will have a cost down version which mac version is 0x3090xxxx
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// b) Replacement for RT3090
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// d) Interference over channel #14
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// e) New BBP features (e.g., SIG re-modulation)
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#define IS_RT3090A(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
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// We will have a cost down version which mac version is 0x3090xxxx
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#define IS_RT3090(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))
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#define IS_RT3070(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
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#define IS_RT3071(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
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#define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))
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#define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
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//#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200)
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/* RT3572, 3592, 3562, 3062 share the same MAC version */
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#define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
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#define IS_VERSION_BEFORE_F(_pAd) (((_pAd)->MACVersion&0xffff) <= 0x0211)
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// F version is 0x0212, E version is 0x0211. 309x can save more power after F version.
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#define IS_VERSION_AFTER_F(_pAd) ((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
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// a) Base on RT3090 (RF IC: RT3020)
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// e) Internal components: PA and LNA
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#define IS_RT3390(_pAd) (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
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// ------------------------------------------------------
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// PCI registers - base address 0x0000
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// ------------------------------------------------------
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#define CHIP_PCI_CFG 0x0000
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#define CHIP_PCI_EECTRL 0x0004
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#define CHIP_PCI_MCUCTRL 0x0008
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#define RETRY_LIMIT 10
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// ------------------------------------------------------
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// BBP & RF definition
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// ------------------------------------------------------
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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#define EEPROM_WRITE_OPCODE 0x05
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#define EEPROM_READ_OPCODE 0x06
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#define EEPROM_EWDS_OPCODE 0x10
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#define EEPROM_EWEN_OPCODE 0x13
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#define NUM_EEPROM_BBP_PARMS 19 // Include NIC Config 0, 1, CR, TX ALC step, BBPs
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#define NUM_EEPROM_TX_G_PARMS 7
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#define EEPROM_NIC1_OFFSET 0x34 // The address is from NIC config 0, not BBP register ID
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#define EEPROM_NIC2_OFFSET 0x36 // The address is from NIC config 0, not BBP register ID
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#define EEPROM_BBP_BASE_OFFSET 0xf0 // The address is from NIC config 0, not BBP register ID
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#define EEPROM_G_TX_PWR_OFFSET 0x52
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#define EEPROM_G_TX2_PWR_OFFSET 0x60
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#define EEPROM_LED1_OFFSET 0x3c
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#define EEPROM_LED2_OFFSET 0x3e
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#define EEPROM_LED3_OFFSET 0x40
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#define EEPROM_LNA_OFFSET 0x44
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#define EEPROM_RSSI_BG_OFFSET 0x46
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#define EEPROM_TXMIXER_GAIN_2_4G 0x48
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#define EEPROM_RSSI_A_OFFSET 0x4a
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#define EEPROM_TXMIXER_GAIN_5G 0x4c
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#define EEPROM_DEFINE_MAX_TXPWR 0x4e
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#define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde // 20MHZ 2.4G tx power.
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#define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee // 40MHZ 2.4G tx power.
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#define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa // 20MHZ 5G tx power.
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#define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a // 40MHZ 5G tx power.
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#define EEPROM_A_TX_PWR_OFFSET 0x78
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#define EEPROM_A_TX2_PWR_OFFSET 0xa6
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//#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j
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//#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe
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//#define EEPROM_TSSI_REF_OFFSET 0x54
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//#define EEPROM_TSSI_DELTA_OFFSET 0x24
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//#define EEPROM_CCK_TX_PWR_OFFSET 0x62
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//#define EEPROM_CALIBRATE_OFFSET 0x7c
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#define EEPROM_VERSION_OFFSET 0x02
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#define EEPROM_FREQ_OFFSET 0x3a
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#define EEPROM_TXPOWER_BYRATE 0xde // 20MHZ power.
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#define EEPROM_TXPOWER_DELTA 0x50 // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
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#define VALID_EEPROM_VERSION 1
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* EEPROM operation related marcos
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#define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \
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(_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value))
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#define RT28xx_EEPROM_WRITE16(_pAd, _offset, _value) \
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(_pAd)->chipOps.eewrite((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (USHORT)(_value))
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// -------------------------------------------------------------------
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// E2PROM data layout
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// -------------------------------------------------------------------
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// MCU_LEDCS: MCU LED Control Setting.
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typedef union _MCU_LEDCS_STRUC {
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#endif // RT_BIG_ENDIAN //
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} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
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// EEPROM antenna select format
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typedef union _EEPROM_ANTENNA_STRUC {
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USHORT RfIcType:4; // see E2PROM document
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USHORT TxPath:4; // 1: 1T, 2: 2T
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USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
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} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
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typedef union _EEPROM_ANTENNA_STRUC {
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USHORT RxPath:4; // 1: 1R, 2: 2R, 3: 3R
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USHORT TxPath:4; // 1: 1T, 2: 2T
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USHORT RfIcType:4; // see E2PROM document
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} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
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typedef union _EEPROM_NIC_CINFIG2_STRUC {
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USHORT DACTestBit:1; // control if driver should patch the DAC issue
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USHORT Rsv2:3; // must be 0
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USHORT AntDiversity:1; // Antenna diversity
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USHORT Rsv1:1; // must be 0
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USHORT BW40MAvailForA:1; // 0:enable, 1:disable
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USHORT BW40MAvailForG:1; // 0:enable, 1:disable
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USHORT EnableWPSPBC:1; // WPS PBC Control bit
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USHORT BW40MSidebandForA:1;
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USHORT BW40MSidebandForG:1;
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USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
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USHORT ExternalLNAForA:1; // external LNA enable for 5G
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USHORT ExternalLNAForG:1; // external LNA enable for 2.4G
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USHORT DynamicTxAgcControl:1; //
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USHORT HardwareRadioControl:1; // Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable
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} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
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typedef union _EEPROM_NIC_CINFIG2_STRUC {
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USHORT HardwareRadioControl:1; // 1:enable, 0:disable
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USHORT DynamicTxAgcControl:1; //
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USHORT ExternalLNAForG:1; //
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USHORT ExternalLNAForA:1; // external LNA enable for 2.4G
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USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable
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USHORT BW40MSidebandForG:1;
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USHORT BW40MSidebandForA:1;
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USHORT EnableWPSPBC:1; // WPS PBC Control bit
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USHORT BW40MAvailForG:1; // 0:enable, 1:disable
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USHORT BW40MAvailForA:1; // 0:enable, 1:disable
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USHORT Rsv1:1; // must be 0
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USHORT AntDiversity:1; // Antenna diversity
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USHORT Rsv2:3; // must be 0
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USHORT DACTestBit:1; // control if driver should patch the DAC issue
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} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
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// TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
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typedef union _EEPROM_TX_PWR_STRUC {
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CHAR Byte1; // High Byte
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CHAR Byte0; // Low Byte
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} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
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typedef union _EEPROM_TX_PWR_STRUC {
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CHAR Byte0; // Low Byte
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CHAR Byte1; // High Byte
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} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
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typedef union _EEPROM_VERSION_STRUC {
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UCHAR Version; // High Byte
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UCHAR FaeReleaseNumber; // Low Byte
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} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
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typedef union _EEPROM_VERSION_STRUC {
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UCHAR FaeReleaseNumber; // Low Byte
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UCHAR Version; // High Byte
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} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
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typedef union _EEPROM_LED_STRUC {
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USHORT Rsvd:3; // Reserved
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USHORT LedMode:5; // Led mode.
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USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
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USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
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USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
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USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
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USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
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USHORT PolarityACT:1; // Polarity ACT setting.
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USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
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USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
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} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
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typedef union _EEPROM_LED_STRUC {
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USHORT PolarityRDY_G:1; // Polarity RDY_G setting.
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USHORT PolarityRDY_A:1; // Polarity RDY_A setting.
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USHORT PolarityACT:1; // Polarity ACT setting.
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USHORT PolarityGPIO_0:1; // Polarity GPIO#0 setting.
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USHORT PolarityGPIO_1:1; // Polarity GPIO#1 setting.
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USHORT PolarityGPIO_2:1; // Polarity GPIO#2 setting.
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USHORT PolarityGPIO_3:1; // Polarity GPIO#3 setting.
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USHORT PolarityGPIO_4:1; // Polarity GPIO#4 setting.
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USHORT LedMode:5; // Led mode.
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USHORT Rsvd:3; // Reserved
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} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
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typedef union _EEPROM_TXPOWER_DELTA_STRUC {
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UCHAR TxPowerEnable:1;// Enable
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UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
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UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
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} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
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typedef union _EEPROM_TXPOWER_DELTA_STRUC {
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UCHAR DeltaValue:6; // Tx Power dalta value (MAX=4)
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UCHAR Type:1; // 1: plus the delta value, 0: minus the delta value
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UCHAR TxPowerEnable:1;// Enable
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} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
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#endif // __RTMP_CHIP_H__ //