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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/completion.h>
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#include <asm/mach/flash.h>
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#include <mach/mxc_nand.h>
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#include <mach/hardware.h>
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#define DRIVER_NAME "mxc_nand"
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#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
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#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
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#define nfc_is_v3_2() cpu_is_mx51()
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#define nfc_is_v3() nfc_is_v3_2()
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/* Addresses for NFC registers */
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#define NFC_BUF_SIZE 0xE00
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#define NFC_BUF_ADDR 0xE04
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#define NFC_FLASH_ADDR 0xE06
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#define NFC_FLASH_CMD 0xE08
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#define NFC_CONFIG 0xE0A
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#define NFC_ECC_STATUS_RESULT 0xE0C
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#define NFC_RSLTMAIN_AREA 0xE0E
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#define NFC_RSLTSPARE_AREA 0xE10
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#define NFC_WRPROT 0xE12
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#define NFC_UNLOCKSTART_BLKADDR 0xE14
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#define NFC_UNLOCKEND_BLKADDR 0xE16
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#define NFC_NF_WRPRST 0xE18
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#define NFC_CONFIG1 0xE1A
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#define NFC_CONFIG2 0xE1C
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/* Addresses for NFC RAM BUFFER Main area 0 */
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#define MAIN_AREA0 0x000
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#define MAIN_AREA1 0x200
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#define MAIN_AREA2 0x400
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#define MAIN_AREA3 0x600
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/* Addresses for NFC SPARE BUFFER Spare area 0 */
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#define SPARE_AREA0 0x800
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#define SPARE_AREA1 0x810
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#define SPARE_AREA2 0x820
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#define SPARE_AREA3 0x830
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/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
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* for Command operation */
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/* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
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* for Address operation */
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/* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
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* for Input operation */
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/* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
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* for Data Output operation */
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#define NFC_OUTPUT 0x8
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/* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
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* for Read ID operation */
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/* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
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* for Read Status operation */
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#define NFC_STATUS 0x20
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/* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
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#define NFC_INT 0x8000
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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#define NFC_BIG (1 << 5)
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#define NFC_RST (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
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#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
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#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
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#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
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#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
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#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
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#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
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#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
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#define NFC_V1_V2_WRPROT (host->regs + 0x12)
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#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
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#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
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#define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
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#define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
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#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
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#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
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#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
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#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
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#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
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#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
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#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
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#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
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#define NFC_V1_V2_CONFIG1_RST (1 << 6)
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#define NFC_V1_V2_CONFIG1_CE (1 << 7)
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#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
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#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
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#define NFC_V2_CONFIG1_FP_INT (1 << 11)
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#define NFC_V1_V2_CONFIG2_INT (1 << 15)
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* Operation modes for the NFC. Valid for v1, v2 and v3
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#define NFC_CMD (1 << 0)
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#define NFC_ADDR (1 << 1)
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#define NFC_INPUT (1 << 2)
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#define NFC_OUTPUT (1 << 3)
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#define NFC_ID (1 << 4)
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#define NFC_STATUS (1 << 5)
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#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
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#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
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#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
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#define NFC_V3_CONFIG1_SP_EN (1 << 0)
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#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
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#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
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#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
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#define NFC_V3_WRPROT (host->regs_ip + 0x0)
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#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
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#define NFC_V3_WRPROT_LOCK (1 << 1)
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#define NFC_V3_WRPROT_UNLOCK (1 << 2)
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#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
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#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
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#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
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#define NFC_V3_CONFIG2_PS_512 (0 << 0)
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#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
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#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
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#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
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#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
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#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
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#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
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#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
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#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
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#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
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#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
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#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
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#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
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#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
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#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
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#define NFC_V3_CONFIG3_FW8 (1 << 3)
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#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
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#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
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#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
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#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
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#define NFC_V3_IPC (host->regs_ip + 0x2C)
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#define NFC_V3_IPC_CREQ (1 << 0)
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#define NFC_V3_IPC_INT (1 << 31)
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#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
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struct mxc_nand_host {
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struct mtd_info mtd;
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struct mtd_partition *parts;
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struct device *dev;
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void __iomem *regs;
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void __iomem *regs_axi;
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void __iomem *regs_ip;
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int status_request;
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wait_queue_head_t irq_waitq;
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struct completion op_completion;
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unsigned int buf_start;
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void (*preset)(struct mtd_info *);
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void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
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void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
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void (*send_page)(struct mtd_info *, unsigned int);
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void (*send_read_id)(struct mxc_nand_host *);
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uint16_t (*get_dev_status)(struct mxc_nand_host *);
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int (*check_int)(struct mxc_nand_host *);
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void (*irq_control)(struct mxc_nand_host *, int);
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/* Define delays in microsec for NAND device operations */
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#define TROP_US_DELAY 2000
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/* Macros to get byte and bit positions of ECC */
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#define COLPOS(x) ((x) >> 3)
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#define BITPOS(x) ((x) & 0xf)
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/* Define single bit Error positions in Main & Spare area */
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#define MAIN_SINGLEBIT_ERROR 0x4
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#define SPARE_SINGLEBIT_ERROR 0x1
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/* OOB placement block for use with hardware ecc generation */
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static struct nand_ecclayout nand_hw_eccoob_8 = {
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.eccpos = {6, 7, 8, 9, 10},
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.oobfree = {{0, 5}, {11, 5}, }
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static struct nand_ecclayout nand_hw_eccoob_16 = {
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.eccpos = {6, 7, 8, 9, 10},
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.oobfree = {{0, 5}, {11, 5}, }
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static struct nand_ecclayout nand_hw_eccoob_64 = {
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static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
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.eccpos = {6, 7, 8, 9, 10},
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.oobfree = {{0, 5}, {12, 4}, }
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static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
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.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
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38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
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.oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
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/* OOB description for 512 byte pages with 16 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
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7, 8, 9, 10, 11, 12, 13, 14, 15
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{.offset = 0, .length = 5}
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/* OOB description for 2048 byte pages with 64 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
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7, 8, 9, 10, 11, 12, 13, 14, 15,
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23, 24, 25, 26, 27, 28, 29, 30, 31,
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39, 40, 41, 42, 43, 44, 45, 46, 47,
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55, 56, 57, 58, 59, 60, 61, 62, 63
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{.offset = 2, .length = 4},
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{.offset = 16, .length = 7},
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{.offset = 32, .length = 7},
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{.offset = 48, .length = 7}
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#ifdef CONFIG_MTD_PARTITIONS
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static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
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struct mxc_nand_host *host = dev_id;
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tmp = readw(host->regs + NFC_CONFIG1);
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tmp |= NFC_INT_MSK; /* Disable interrupt */
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writew(tmp, host->regs + NFC_CONFIG1);
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wake_up(&host->irq_waitq);
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if (!host->check_int(host))
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host->irq_control(host, 0);
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complete(&host->op_completion);
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return IRQ_HANDLED;
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static int check_int_v3(struct mxc_nand_host *host)
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tmp = readl(NFC_V3_IPC);
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if (!(tmp & NFC_V3_IPC_INT))
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tmp &= ~NFC_V3_IPC_INT;
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writel(tmp, NFC_V3_IPC);
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static int check_int_v1_v2(struct mxc_nand_host *host)
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tmp = readw(NFC_V1_V2_CONFIG2);
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if (!(tmp & NFC_V1_V2_CONFIG2_INT))
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writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
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* It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
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* if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
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* driver can enable/disable the irq line rather than simply masking the
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static void irq_control_mx21(struct mxc_nand_host *host, int activate)
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enable_irq(host->irq);
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disable_irq_nosync(host->irq);
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static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
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tmp = readw(NFC_V1_V2_CONFIG1);
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tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
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tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
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writew(tmp, NFC_V1_V2_CONFIG1);
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static void irq_control_v3(struct mxc_nand_host *host, int activate)
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tmp = readl(NFC_V3_CONFIG2);
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tmp &= ~NFC_V3_CONFIG2_INT_MSK;
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tmp |= NFC_V3_CONFIG2_INT_MSK;
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writel(tmp, NFC_V3_CONFIG2);
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/* This function polls the NANDFC to wait for the basic operation to
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* complete by checking the INT bit of config2 register.
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static void wait_op_done(struct mxc_nand_host *host, int max_retries,
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uint16_t param, int useirq)
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static void wait_op_done(struct mxc_nand_host *host, int useirq)
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int max_retries = 8000;
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if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
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tmp = readw(host->regs + NFC_CONFIG1);
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tmp &= ~NFC_INT_MSK; /* Enable interrupt */
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writew(tmp, host->regs + NFC_CONFIG1);
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wait_event(host->irq_waitq,
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readw(host->regs + NFC_CONFIG2) & NFC_INT);
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tmp = readw(host->regs + NFC_CONFIG2);
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writew(tmp, host->regs + NFC_CONFIG2);
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if (!host->check_int(host)) {
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INIT_COMPLETION(host->op_completion);
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host->irq_control(host, 1);
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wait_for_completion(&host->op_completion);
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while (max_retries-- > 0) {
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if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
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tmp = readw(host->regs + NFC_CONFIG2);
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writew(tmp, host->regs + NFC_CONFIG2);
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if (host->check_int(host))
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if (max_retries < 0)
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DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
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DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
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static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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writel(cmd, NFC_V3_FLASH_CMD);
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/* send out command */
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writel(NFC_CMD, NFC_V3_LAUNCH);
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/* Wait for operation to complete */
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wait_op_done(host, useirq);
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/* This function issues the specified command to the NAND device and
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* waits for completion. */
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static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
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writew(cmd, host->regs + NFC_FLASH_CMD);
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writew(NFC_CMD, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, cmd, useirq);
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writew(cmd, NFC_V1_V2_FLASH_CMD);
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writew(NFC_CMD, NFC_V1_V2_CONFIG2);
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if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
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int max_retries = 100;
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/* Reset completion is indicated by NFC_CONFIG2 */
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while (max_retries-- > 0) {
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if (readw(NFC_V1_V2_CONFIG2) == 0) {
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DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
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/* Wait for operation to complete */
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wait_op_done(host, useirq);
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static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
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writel(addr, NFC_V3_FLASH_ADDR0);
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/* send out address */
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writel(NFC_ADDR, NFC_V3_LAUNCH);
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wait_op_done(host, 0);
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/* This function sends an address (or partial address) to the
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* NAND device. The address is used to select the source/destination for
223
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* a NAND command. */
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static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
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static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
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DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
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writew(addr, host->regs + NFC_FLASH_ADDR);
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writew(NFC_ADDR, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, addr, islast);
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/* This function requests the NANDFC to initate the transfer
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* of data currently in the NANDFC RAM buffer to the NAND device. */
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static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
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DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
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/* NANDFC buffer 0 is used for page read/write */
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writew(buf_id, host->regs + NFC_BUF_ADDR);
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/* Configure spare or page+spare access */
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if (!host->pagesize_2k) {
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uint16_t config1 = readw(host->regs + NFC_CONFIG1);
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config1 |= NFC_SP_EN;
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config1 &= ~(NFC_SP_EN);
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writew(config1, host->regs + NFC_CONFIG1);
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writew(NFC_INPUT, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host, TROP_US_DELAY, spare_only, true);
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/* Requests NANDFC to initated the transfer of data from the
262
* NAND device into in the NANDFC ram buffer. */
263
static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
266
DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
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/* NANDFC buffer 0 is used for page read/write */
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writew(buf_id, host->regs + NFC_BUF_ADDR);
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/* Configure spare or page+spare access */
272
if (!host->pagesize_2k) {
273
uint32_t config1 = readw(host->regs + NFC_CONFIG1);
275
config1 |= NFC_SP_EN;
277
config1 &= ~NFC_SP_EN;
278
writew(config1, host->regs + NFC_CONFIG1);
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writew(NFC_OUTPUT, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
284
wait_op_done(host, TROP_US_DELAY, spare_only, true);
386
writew(addr, NFC_V1_V2_FLASH_ADDR);
387
writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
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/* Wait for operation to complete */
390
wait_op_done(host, islast);
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static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
395
struct nand_chip *nand_chip = mtd->priv;
396
struct mxc_nand_host *host = nand_chip->priv;
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tmp = readl(NFC_V3_CONFIG1);
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writel(tmp, NFC_V3_CONFIG1);
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/* transfer data from NFC ram to nand */
404
writel(ops, NFC_V3_LAUNCH);
406
wait_op_done(host, false);
409
static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
411
struct nand_chip *nand_chip = mtd->priv;
412
struct mxc_nand_host *host = nand_chip->priv;
415
if (nfc_is_v1() && mtd->writesize > 512)
420
for (i = 0; i < bufs; i++) {
422
/* NANDFC buffer 0 is used for page read/write */
423
writew(i, NFC_V1_V2_BUF_ADDR);
425
writew(ops, NFC_V1_V2_CONFIG2);
427
/* Wait for operation to complete */
428
wait_op_done(host, true);
432
static void send_read_id_v3(struct mxc_nand_host *host)
434
/* Read ID into main buffer */
435
writel(NFC_ID, NFC_V3_LAUNCH);
437
wait_op_done(host, true);
439
memcpy(host->data_buf, host->main_area0, 16);
287
442
/* Request the NANDFC to perform a read of the NAND device ID. */
288
static void send_read_id(struct mxc_nand_host *host)
443
static void send_read_id_v1_v2(struct mxc_nand_host *host)
290
445
struct nand_chip *this = &host->nand;
293
447
/* NANDFC buffer 0 is used for device ID output */
294
writew(0x0, host->regs + NFC_BUF_ADDR);
296
/* Read ID into main buffer */
297
tmp = readw(host->regs + NFC_CONFIG1);
299
writew(tmp, host->regs + NFC_CONFIG1);
301
writew(NFC_ID, host->regs + NFC_CONFIG2);
448
writew(0x0, NFC_V1_V2_BUF_ADDR);
450
writew(NFC_ID, NFC_V1_V2_CONFIG2);
303
452
/* Wait for operation to complete */
304
wait_op_done(host, TROP_US_DELAY, 0, true);
453
wait_op_done(host, true);
455
memcpy(host->data_buf, host->main_area0, 16);
306
457
if (this->options & NAND_BUSWIDTH_16) {
307
void __iomem *main_buf = host->regs + MAIN_AREA0;
308
458
/* compress the ID info */
309
writeb(readb(main_buf + 2), main_buf + 1);
310
writeb(readb(main_buf + 4), main_buf + 2);
311
writeb(readb(main_buf + 6), main_buf + 3);
312
writeb(readb(main_buf + 8), main_buf + 4);
313
writeb(readb(main_buf + 10), main_buf + 5);
459
host->data_buf[1] = host->data_buf[2];
460
host->data_buf[2] = host->data_buf[4];
461
host->data_buf[3] = host->data_buf[6];
462
host->data_buf[4] = host->data_buf[8];
463
host->data_buf[5] = host->data_buf[10];
467
static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
469
writew(NFC_STATUS, NFC_V3_LAUNCH);
470
wait_op_done(host, true);
472
return readl(NFC_V3_CONFIG1) >> 16;
317
475
/* This function requests the NANDFC to perform a read of the
318
476
* NAND device status and returns the current status. */
319
static uint16_t get_dev_status(struct mxc_nand_host *host)
477
static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
321
void __iomem *main_buf = host->regs + MAIN_AREA1;
479
void __iomem *main_buf = host->main_area0;
324
/* Issue status request to NAND device */
326
/* store the main area1 first word, later do recovery */
483
writew(0x0, NFC_V1_V2_BUF_ADDR);
486
* The device status is stored in main_area0. To
487
* prevent corruption of the buffer save the value
488
* and restore it afterwards.
327
490
store = readl(main_buf);
328
/* NANDFC buffer 1 is used for device status to prevent
329
* corruption of read/write buffer on status requests. */
330
writew(1, host->regs + NFC_BUF_ADDR);
332
/* Read status into main buffer */
333
tmp = readw(host->regs + NFC_CONFIG1);
335
writew(tmp, host->regs + NFC_CONFIG1);
337
writew(NFC_STATUS, host->regs + NFC_CONFIG2);
339
/* Wait for operation to complete */
340
wait_op_done(host, TROP_US_DELAY, 0, true);
342
/* Status is placed in first word of main buffer */
343
/* get status, then recovery area 1 data */
492
writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
493
wait_op_done(host, true);
344
495
ret = readw(main_buf);
345
497
writel(store, main_buf);
695
/* Used by the upper layer to write command to NAND Flash for
696
* different operations to be carried out on NAND Flash */
697
static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
698
int column, int page_addr)
686
* Function to transfer data to/from spare area.
688
static void copy_spare(struct mtd_info *mtd, bool bfrom)
690
struct nand_chip *this = mtd->priv;
691
struct mxc_nand_host *host = this->priv;
693
u16 n = mtd->writesize >> 9;
694
u8 *d = host->data_buf + mtd->writesize;
695
u8 *s = host->spare0;
696
u16 t = host->spare_len;
698
j = (mtd->oobsize / n >> 1) << 1;
701
for (i = 0; i < n - 1; i++)
702
memcpy(d + i * j, s + i * t, j);
704
/* the last section */
705
memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
707
for (i = 0; i < n - 1; i++)
708
memcpy(&s[i * t], &d[i * j], j);
710
/* the last section */
711
memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
715
static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
700
717
struct nand_chip *nand_chip = mtd->priv;
701
718
struct mxc_nand_host *host = nand_chip->priv;
704
DEBUG(MTD_DEBUG_LEVEL3,
705
"mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
706
command, column, page_addr);
708
/* Reset command state information */
709
host->status_request = false;
711
/* Command pre-processing step */
714
case NAND_CMD_STATUS:
716
host->status_request = true;
720
host->col_addr = column;
721
host->spare_only = false;
725
case NAND_CMD_READOOB:
726
host->col_addr = column;
727
host->spare_only = true;
729
if (host->pagesize_2k)
730
command = NAND_CMD_READ0; /* only READ0 is valid */
734
if (column >= mtd->writesize) {
736
* FIXME: before send SEQIN command for write OOB,
737
* We must read one page out.
738
* For K9F1GXX has no READ1 command to set current HW
739
* pointer to spare area, we must write the whole page
740
* including OOB together.
742
if (host->pagesize_2k)
743
/* call ourself to read a page */
744
mxc_nand_command(mtd, NAND_CMD_READ0, 0,
747
host->col_addr = column - mtd->writesize;
748
host->spare_only = true;
750
/* Set program pointer to spare region */
751
if (!host->pagesize_2k)
752
send_cmd(host, NAND_CMD_READOOB, false);
754
host->spare_only = false;
755
host->col_addr = column;
757
/* Set program pointer to page start */
758
if (!host->pagesize_2k)
759
send_cmd(host, NAND_CMD_READ0, false);
764
case NAND_CMD_PAGEPROG:
765
send_prog_page(host, 0, host->spare_only);
767
if (host->pagesize_2k) {
768
/* data in 4 areas datas */
769
send_prog_page(host, 1, host->spare_only);
770
send_prog_page(host, 2, host->spare_only);
771
send_prog_page(host, 3, host->spare_only);
776
case NAND_CMD_ERASE1:
781
/* Write out the command to the device. */
782
send_cmd(host, command, useirq);
784
720
/* Write out column address, if necessary */
785
721
if (column != -1) {
787
723
* MXC NANDFC can only perform full page+spare or
788
724
* spare-only read/write. When the upper layers
789
725
* layers perform a read/write buf operation,
790
* we will used the saved column adress to index into
726
* we will used the saved column address to index into
793
send_addr(host, 0, page_addr == -1);
794
if (host->pagesize_2k)
729
host->send_addr(host, 0, page_addr == -1);
730
if (mtd->writesize > 512)
795
731
/* another col addr cycle for 2k page */
796
send_addr(host, 0, false);
732
host->send_addr(host, 0, false);
799
735
/* Write out page address, if necessary */
800
736
if (page_addr != -1) {
801
737
/* paddr_0 - p_addr_7 */
802
send_addr(host, (page_addr & 0xff), false);
738
host->send_addr(host, (page_addr & 0xff), false);
804
if (host->pagesize_2k) {
740
if (mtd->writesize > 512) {
805
741
if (mtd->size >= 0x10000000) {
806
742
/* paddr_8 - paddr_15 */
807
send_addr(host, (page_addr >> 8) & 0xff, false);
808
send_addr(host, (page_addr >> 16) & 0xff, true);
743
host->send_addr(host, (page_addr >> 8) & 0xff, false);
744
host->send_addr(host, (page_addr >> 16) & 0xff, true);
810
746
/* paddr_8 - paddr_15 */
811
send_addr(host, (page_addr >> 8) & 0xff, true);
747
host->send_addr(host, (page_addr >> 8) & 0xff, true);
813
749
/* One more address cycle for higher density devices */
814
750
if (mtd->size >= 0x4000000) {
815
751
/* paddr_8 - paddr_15 */
816
send_addr(host, (page_addr >> 8) & 0xff, false);
817
send_addr(host, (page_addr >> 16) & 0xff, true);
752
host->send_addr(host, (page_addr >> 8) & 0xff, false);
753
host->send_addr(host, (page_addr >> 16) & 0xff, true);
819
755
/* paddr_8 - paddr_15 */
820
send_addr(host, (page_addr >> 8) & 0xff, true);
756
host->send_addr(host, (page_addr >> 8) & 0xff, true);
824
/* Command post-processing step */
762
* v2 and v3 type controllers can do 4bit or 8bit ecc depending
763
* on how much oob the nand chip has. For 8bit ecc we need at least
764
* 26 bytes of oob data per 512 byte block.
766
static int get_eccsize(struct mtd_info *mtd)
768
int oobbytes_per_512 = 0;
770
oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
772
if (oobbytes_per_512 < 26)
778
static void preset_v1_v2(struct mtd_info *mtd)
780
struct nand_chip *nand_chip = mtd->priv;
781
struct mxc_nand_host *host = nand_chip->priv;
782
uint16_t config1 = 0;
784
if (nand_chip->ecc.mode == NAND_ECC_HW)
785
config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
788
config1 |= NFC_V2_CONFIG1_FP_INT;
791
config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
793
if (nfc_is_v21() && mtd->writesize) {
794
uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
796
host->eccsize = get_eccsize(mtd);
797
if (host->eccsize == 4)
798
config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
800
config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
805
writew(config1, NFC_V1_V2_CONFIG1);
806
/* preset operation */
808
/* Unlock the internal RAM Buffer */
809
writew(0x2, NFC_V1_V2_CONFIG);
811
/* Blocks to be unlocked */
813
writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
814
writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
815
} else if (nfc_is_v1()) {
816
writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
817
writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
821
/* Unlock Block Command for given address range */
822
writew(0x4, NFC_V1_V2_WRPROT);
825
static void preset_v3(struct mtd_info *mtd)
827
struct nand_chip *chip = mtd->priv;
828
struct mxc_nand_host *host = chip->priv;
829
uint32_t config2, config3;
832
writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
833
writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
835
/* Unlock the internal RAM Buffer */
836
writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
839
/* Blocks to be unlocked */
840
for (i = 0; i < NAND_MAX_CHIPS; i++)
841
writel(0x0 | (0xffff << 16),
842
NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
844
writel(0, NFC_V3_IPC);
846
config2 = NFC_V3_CONFIG2_ONE_CYCLE |
847
NFC_V3_CONFIG2_2CMD_PHASES |
848
NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
849
NFC_V3_CONFIG2_ST_CMD(0x70) |
850
NFC_V3_CONFIG2_INT_MSK |
851
NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
853
if (chip->ecc.mode == NAND_ECC_HW)
854
config2 |= NFC_V3_CONFIG2_ECC_EN;
856
addr_phases = fls(chip->pagemask) >> 3;
858
if (mtd->writesize == 2048) {
859
config2 |= NFC_V3_CONFIG2_PS_2048;
860
config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
861
} else if (mtd->writesize == 4096) {
862
config2 |= NFC_V3_CONFIG2_PS_4096;
863
config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
865
config2 |= NFC_V3_CONFIG2_PS_512;
866
config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
869
if (mtd->writesize) {
870
config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
871
host->eccsize = get_eccsize(mtd);
872
if (host->eccsize == 8)
873
config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
876
writel(config2, NFC_V3_CONFIG2);
878
config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
879
NFC_V3_CONFIG3_NO_SDMA |
880
NFC_V3_CONFIG3_RBB_MODE |
881
NFC_V3_CONFIG3_SBB(6) | /* Reset default */
882
NFC_V3_CONFIG3_ADD_OP(0);
884
if (!(chip->options & NAND_BUSWIDTH_16))
885
config3 |= NFC_V3_CONFIG3_FW8;
887
writel(config3, NFC_V3_CONFIG3);
889
writel(0, NFC_V3_DELAY_LINE);
892
/* Used by the upper layer to write command to NAND Flash for
893
* different operations to be carried out on NAND Flash */
894
static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
895
int column, int page_addr)
897
struct nand_chip *nand_chip = mtd->priv;
898
struct mxc_nand_host *host = nand_chip->priv;
900
DEBUG(MTD_DEBUG_LEVEL3,
901
"mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
902
command, column, page_addr);
904
/* Reset command state information */
905
host->status_request = false;
907
/* Command pre-processing step */
825
908
switch (command) {
827
909
case NAND_CMD_RESET:
911
host->send_cmd(host, command, false);
914
case NAND_CMD_STATUS:
916
host->status_request = true;
918
host->send_cmd(host, command, true);
919
mxc_do_addr_cycle(mtd, column, page_addr);
830
923
case NAND_CMD_READOOB:
832
if (host->pagesize_2k) {
833
/* send read confirm command */
834
send_cmd(host, NAND_CMD_READSTART, true);
835
/* read for each AREA */
836
send_read_page(host, 0, host->spare_only);
837
send_read_page(host, 1, host->spare_only);
838
send_read_page(host, 2, host->spare_only);
839
send_read_page(host, 3, host->spare_only);
841
send_read_page(host, 0, host->spare_only);
924
if (command == NAND_CMD_READ0)
925
host->buf_start = column;
927
host->buf_start = column + mtd->writesize;
929
command = NAND_CMD_READ0; /* only READ0 is valid */
931
host->send_cmd(host, command, false);
932
mxc_do_addr_cycle(mtd, column, page_addr);
934
if (mtd->writesize > 512)
935
host->send_cmd(host, NAND_CMD_READSTART, true);
937
host->send_page(mtd, NFC_OUTPUT);
939
memcpy(host->data_buf, host->main_area0, mtd->writesize);
940
copy_spare(mtd, true);
944
if (column >= mtd->writesize)
945
/* call ourself to read a page */
946
mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
948
host->buf_start = column;
950
host->send_cmd(host, command, false);
951
mxc_do_addr_cycle(mtd, column, page_addr);
954
case NAND_CMD_PAGEPROG:
955
memcpy(host->main_area0, host->data_buf, mtd->writesize);
956
copy_spare(mtd, false);
957
host->send_page(mtd, NFC_INPUT);
958
host->send_cmd(host, command, true);
959
mxc_do_addr_cycle(mtd, column, page_addr);
844
962
case NAND_CMD_READID:
849
case NAND_CMD_PAGEPROG:
852
case NAND_CMD_STATUS:
963
host->send_cmd(host, command, true);
964
mxc_do_addr_cycle(mtd, column, page_addr);
965
host->send_read_id(host);
966
host->buf_start = column;
969
case NAND_CMD_ERASE1:
855
970
case NAND_CMD_ERASE2:
971
host->send_cmd(host, command, false);
972
mxc_do_addr_cycle(mtd, column, page_addr);
860
/* Define some generic bad / good block scan pattern which are used
861
* while scanning a device for factory marked good / bad blocks. */
862
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
864
static struct nand_bbt_descr smallpage_memorybased = {
865
.options = NAND_BBT_SCAN2NDPAGE,
868
.pattern = scan_ff_pattern
979
* The generic flash bbt decriptors overlap with our ecc
980
* hardware, so define some i.MX specific ones.
982
static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
983
static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
985
static struct nand_bbt_descr bbt_main_descr = {
986
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
987
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
992
.pattern = bbt_pattern,
995
static struct nand_bbt_descr bbt_mirror_descr = {
996
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
997
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1002
.pattern = mirror_pattern,
871
1005
static int __init mxcnd_probe(struct platform_device *pdev)
923
host->regs = ioremap(res->start, res->end - res->start + 1);
1060
host->base = ioremap(res->start, resource_size(res));
929
tmp = readw(host->regs + NFC_CONFIG1);
931
writew(tmp, host->regs + NFC_CONFIG1);
933
init_waitqueue_head(&host->irq_waitq);
935
host->irq = platform_get_irq(pdev, 0);
937
err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
1066
host->main_area0 = host->base;
1068
if (nfc_is_v1() || nfc_is_v21()) {
1069
host->preset = preset_v1_v2;
1070
host->send_cmd = send_cmd_v1_v2;
1071
host->send_addr = send_addr_v1_v2;
1072
host->send_page = send_page_v1_v2;
1073
host->send_read_id = send_read_id_v1_v2;
1074
host->get_dev_status = get_dev_status_v1_v2;
1075
host->check_int = check_int_v1_v2;
1077
host->irq_control = irq_control_mx21;
1079
host->irq_control = irq_control_v1_v2;
1083
host->regs = host->base + 0x1e00;
1084
host->spare0 = host->base + 0x1000;
1085
host->spare_len = 64;
1086
oob_smallpage = &nandv2_hw_eccoob_smallpage;
1087
oob_largepage = &nandv2_hw_eccoob_largepage;
1088
this->ecc.bytes = 9;
1089
} else if (nfc_is_v1()) {
1090
host->regs = host->base + 0xe00;
1091
host->spare0 = host->base + 0x800;
1092
host->spare_len = 16;
1093
oob_smallpage = &nandv1_hw_eccoob_smallpage;
1094
oob_largepage = &nandv1_hw_eccoob_largepage;
1095
this->ecc.bytes = 3;
1097
} else if (nfc_is_v3_2()) {
1098
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1103
host->regs_ip = ioremap(res->start, resource_size(res));
1104
if (!host->regs_ip) {
1108
host->regs_axi = host->base + 0x1e00;
1109
host->spare0 = host->base + 0x1000;
1110
host->spare_len = 64;
1111
host->preset = preset_v3;
1112
host->send_cmd = send_cmd_v3;
1113
host->send_addr = send_addr_v3;
1114
host->send_page = send_page_v3;
1115
host->send_read_id = send_read_id_v3;
1116
host->check_int = check_int_v3;
1117
host->get_dev_status = get_dev_status_v3;
1118
host->irq_control = irq_control_v3;
1119
oob_smallpage = &nandv2_hw_eccoob_smallpage;
1120
oob_largepage = &nandv2_hw_eccoob_largepage;
1124
this->ecc.size = 512;
1125
this->ecc.layout = oob_smallpage;
941
1127
if (pdata->hw_ecc) {
942
1128
this->ecc.calculate = mxc_nand_calculate_ecc;
943
1129
this->ecc.hwctl = mxc_nand_enable_hwecc;
944
this->ecc.correct = mxc_nand_correct_data;
1131
this->ecc.correct = mxc_nand_correct_data_v1;
1133
this->ecc.correct = mxc_nand_correct_data_v2_v3;
945
1134
this->ecc.mode = NAND_ECC_HW;
946
this->ecc.size = 512;
948
tmp = readw(host->regs + NFC_CONFIG1);
950
writew(tmp, host->regs + NFC_CONFIG1);
952
this->ecc.size = 512;
954
this->ecc.layout = &nand_hw_eccoob_8;
955
1136
this->ecc.mode = NAND_ECC_SOFT;
956
tmp = readw(host->regs + NFC_CONFIG1);
958
writew(tmp, host->regs + NFC_CONFIG1);
962
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
964
/* preset operation */
965
/* Unlock the internal RAM Buffer */
966
writew(0x2, host->regs + NFC_CONFIG);
968
/* Blocks to be unlocked */
969
writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
970
writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
972
/* Unlock Block Command for given address range */
973
writew(0x4, host->regs + NFC_WRPROT);
975
1139
/* NAND bus width determines access funtions used by upper layer */
976
if (pdata->width == 2) {
1140
if (pdata->width == 2)
977
1141
this->options |= NAND_BUSWIDTH_16;
978
this->ecc.layout = &nand_hw_eccoob_16;
1143
if (pdata->flash_bbt) {
1144
this->bbt_td = &bbt_main_descr;
1145
this->bbt_md = &bbt_mirror_descr;
1146
/* update flash based bbt */
1147
this->options |= NAND_USE_FLASH_BBT;
1150
init_completion(&host->op_completion);
1152
host->irq = platform_get_irq(pdev, 0);
1155
* mask the interrupt. For i.MX21 explicitely call
1156
* irq_control_v1_v2 to use the mask bit. We can't call
1157
* disable_irq_nosync() for an interrupt we do not own yet.
1160
irq_control_v1_v2(host, 0);
1162
host->irq_control(host, 0);
1164
err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1168
host->irq_control(host, 0);
1171
* Now that the interrupt is disabled make sure the interrupt
1172
* mask bit is cleared on i.MX21. Otherwise we can't read
1173
* the interrupt status bit on this machine.
1176
irq_control_v1_v2(host, 1);
981
1178
/* first scan to find the device and get the page size */
982
if (nand_scan_ident(mtd, 1)) {
1179
if (nand_scan_ident(mtd, 1, NULL)) {
987
if (mtd->writesize == 2048) {
988
host->pagesize_2k = 1;
989
this->badblock_pattern = &smallpage_memorybased;
1184
/* Call preset again, with correct writesize this time */
992
if (this->ecc.mode == NAND_ECC_HW) {
993
switch (mtd->oobsize) {
995
this->ecc.layout = &nand_hw_eccoob_8;
998
this->ecc.layout = &nand_hw_eccoob_16;
1001
this->ecc.layout = &nand_hw_eccoob_64;
1004
/* page size not handled by HW ECC */
1005
/* switching back to soft ECC */
1006
this->ecc.size = 512;
1007
this->ecc.bytes = 3;
1008
this->ecc.layout = &nand_hw_eccoob_8;
1009
this->ecc.mode = NAND_ECC_SOFT;
1010
this->ecc.calculate = NULL;
1011
this->ecc.correct = NULL;
1012
this->ecc.hwctl = NULL;
1013
tmp = readw(host->regs + NFC_CONFIG1);
1015
writew(tmp, host->regs + NFC_CONFIG1);
1187
if (mtd->writesize == 2048)
1188
this->ecc.layout = oob_largepage;
1020
1190
/* second phase scan */
1021
1191
if (nand_scan_tail(mtd)) {