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Viewing changes to arch/arm/plat-s3c64xx/cpufreq.c

  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno, Martin Michlmayr
  • Date: 2011-04-06 13:53:30 UTC
  • mfrom: (43.1.5 sid)
  • Revision ID: james.westby@ubuntu.com-20110406135330-wjufxhd0tvn3zx4z
Tags: 2.6.38-3
http://bugs.debian.org/620124
http://bugs.debian.org/620284
http://bugs.debian.org/620204
[ Ben Hutchings ]
* [ppc64] Add to linux-tools package architectures (Closes: #620124)
* [amd64] Save cr4 to mmu_cr4_features at boot time (Closes: #620284)
* appletalk: Fix bugs introduced when removing use of BKL
* ALSA: Fix yet another race in disconnection
* cciss: Fix lost command issue
* ath9k: Fix kernel panic in AR2427
* ses: Avoid kernel panic when lun 0 is not mapped
* PCI/ACPI: Report ASPM support to BIOS if not disabled from command line

[ Aurelien Jarno ]
* rtlwifi: fix build when PCI is not enabled.

[ Martin Michlmayr ]
* rtlwifi: Eliminate udelay calls with too large values (Closes: #620204)

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arch/arm/plat-s3c64xx/cpufreq.c
1
 
/* linux/arch/arm/plat-s3c64xx/cpufreq.c
2
 
 *
3
 
 * Copyright 2009 Wolfson Microelectronics plc
4
 
 *
5
 
 * S3C64xx CPUfreq Support
6
 
 *
7
 
 * This program is free software; you can redistribute it and/or modify
8
 
 * it under the terms of the GNU General Public License version 2 as
9
 
 * published by the Free Software Foundation.
10
 
 */
11
 
 
12
 
#include <linux/kernel.h>
13
 
#include <linux/types.h>
14
 
#include <linux/init.h>
15
 
#include <linux/cpufreq.h>
16
 
#include <linux/clk.h>
17
 
#include <linux/err.h>
18
 
#include <linux/regulator/consumer.h>
19
 
 
20
 
static struct clk *armclk;
21
 
static struct regulator *vddarm;
22
 
 
23
 
#ifdef CONFIG_CPU_S3C6410
24
 
struct s3c64xx_dvfs {
25
 
        unsigned int vddarm_min;
26
 
        unsigned int vddarm_max;
27
 
};
28
 
 
29
 
static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
30
 
        [0] = { 1000000, 1000000 },
31
 
        [1] = { 1000000, 1050000 },
32
 
        [2] = { 1050000, 1100000 },
33
 
        [3] = { 1050000, 1150000 },
34
 
        [4] = { 1250000, 1350000 },
35
 
};
36
 
 
37
 
static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
38
 
        { 0,  66000 },
39
 
        { 0, 133000 },
40
 
        { 1, 222000 },
41
 
        { 1, 266000 },
42
 
        { 2, 333000 },
43
 
        { 2, 400000 },
44
 
        { 3, 532000 },
45
 
        { 3, 533000 },
46
 
        { 4, 667000 },
47
 
        { 0, CPUFREQ_TABLE_END },
48
 
};
49
 
#endif
50
 
 
51
 
static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
52
 
{
53
 
        if (policy->cpu != 0)
54
 
                return -EINVAL;
55
 
 
56
 
        return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
57
 
}
58
 
 
59
 
static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
60
 
{
61
 
        if (cpu != 0)
62
 
                return 0;
63
 
 
64
 
        return clk_get_rate(armclk) / 1000;
65
 
}
66
 
 
67
 
static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
68
 
                                      unsigned int target_freq,
69
 
                                      unsigned int relation)
70
 
{
71
 
        int ret;
72
 
        unsigned int i;
73
 
        struct cpufreq_freqs freqs;
74
 
        struct s3c64xx_dvfs *dvfs;
75
 
 
76
 
        ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
77
 
                                             target_freq, relation, &i);
78
 
        if (ret != 0)
79
 
                return ret;
80
 
 
81
 
        freqs.cpu = 0;
82
 
        freqs.old = clk_get_rate(armclk) / 1000;
83
 
        freqs.new = s3c64xx_freq_table[i].frequency;
84
 
        freqs.flags = 0;
85
 
        dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
86
 
 
87
 
        if (freqs.old == freqs.new)
88
 
                return 0;
89
 
 
90
 
        pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
91
 
 
92
 
        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
 
 
94
 
#ifdef CONFIG_REGULATOR
95
 
        if (vddarm && freqs.new > freqs.old) {
96
 
                ret = regulator_set_voltage(vddarm,
97
 
                                            dvfs->vddarm_min,
98
 
                                            dvfs->vddarm_max);
99
 
                if (ret != 0) {
100
 
                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
101
 
                               freqs.new, ret);
102
 
                        goto err;
103
 
                }
104
 
        }
105
 
#endif
106
 
 
107
 
        ret = clk_set_rate(armclk, freqs.new * 1000);
108
 
        if (ret < 0) {
109
 
                pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
110
 
                       freqs.new, ret);
111
 
                goto err;
112
 
        }
113
 
 
114
 
#ifdef CONFIG_REGULATOR
115
 
        if (vddarm && freqs.new < freqs.old) {
116
 
                ret = regulator_set_voltage(vddarm,
117
 
                                            dvfs->vddarm_min,
118
 
                                            dvfs->vddarm_max);
119
 
                if (ret != 0) {
120
 
                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
121
 
                               freqs.new, ret);
122
 
                        goto err_clk;
123
 
                }
124
 
        }
125
 
#endif
126
 
 
127
 
        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
128
 
 
129
 
        pr_debug("cpufreq: Set actual frequency %lukHz\n",
130
 
                 clk_get_rate(armclk) / 1000);
131
 
 
132
 
        return 0;
133
 
 
134
 
err_clk:
135
 
        if (clk_set_rate(armclk, freqs.old * 1000) < 0)
136
 
                pr_err("Failed to restore original clock rate\n");
137
 
err:
138
 
        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
139
 
 
140
 
        return ret;
141
 
}
142
 
 
143
 
#ifdef CONFIG_REGULATOR
144
 
static void __init s3c64xx_cpufreq_constrain_voltages(void)
145
 
{
146
 
        int count, v, i, found;
147
 
        struct cpufreq_frequency_table *freq;
148
 
        struct s3c64xx_dvfs *dvfs;
149
 
 
150
 
        count = regulator_count_voltages(vddarm);
151
 
        if (count < 0) {
152
 
                pr_err("cpufreq: Unable to check supported voltages\n");
153
 
                return;
154
 
        }
155
 
 
156
 
        freq = s3c64xx_freq_table;
157
 
        while (freq->frequency != CPUFREQ_TABLE_END) {
158
 
                if (freq->frequency == CPUFREQ_ENTRY_INVALID)
159
 
                        continue;
160
 
 
161
 
                dvfs = &s3c64xx_dvfs_table[freq->index];
162
 
                found = 0;
163
 
 
164
 
                for (i = 0; i < count; i++) {
165
 
                        v = regulator_list_voltage(vddarm, i);
166
 
                        if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
167
 
                                found = 1;
168
 
                }
169
 
 
170
 
                if (!found) {
171
 
                        pr_debug("cpufreq: %dkHz unsupported by regulator\n",
172
 
                                 freq->frequency);
173
 
                        freq->frequency = CPUFREQ_ENTRY_INVALID;
174
 
                }
175
 
 
176
 
                freq++;
177
 
        }
178
 
}
179
 
#endif
180
 
 
181
 
static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
182
 
{
183
 
        int ret;
184
 
        struct cpufreq_frequency_table *freq;
185
 
 
186
 
        if (policy->cpu != 0)
187
 
                return -EINVAL;
188
 
 
189
 
        if (s3c64xx_freq_table == NULL) {
190
 
                pr_err("cpufreq: No frequency information for this CPU\n");
191
 
                return -ENODEV;
192
 
        }
193
 
 
194
 
        armclk = clk_get(NULL, "armclk");
195
 
        if (IS_ERR(armclk)) {
196
 
                pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
197
 
                       PTR_ERR(armclk));
198
 
                return PTR_ERR(armclk);
199
 
        }
200
 
 
201
 
#ifdef CONFIG_REGULATOR
202
 
        vddarm = regulator_get(NULL, "vddarm");
203
 
        if (IS_ERR(vddarm)) {
204
 
                ret = PTR_ERR(vddarm);
205
 
                pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
206
 
                pr_err("cpufreq: Only frequency scaling available\n");
207
 
                vddarm = NULL;
208
 
        } else {
209
 
                s3c64xx_cpufreq_constrain_voltages();
210
 
        }
211
 
#endif
212
 
 
213
 
        freq = s3c64xx_freq_table;
214
 
        while (freq->frequency != CPUFREQ_TABLE_END) {
215
 
                unsigned long r;
216
 
 
217
 
                /* Check for frequencies we can generate */
218
 
                r = clk_round_rate(armclk, freq->frequency * 1000);
219
 
                r /= 1000;
220
 
                if (r != freq->frequency)
221
 
                        freq->frequency = CPUFREQ_ENTRY_INVALID;
222
 
 
223
 
                /* If we have no regulator then assume startup
224
 
                 * frequency is the maximum we can support. */
225
 
                if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
226
 
                        freq->frequency = CPUFREQ_ENTRY_INVALID;
227
 
 
228
 
                freq++;
229
 
        }
230
 
 
231
 
        policy->cur = clk_get_rate(armclk) / 1000;
232
 
 
233
 
        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
234
 
         * write plus clock reprogramming. */
235
 
        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
236
 
 
237
 
        ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
238
 
        if (ret != 0) {
239
 
                pr_err("cpufreq: Failed to configure frequency table: %d\n",
240
 
                       ret);
241
 
                regulator_put(vddarm);
242
 
                clk_put(armclk);
243
 
        }
244
 
 
245
 
        return ret;
246
 
}
247
 
 
248
 
static struct cpufreq_driver s3c64xx_cpufreq_driver = {
249
 
        .owner          = THIS_MODULE,
250
 
        .flags          = 0,
251
 
        .verify         = s3c64xx_cpufreq_verify_speed,
252
 
        .target         = s3c64xx_cpufreq_set_target,
253
 
        .get            = s3c64xx_cpufreq_get_speed,
254
 
        .init           = s3c64xx_cpufreq_driver_init,
255
 
        .name           = "s3c",
256
 
};
257
 
 
258
 
static int __init s3c64xx_cpufreq_init(void)
259
 
{
260
 
        return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
261
 
}
262
 
module_init(s3c64xx_cpufreq_init);