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Viewing changes to drivers/net/wireless/ath/ath9k/eeprom_4k.c

  • Committer: Bazaar Package Importer
  • Author(s): Ben Hutchings, Ben Hutchings, Aurelien Jarno, Martin Michlmayr
  • Date: 2011-04-06 13:53:30 UTC
  • mfrom: (43.1.5 sid)
  • Revision ID: james.westby@ubuntu.com-20110406135330-wjufxhd0tvn3zx4z
Tags: 2.6.38-3
http://bugs.debian.org/620124
http://bugs.debian.org/620284
http://bugs.debian.org/620204
[ Ben Hutchings ]
* [ppc64] Add to linux-tools package architectures (Closes: #620124)
* [amd64] Save cr4 to mmu_cr4_features at boot time (Closes: #620284)
* appletalk: Fix bugs introduced when removing use of BKL
* ALSA: Fix yet another race in disconnection
* cciss: Fix lost command issue
* ath9k: Fix kernel panic in AR2427
* ses: Avoid kernel panic when lun 0 is not mapped
* PCI/ACPI: Report ASPM support to BIOS if not disabled from command line

[ Aurelien Jarno ]
* rtlwifi: fix build when PCI is not enabled.

[ Martin Michlmayr ]
* rtlwifi: Eliminate udelay calls with too large values (Closes: #620204)

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Lines of Context:
drivers/net/wireless/ath/ath9k/eeprom_4k.c
14
14
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15
15
 */
16
16
 
17
 
#include "ath9k.h"
 
17
#include "hw.h"
 
18
#include "ar9002_phy.h"
18
19
 
19
20
static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20
21
{
29
30
static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30
31
{
31
32
#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 
33
        struct ath_common *common = ath9k_hw_common(ah);
32
34
        u16 *eep_data = (u16 *)&ah->eeprom.map4k;
33
35
        int addr, eep_start_loc = 0;
34
36
 
35
37
        eep_start_loc = 64;
36
38
 
37
39
        if (!ath9k_hw_use_flash(ah)) {
38
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
40
                ath_dbg(common, ATH_DBG_EEPROM,
39
41
                        "Reading from EEPROM, not flash\n");
40
42
        }
41
43
 
42
44
        for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43
 
                if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44
 
                        DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
45
 
                               "Unable to read eeprom region \n");
 
45
                if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
 
46
                        ath_dbg(common, ATH_DBG_EEPROM,
 
47
                                "Unable to read eeprom region\n");
46
48
                        return false;
47
49
                }
48
50
                eep_data++;
55
57
static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
56
58
{
57
59
#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 
60
        struct ath_common *common = ath9k_hw_common(ah);
58
61
        struct ar5416_eeprom_4k *eep =
59
62
                (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
60
63
        u16 *eepdata, temp, magic, magic2;
64
67
 
65
68
 
66
69
        if (!ath9k_hw_use_flash(ah)) {
67
 
                if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 
70
                if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
68
71
                                         &magic)) {
69
 
                        DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
70
 
                                "Reading Magic # failed\n");
 
72
                        ath_err(common, "Reading Magic # failed\n");
71
73
                        return false;
72
74
                }
73
75
 
74
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
76
                ath_dbg(common, ATH_DBG_EEPROM,
75
77
                        "Read Magic = 0x%04X\n", magic);
76
78
 
77
79
                if (magic != AR5416_EEPROM_MAGIC) {
87
89
                                        eepdata++;
88
90
                                }
89
91
                        } else {
90
 
                                DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
91
 
                                        "Invalid EEPROM Magic. "
92
 
                                        "endianness mismatch.\n");
 
92
                                ath_err(common,
 
93
                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
93
94
                                return -EINVAL;
94
95
                        }
95
96
                }
96
97
        }
97
98
 
98
 
        DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 
99
        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
99
100
                need_swap ? "True" : "False");
100
101
 
101
102
        if (need_swap)
117
118
                u32 integer;
118
119
                u16 word;
119
120
 
120
 
                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
121
                ath_dbg(common, ATH_DBG_EEPROM,
121
122
                        "EEPROM Endianness is not native.. Changing\n");
122
123
 
123
124
                word = swab16(eep->baseEepHeader.length);
152
153
                        eep->modalHeader.antCtrlChain[i] = integer;
153
154
                }
154
155
 
155
 
                for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 
156
                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
156
157
                        word = swab16(eep->modalHeader.spurChans[i].spurChan);
157
158
                        eep->modalHeader.spurChans[i].spurChan = word;
158
159
                }
160
161
 
161
162
        if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162
163
            ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163
 
                DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
164
 
                        "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 
164
                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165
165
                        sum, ah->eep_ops->get_eeprom_ver(ah));
166
166
                return -EINVAL;
167
167
        }
176
176
        struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
177
177
        struct modal_eep_4k_header *pModal = &eep->modalHeader;
178
178
        struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 
179
        u16 ver_minor;
 
180
 
 
181
        ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
179
182
 
180
183
        switch (param) {
181
184
        case EEP_NFTHRESH_2:
182
185
                return pModal->noiseFloorThreshCh[0];
183
 
        case AR_EEPROM_MAC(0):
 
186
        case EEP_MAC_LSW:
184
187
                return pBase->macAddr[0] << 8 | pBase->macAddr[1];
185
 
        case AR_EEPROM_MAC(1):
 
188
        case EEP_MAC_MID:
186
189
                return pBase->macAddr[2] << 8 | pBase->macAddr[3];
187
 
        case AR_EEPROM_MAC(2):
 
190
        case EEP_MAC_MSW:
188
191
                return pBase->macAddr[4] << 8 | pBase->macAddr[5];
189
192
        case EEP_REG_0:
190
193
                return pBase->regDmn[0];
201
204
        case EEP_DB_2:
202
205
                return pModal->db1_1;
203
206
        case EEP_MINOR_REV:
204
 
                return pBase->version & AR5416_EEP_VER_MINOR_MASK;
 
207
                return ver_minor;
205
208
        case EEP_TX_MASK:
206
209
                return pBase->txMask;
207
210
        case EEP_RX_MASK:
208
211
                return pBase->rxMask;
209
212
        case EEP_FRAC_N_5G:
210
213
                return 0;
 
214
        case EEP_PWR_TABLE_OFFSET:
 
215
                return AR5416_PWR_TABLE_OFFSET_DB;
 
216
        case EEP_MODAL_VER:
 
217
                return pModal->version;
 
218
        case EEP_ANT_DIV_CTL1:
 
219
                return pModal->antdiv_ctl1;
 
220
        case EEP_TXGAIN_TYPE:
 
221
                if (ver_minor >= AR5416_EEP_MINOR_VER_19)
 
222
                        return pBase->txGainType;
 
223
                else
 
224
                        return AR5416_EEP_TXGAIN_ORIGINAL;
211
225
        default:
212
226
                return 0;
213
227
        }
214
228
}
215
229
 
216
 
static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
217
 
                                struct ath9k_channel *chan,
218
 
                                struct cal_data_per_freq_4k *pRawDataSet,
219
 
                                u8 *bChans, u16 availPiers,
220
 
                                u16 tPdGainOverlap, int16_t *pMinCalPower,
221
 
                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
222
 
                                u16 numXpdGains)
223
 
{
224
 
#define TMP_VAL_VPD_TABLE \
225
 
        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
226
 
        int i, j, k;
227
 
        int16_t ss;
228
 
        u16 idxL = 0, idxR = 0, numPiers;
229
 
        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
230
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
231
 
        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
232
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
233
 
        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
234
 
                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
235
 
 
236
 
        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
237
 
        u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
238
 
        u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
239
 
        int16_t vpdStep;
240
 
        int16_t tmpVal;
241
 
        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
242
 
        bool match;
243
 
        int16_t minDelta = 0;
244
 
        struct chan_centers centers;
245
 
#define PD_GAIN_BOUNDARY_DEFAULT 58;
246
 
 
247
 
        ath9k_hw_get_channel_centers(ah, chan, &centers);
248
 
 
249
 
        for (numPiers = 0; numPiers < availPiers; numPiers++) {
250
 
                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
251
 
                        break;
252
 
        }
253
 
 
254
 
        match = ath9k_hw_get_lower_upper_index(
255
 
                                        (u8)FREQ2FBIN(centers.synth_center,
256
 
                                        IS_CHAN_2GHZ(chan)), bChans, numPiers,
257
 
                                        &idxL, &idxR);
258
 
 
259
 
        if (match) {
260
 
                for (i = 0; i < numXpdGains; i++) {
261
 
                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
262
 
                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
263
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
264
 
                                        pRawDataSet[idxL].pwrPdg[i],
265
 
                                        pRawDataSet[idxL].vpdPdg[i],
266
 
                                        AR5416_EEP4K_PD_GAIN_ICEPTS,
267
 
                                        vpdTableI[i]);
268
 
                }
269
 
        } else {
270
 
                for (i = 0; i < numXpdGains; i++) {
271
 
                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
272
 
                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
273
 
                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
274
 
                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
275
 
 
276
 
                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
277
 
 
278
 
                        maxPwrT4[i] =
279
 
                                min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
280
 
                                    pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
281
 
 
282
 
 
283
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
284
 
                                                pPwrL, pVpdL,
285
 
                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
286
 
                                                vpdTableL[i]);
287
 
                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
288
 
                                                pPwrR, pVpdR,
289
 
                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
290
 
                                                vpdTableR[i]);
291
 
 
292
 
                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
293
 
                                vpdTableI[i][j] =
294
 
                                        (u8)(ath9k_hw_interpolate((u16)
295
 
                                             FREQ2FBIN(centers.
296
 
                                                       synth_center,
297
 
                                                       IS_CHAN_2GHZ
298
 
                                                       (chan)),
299
 
                                             bChans[idxL], bChans[idxR],
300
 
                                             vpdTableL[i][j], vpdTableR[i][j]));
301
 
                        }
302
 
                }
303
 
        }
304
 
 
305
 
        *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
306
 
 
307
 
        k = 0;
308
 
 
309
 
        for (i = 0; i < numXpdGains; i++) {
310
 
                if (i == (numXpdGains - 1))
311
 
                        pPdGainBoundaries[i] =
312
 
                                (u16)(maxPwrT4[i] / 2);
313
 
                else
314
 
                        pPdGainBoundaries[i] =
315
 
                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
316
 
 
317
 
                pPdGainBoundaries[i] =
318
 
                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
319
 
 
320
 
                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
321
 
                        minDelta = pPdGainBoundaries[0] - 23;
322
 
                        pPdGainBoundaries[0] = 23;
323
 
                } else {
324
 
                        minDelta = 0;
325
 
                }
326
 
 
327
 
                if (i == 0) {
328
 
                        if (AR_SREV_9280_10_OR_LATER(ah))
329
 
                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
330
 
                        else
331
 
                                ss = 0;
332
 
                } else {
333
 
                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
334
 
                                        (minPwrT4[i] / 2)) -
335
 
                                       tPdGainOverlap + 1 + minDelta);
336
 
                }
337
 
                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
338
 
                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
339
 
 
340
 
                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
341
 
                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
342
 
                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
343
 
                        ss++;
344
 
                }
345
 
 
346
 
                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
347
 
                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
348
 
                                (minPwrT4[i] / 2));
349
 
                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
350
 
                        tgtIndex : sizeCurrVpdTable;
351
 
 
352
 
                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
353
 
                        pPDADCValues[k++] = vpdTableI[i][ss++];
354
 
 
355
 
                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
356
 
                                    vpdTableI[i][sizeCurrVpdTable - 2]);
357
 
                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
358
 
 
359
 
                if (tgtIndex >= maxIndex) {
360
 
                        while ((ss <= tgtIndex) &&
361
 
                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
362
 
                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
363
 
                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
364
 
                                                         255 : tmpVal);
365
 
                                ss++;
366
 
                        }
367
 
                }
368
 
        }
369
 
 
370
 
        while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
371
 
                pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
372
 
                i++;
373
 
        }
374
 
 
375
 
        while (k < AR5416_NUM_PDADC_VALUES) {
376
 
                pPDADCValues[k] = pPDADCValues[k - 1];
377
 
                k++;
378
 
        }
379
 
 
380
 
        return;
381
 
#undef TMP_VAL_VPD_TABLE
382
 
}
383
 
 
384
230
static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
385
231
                                  struct ath9k_channel *chan,
386
232
                                  int16_t *pTxPowerIndexOffset)
387
233
{
 
234
        struct ath_common *common = ath9k_hw_common(ah);
388
235
        struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
389
236
        struct cal_data_per_freq_4k *pRawDataset;
390
237
        u8 *pCalBChans = NULL;
391
238
        u16 pdGainOverlap_t2;
392
239
        static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
393
 
        u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
 
240
        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
394
241
        u16 numPiers, i, j;
395
 
        int16_t tMinCalPower;
396
242
        u16 numXpdGain, xpdMask;
397
243
        u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
398
244
        u32 reg32, regOffset, regChainOffset;
413
259
 
414
260
        numXpdGain = 0;
415
261
 
416
 
        for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
417
 
                if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
 
262
        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 
263
                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
418
264
                        if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
419
265
                                break;
420
266
                        xpdGainValues[numXpdGain] =
421
 
                                (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
 
267
                                (u16)(AR5416_PD_GAINS_IN_MASK - i);
422
268
                        numXpdGain++;
423
269
                }
424
270
        }
442
288
                if (pEepData->baseEepHeader.txMask & (1 << i)) {
443
289
                        pRawDataset = pEepData->calPierData2G[i];
444
290
 
445
 
                        ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
 
291
                        ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
446
292
                                            pRawDataset, pCalBChans,
447
293
                                            numPiers, pdGainOverlap_t2,
448
 
                                            &tMinCalPower, gainBoundaries,
 
294
                                            gainBoundaries,
449
295
                                            pdadcValues, numXpdGain);
450
296
 
 
297
                        ENABLE_REGWRITE_BUFFER(ah);
 
298
 
451
299
                        if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
452
300
                                REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
453
301
                                          SM(pdGainOverlap_t2,
470
318
                                        ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471
319
                                REG_WRITE(ah, regOffset, reg32);
472
320
 
473
 
                                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
321
                                ath_dbg(common, ATH_DBG_EEPROM,
474
322
                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
475
323
                                        i, regChainOffset, regOffset,
476
324
                                        reg32);
477
 
                                DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 
325
                                ath_dbg(common, ATH_DBG_EEPROM,
478
326
                                        "PDADC: Chain %d | "
479
327
                                        "PDADC %3d Value %3d | "
480
328
                                        "PDADC %3d Value %3d | "
483
331
                                        i, 4 * j, pdadcValues[4 * j],
484
332
                                        4 * j + 1, pdadcValues[4 * j + 1],
485
333
                                        4 * j + 2, pdadcValues[4 * j + 2],
486
 
                                        4 * j + 3,
487
 
                                        pdadcValues[4 * j + 3]);
 
334
                                        4 * j + 3, pdadcValues[4 * j + 3]);
488
335
 
489
336
                                regOffset += 4;
490
337
                        }
 
338
 
 
339
                        REGWRITE_BUFFER_FLUSH(ah);
491
340
                }
492
341
        }
493
342
 
512
361
        int i;
513
362
        int16_t twiceLargestAntenna;
514
363
        u16 twiceMinEdgePower;
515
 
        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
364
        u16 twiceMaxEdgePower = MAX_RATE_POWER;
516
365
        u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
517
 
        u16 numCtlModes, *pCtlMode, ctlMode, freq;
 
366
        u16 numCtlModes;
 
367
        const u16 *pCtlMode;
 
368
        u16 ctlMode, freq;
518
369
        struct chan_centers centers;
519
370
        struct cal_ctl_data_4k *rep;
520
371
        struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
521
372
        static const u16 tpScaleReductionTable[5] =
522
 
                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 
373
                { 0, 3, 6, 9, MAX_RATE_POWER };
523
374
        struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
524
375
                0, { 0, 0, 0, 0}
525
376
        };
530
381
        struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
531
382
                0, {0, 0, 0, 0}
532
383
        };
533
 
        u16 ctlModesFor11g[] =
534
 
                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
535
 
                  CTL_2GHT40
536
 
                };
 
384
        static const u16 ctlModesFor11g[] = {
 
385
                CTL_11B, CTL_11G, CTL_2GHT20,
 
386
                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 
387
        };
537
388
 
538
389
        ath9k_hw_get_channel_centers(ah, chan, &centers);
539
390
 
595
446
 
596
447
                if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
597
448
                    ah->eep_ops->get_eeprom_rev(ah) <= 2)
598
 
                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 
449
                        twiceMaxEdgePower = MAX_RATE_POWER;
599
450
 
600
451
                for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
601
452
                             pEepData->ctlIndex[i]; i++) {
706
557
                                    u16 cfgCtl,
707
558
                                    u8 twiceAntennaReduction,
708
559
                                    u8 twiceMaxRegulatoryPower,
709
 
                                    u8 powerLimit)
 
560
                                    u8 powerLimit, bool test)
710
561
{
711
562
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
712
563
        struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
731
582
 
732
583
        ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
733
584
 
 
585
        regulatory->max_power_level = 0;
734
586
        for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
735
587
                ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
736
 
                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
737
 
                        ratesArray[i] = AR5416_MAX_RATE_POWER;
 
588
                if (ratesArray[i] > MAX_RATE_POWER)
 
589
                        ratesArray[i] = MAX_RATE_POWER;
 
590
 
 
591
                if (ratesArray[i] > regulatory->max_power_level)
 
592
                        regulatory->max_power_level = ratesArray[i];
738
593
        }
739
594
 
 
595
        if (test)
 
596
            return;
740
597
 
741
598
        /* Update regulatory */
742
 
 
743
599
        i = rate6mb;
744
600
        if (IS_CHAN_HT40(chan))
745
601
                i = rateHt40_0;
748
604
 
749
605
        regulatory->max_power_level = ratesArray[i];
750
606
 
751
 
        if (AR_SREV_9280_10_OR_LATER(ah)) {
 
607
        if (AR_SREV_9280_20_OR_LATER(ah)) {
752
608
                for (i = 0; i < Ar5416RateSize; i++)
753
 
                        ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
 
609
                        ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
754
610
        }
755
611
 
 
612
        ENABLE_REGWRITE_BUFFER(ah);
 
613
 
756
614
        /* OFDM power per rate */
757
615
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
758
616
                  ATH9K_POW_SM(ratesArray[rate18mb], 24)
815
673
                          | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
816
674
                          | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
817
675
        }
 
676
 
 
677
        REGWRITE_BUFFER_FLUSH(ah);
818
678
}
819
679
 
820
680
static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
891
751
                      AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
892
752
        REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
893
753
                      AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
894
 
 
895
 
        if (AR_SREV_9285_11(ah))
896
 
                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
897
754
}
898
755
 
899
756
/*
913
770
        pModal = &eep->modalHeader;
914
771
        txRxAttenLocal = 23;
915
772
 
916
 
        REG_WRITE(ah, AR_PHY_SWITCH_COM,
917
 
                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 
773
        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
918
774
 
919
775
        /* Single chain for 4K EEPROM*/
920
776
        ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
1091
947
        }
1092
948
 
1093
949
 
1094
 
        if (AR_SREV_9285_11(ah))
1095
 
                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1096
 
 
1097
950
        REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1098
951
                      pModal->switchSettling);
1099
952
        REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1107
960
 
1108
961
        REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1109
962
                      pModal->txEndToRxOn);
 
963
 
 
964
        if (AR_SREV_9271_10(ah))
 
965
                REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 
966
                              pModal->txEndToRxOn);
1110
967
        REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1111
968
                      pModal->thresh62);
1112
969
        REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1129
986
        }
1130
987
}
1131
988
 
1132
 
static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1133
 
                                              struct ath9k_channel *chan)
1134
 
{
1135
 
        struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1136
 
        struct modal_eep_4k_header *pModal = &eep->modalHeader;
1137
 
 
1138
 
        return pModal->antCtrlCommon & 0xFFFF;
1139
 
}
1140
 
 
1141
 
static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1142
 
                                         enum ieee80211_band freq_band)
1143
 
{
1144
 
        return 1;
1145
 
}
1146
 
 
1147
989
static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1148
990
{
1149
991
#define EEP_MAP4K_SPURCHAN \
1150
992
        (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
 
993
        struct ath_common *common = ath9k_hw_common(ah);
1151
994
 
1152
995
        u16 spur_val = AR_NO_SPUR;
1153
996
 
1154
 
        DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1155
 
                "Getting spur idx %d is2Ghz. %d val %x\n",
 
997
        ath_dbg(common, ATH_DBG_ANI,
 
998
                "Getting spur idx:%d is2Ghz:%d val:%x\n",
1156
999
                i, is2GHz, ah->config.spurchans[i][is2GHz]);
1157
1000
 
1158
1001
        switch (ah->config.spurmode) {
1160
1003
                break;
1161
1004
        case SPUR_ENABLE_IOCTL:
1162
1005
                spur_val = ah->config.spurchans[i][is2GHz];
1163
 
                DPRINTF(ah->ah_sc, ATH_DBG_ANI,
 
1006
                ath_dbg(common, ATH_DBG_ANI,
1164
1007
                        "Getting spur val from new loc. %d\n", spur_val);
1165
1008
                break;
1166
1009
        case SPUR_ENABLE_EEPROM:
1179
1022
        .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1180
1023
        .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1181
1024
        .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1182
 
        .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1183
 
        .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1184
1025
        .set_board_values       = ath9k_hw_4k_set_board_values,
1185
1026
        .set_addac              = ath9k_hw_4k_set_addac,
1186
1027
        .set_txpower            = ath9k_hw_4k_set_txpower,