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Viewing changes to src/amd/compiler/tests/test_insert_waitcnt.cpp

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/amd/compiler/tests/test_insert_waitcnt.cpp
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   Operand chan_counter(PhysReg(260), v1);
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   Operand m(m0, s1);
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   Instruction *ds_instr;
 
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   Instruction* ds_instr;
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   //>> ds_ordered_count %0:v[0], %0:v[3], %0:m0 offset0:3072 gds storage:gds semantics:volatile
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   //! s_waitcnt lgkmcnt(0)
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   ds_instr = bld.ds(aco_opcode::ds_ordered_count, def0, gds_base, m, 3072u, 0u, true);
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   ds_instr->ds().sync = memory_sync_info(storage_gds, semantic_volatile);
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   //! ds_add_rtn_u32 %0:v[1], %0:v[3], %0:v[4], %0:m0 gds storage:gds semantics:volatile,atomic,rmw
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   ds_instr = bld.ds(aco_opcode::ds_add_rtn_u32, def1,
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                     gds_base, chan_counter, m, 0u, 0u, true);
 
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   ds_instr = bld.ds(aco_opcode::ds_add_rtn_u32, def1, gds_base, chan_counter, m, 0u, 0u, true);
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   ds_instr->ds().sync = memory_sync_info(storage_gds, semantic_atomicrmw);
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   //! s_waitcnt lgkmcnt(0)