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Viewing changes to src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/amd/vulkan/nir/radv_nir_lower_vs_inputs.c
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} lower_vs_inputs_state;
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static nir_ssa_def *
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lower_load_vs_input_from_prolog(nir_builder *b, nir_intrinsic_instr *intrin,
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                                lower_vs_inputs_state *s)
 
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lower_load_vs_input_from_prolog(nir_builder *b, nir_intrinsic_instr *intrin, lower_vs_inputs_state *s)
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{
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   nir_src *offset_src = nir_get_io_offset_src(intrin);
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   assert(nir_src_is_const(*offset_src));
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   const unsigned arg_bit_size = MAX2(bit_size, 32);
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   unsigned num_input_args = 1;
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   nir_ssa_def *input_args[2] = {
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      ac_nir_load_arg(b, &s->args->ac, s->args->vs_inputs[driver_location]), NULL};
 
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   nir_ssa_def *input_args[2] = {ac_nir_load_arg(b, &s->args->ac, s->args->vs_inputs[driver_location]), NULL};
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   if (component * 32 + arg_bit_size * num_components > 128) {
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      assert(bit_size == 64);
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}
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static nir_ssa_def *
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oob_input_load_value(nir_builder *b, const unsigned channel_idx, const unsigned bit_size,
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                     const bool is_float)
 
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oob_input_load_value(nir_builder *b, const unsigned channel_idx, const unsigned bit_size, const bool is_float)
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{
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   /* 22.1.1. Attribute Location and Component Assignment of Vulkan 1.3 specification:
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    * For 64-bit data types, no default attribute values are provided. Input variables
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}
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static unsigned
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count_format_bytes(const struct util_format_description *f, const unsigned first_channel,
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                   const unsigned num_channels)
 
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count_format_bytes(const struct util_format_description *f, const unsigned first_channel, const unsigned num_channels)
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{
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   if (!num_channels)
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      return 0;
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}
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static unsigned
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first_used_swizzled_channel(const struct util_format_description *f, const unsigned mask,
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                            const bool backwards)
 
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first_used_swizzled_channel(const struct util_format_description *f, const unsigned mask, const bool backwards)
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{
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   unsigned first_used = backwards ? 0 : f->nr_channels;
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   const unsigned it_mask = mask & BITFIELD_MASK(f->nr_channels);
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}
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static nir_ssa_def *
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adjust_vertex_fetch_alpha(nir_builder *b, enum ac_vs_input_alpha_adjust alpha_adjust,
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                          nir_ssa_def *alpha)
 
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adjust_vertex_fetch_alpha(nir_builder *b, enum ac_vs_input_alpha_adjust alpha_adjust, nir_ssa_def *alpha)
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{
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   if (alpha_adjust == AC_ALPHA_ADJUST_SSCALED)
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      alpha = nir_f2u32(b, alpha);
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   const struct util_format_description *f = util_format_description(attrib_format);
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   const struct ac_vtx_format_info *vtx_info =
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      ac_get_vtx_format_info(s->rad_info->gfx_level, s->rad_info->family, attrib_format);
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   const unsigned binding_index =
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      s->info->vs.use_per_attribute_vb_descs ? location : attrib_binding;
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   const unsigned desc_index =
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      util_bitcount(s->info->vs.vb_desc_usage_mask & u_bit_consecutive(0, binding_index));
 
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   const unsigned binding_index = s->info->vs.use_per_attribute_vb_descs ? location : attrib_binding;
 
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   const unsigned desc_index = util_bitcount(s->info->vs.vb_desc_usage_mask & u_bit_consecutive(0, binding_index));
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   nir_ssa_def *vertex_buffers_arg = ac_nir_load_arg(b, &s->args->ac, s->args->ac.vertex_buffers);
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   nir_ssa_def *vertex_buffers =
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      nir_pack_64_2x32_split(b, vertex_buffers_arg, nir_imm_int(b, s->rad_info->address32_hi));
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   nir_ssa_def *descriptor =
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      nir_load_smem_amd(b, 4, vertex_buffers, nir_imm_int(b, desc_index * 16));
 
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   nir_ssa_def *descriptor = nir_load_smem_amd(b, 4, vertex_buffers, nir_imm_int(b, desc_index * 16));
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   nir_ssa_def *base_index = calc_vs_input_index(b, location, s);
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   nir_ssa_def *zero = nir_imm_int(b, 0);
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    * Don't shrink the format here because this might allow the backend to
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    * emit fewer (but larger than needed) HW instructions.
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    */
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   const unsigned first_trailing_unused_channel =
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      first_used_swizzled_channel(f, dest_use_mask, true) + 1;
 
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   const unsigned first_trailing_unused_channel = first_used_swizzled_channel(f, dest_use_mask, true) + 1;
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   const unsigned max_loaded_channels = MIN2(first_trailing_unused_channel, f->nr_channels);
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   const unsigned fetch_num_channels =
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      first_used_channel >= max_loaded_channels ? 0 : max_loaded_channels - skipped_start;
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       * Note, NONE seems to occur in real use and is considered an array format.
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       */
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      if (f->is_array && fetch_format != PIPE_FORMAT_NONE) {
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         while (channels > 1 && attrib_stride &&
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                (const_off + count_format_bytes(f, start, channels)) > attrib_stride) {
 
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         while (channels > 1 && attrib_stride && (const_off + count_format_bytes(f, start, channels)) > attrib_stride) {
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            channels--;
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         }
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         /* Keep the fetch format as large as possible to let the backend emit
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          * larger load instructions when it deems them beneficial.
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          */
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         fetch_format =
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            util_format_get_array(f->channel[0].type, f->channel[0].size, f->nr_channels - start,
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                                  f->is_unorm || f->is_snorm, f->channel[0].pure_integer);
 
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         fetch_format = util_format_get_array(f->channel[0].type, f->channel[0].size, f->nr_channels - start,
 
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                                              f->is_unorm || f->is_snorm, f->channel[0].pure_integer);
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      }
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      assert(f->is_array || channels == fetch_num_channels);
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       * Typed loads can cause GPU hangs when used with improper alignment.
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       */
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      if (can_use_untyped_load(f, bit_size)) {
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         loads[num_loads++] =
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            nir_load_buffer_amd(b, channels, bit_size, descriptor, zero, zero, index,
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                                .base = const_off, .memory_modes = nir_var_shader_in);
 
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         loads[num_loads++] = nir_load_buffer_amd(b, channels, bit_size, descriptor, zero, zero, index,
 
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                                                  .base = const_off, .memory_modes = nir_var_shader_in);
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      } else {
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         const unsigned align_mul = MAX2(1, s->pl_key->vs.vertex_binding_align[attrib_binding]);
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         const unsigned align_offset = const_off % align_mul;
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         loads[num_loads++] = nir_load_typed_buffer_amd(
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            b, channels, bit_size, descriptor, zero, zero, index, .base = const_off,
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            .format = fetch_format, .align_mul = align_mul, .align_offset = align_offset,
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            .memory_modes = nir_var_shader_in);
 
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            b, channels, bit_size, descriptor, zero, zero, index, .base = const_off, .format = fetch_format,
 
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            .align_mul = align_mul, .align_offset = align_offset, .memory_modes = nir_var_shader_in);
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      }
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   }
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   nir_ssa_def *load = loads[0];
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   /* Extract the channels we actually need when we couldn't skip starting
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    * components or had to emit more than one load instrinsic.
 
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    * components or had to emit more than one load intrinsic.
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    */
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   if (num_loads > 0 && (first_used_channel > skipped_start || num_loads != 1))
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      load = nir_extract_bits(b, loads, num_loads, (first_used_channel - skipped_start) * bit_size,
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                              max_loaded_channels - first_used_channel, bit_size);
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   /* Return early if possible to avoid generating unnecessary IR. */
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   if (num_loads > 0 && first_used_channel == component &&
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       load->num_components == dest_num_components && !needs_swizzle &&
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       alpha_adjust == AC_ALPHA_ADJUST_NONE)
 
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   if (num_loads > 0 && first_used_channel == component && load->num_components == dest_num_components &&
 
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       !needs_swizzle && alpha_adjust == AC_ALPHA_ADJUST_NONE)
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      return load;
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   /* Fill unused and OOB components.
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      .rad_info = rad_info,
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   };
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   return nir_shader_instructions_pass(shader, lower_vs_input_instr,
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                                       nir_metadata_dominance | nir_metadata_block_index, &state);
 
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   return nir_shader_instructions_pass(shader, lower_vs_input_instr, nir_metadata_dominance | nir_metadata_block_index,
 
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                                       &state);
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}