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Viewing changes to src/gallium/drivers/nouveau/nv50/nv50_screen.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
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   case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
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   case PIPE_CAP_SUPPORTED_PRIM_MODES:
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      return BITFIELD_MASK(PIPE_PRIM_MAX);
 
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      return BITFIELD_MASK(MESA_PRIM_COUNT);
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   /* supported caps */
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   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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   case PIPE_CAP_DEPTH_BOUNDS_TEST:
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   case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
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   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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   case PIPE_CAP_CLEAR_TEXTURE:
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   case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
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   case PIPE_CAP_INVALIDATE_BUFFER:
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   case PIPE_CAP_STRING_MARKER:
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      return 1;
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   case PIPE_CAP_ALPHA_TEST:
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      /* nvc0 has fixed function alpha test support, but nv50 doesn't.  The TGSI
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       * backend emits the conditional discard code against a driver-uploaded
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       * uniform, but with NIR we can have the st emit it for us.
 
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      /* nvc0 has fixed function alpha test support, but nv50 doesn't.  If we
 
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       * don't have it, then the frontend will lower it for us.
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       */
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      return class_3d >= NVC0_3D_CLASS || !screen->prefer_nir;
 
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      return class_3d >= NVC0_3D_CLASS;
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   case PIPE_CAP_TEXTURE_TRANSFER_MODES:
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      return PIPE_TEXTURE_TRANSFER_BLIT;
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                             enum pipe_shader_type shader,
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                             enum pipe_shader_cap param)
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{
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   const struct nouveau_screen *screen = nouveau_screen(pscreen);
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   switch (shader) {
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   case PIPE_SHADER_VERTEX:
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   case PIPE_SHADER_GEOMETRY:
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      return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
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   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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      return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
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   case PIPE_SHADER_CAP_PREFERRED_IR:
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      return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
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   case PIPE_SHADER_CAP_SUPPORTED_IRS:
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      return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
 
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      return 1 << PIPE_SHADER_IR_NIR;
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   case PIPE_SHADER_CAP_DROUND_SUPPORTED:
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   case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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      RET((uint64_t []) { 16 << 10 });
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   case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
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      RET((uint64_t []) { 4096 });
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   case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 
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   case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
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      RET((uint32_t []) { 32 });
 
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   case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
 
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      RET((uint32_t []) { 0 });
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   case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
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      RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
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   case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
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}
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static void
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nv50_screen_fence_emit(struct pipe_context *pcontext, u32 *sequence)
 
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nv50_screen_fence_emit(struct pipe_context *pcontext, u32 *sequence,
 
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                       struct nouveau_bo *wait)
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{
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   struct nv50_context *nv50 = nv50_context(pcontext);
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   struct nv50_screen *screen = nv50->screen;
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   struct nouveau_pushbuf *push = nv50->base.pushbuf;
 
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   struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
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   /* we need to do it after possible flush in MARK_RING */
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   *sequence = ++screen->base.fence.sequence;
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                    NV50_3D_QUERY_GET_TYPE_QUERY |
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                    NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
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                    NV50_3D_QUERY_GET_SHORT);
 
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   nouveau_pushbuf_refn(push, &ref, 1);
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}
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static u32
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   PUSH_DATA (push, 1);
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   BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
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   PUSH_DATA (push, 1);
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   PUSH_KICK (push);
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}
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static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
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                                 enum pipe_shader_ir ir,
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                                 enum pipe_shader_type shader)
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{
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   struct nouveau_screen *screen = nouveau_screen(pscreen);
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   if (ir == PIPE_SHADER_IR_NIR)
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      return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader, screen->prefer_nir);
 
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      return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
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   return NULL;
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}
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      goto fail;
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   }
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   // submit all initial state
 
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   PUSH_KICK(screen->base.pushbuf);
 
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   return &screen->base;
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fail: