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Viewing changes to src/gallium/drivers/r600/r600_pipe.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/gallium/drivers/r600/r600_pipe.c
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        rctx->b.gfx.flush = r600_context_gfx_flush;
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        u_suballocator_init(&rctx->allocator_fetch_shader, &rctx->b.b, 64 * 1024,
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                            0, PIPE_USAGE_DEFAULT, 0, FALSE);
 
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                            0, PIPE_USAGE_DEFAULT, 0, false);
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        rctx->isa = calloc(1, sizeof(struct r600_isa));
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        if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
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        return NULL;
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}
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static bool is_nir_enabled(struct r600_common_screen *screen) {
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   return !(screen->debug_flags & DBG_USE_TGSI);
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}
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/*
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 * pipe_screen
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 */
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        case PIPE_CAP_QUERY_MEMORY_INFO:
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        case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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        case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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        case PIPE_CAP_CLEAR_TEXTURE:
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        case PIPE_CAP_LEGACY_MATH_RULES:
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        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
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        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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        case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
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        case PIPE_CAP_GL_SPIRV:
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                return is_nir_enabled(&rscreen->b);
 
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                return 1;
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        case PIPE_CAP_TEXTURE_TRANSFER_MODES:
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                return PIPE_TEXTURE_TRANSFER_BLIT;
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        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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                return 4;
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        case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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                if (!is_nir_enabled(&rscreen->b))
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                        return 140;
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                FALLTHROUGH;
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        case PIPE_CAP_GLSL_FEATURE_LEVEL:
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                if (family >= CHIP_CEDAR)
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                   return is_nir_enabled(&rscreen->b) ? 450 : 430;
 
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                   return 450;
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                return 330;
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        /* Supported except the original R600. */
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                    rscreen->b.family == CHIP_CYPRESS ||
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                    rscreen->b.family == CHIP_HEMLOCK)
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                        return 1;
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                if (is_nir_enabled(&rscreen->b) &&
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                        rscreen->b.family >= CHIP_CEDAR)
 
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                if (rscreen->b.family >= CHIP_CEDAR)
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                        return 1;
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                return 0;
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        case PIPE_CAP_TWO_SIDED_COLOR:
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                return !is_nir_enabled(&rscreen->b);
 
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                return 0;
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        case PIPE_CAP_INT64_DIVMOD:
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                /* it is actually not supported, but the nir lowering handles this corectly wheras
 
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                /* it is actually not supported, but the nir lowering handles this correctly whereas
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                 * the glsl lowering path seems to not initialize the buildins correctly.
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                 */
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                return is_nir_enabled(&rscreen->b);
 
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                return 1;
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        case PIPE_CAP_CULL_DISTANCE:
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                return 1;
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        case PIPE_CAP_QUERY_TIMESTAMP:
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                return rscreen->b.info.clock_crystal_freq != 0;
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        case PIPE_CAP_TIMER_RESOLUTION:
 
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                /* Conversion to nanos from cycles per millisecond */
 
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                return DIV_ROUND_UP(1000000, rscreen->b.info.clock_crystal_freq);
 
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        case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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        case PIPE_CAP_MIN_TEXEL_OFFSET:
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                return -8;
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        case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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                if (shader == PIPE_SHADER_COMPUTE) {
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                        uint64_t max_const_buffer_size;
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                        enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
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                                PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
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                        pscreen->get_compute_param(pscreen, ir_type,
 
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                        pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
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                                                   PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
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                                                   &max_const_buffer_size);
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                        return MIN2(max_const_buffer_size, INT_MAX);
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        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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                return 16;
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        case PIPE_SHADER_CAP_PREFERRED_IR:
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                if (rscreen->b.debug_flags & DBG_USE_TGSI)
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                        return PIPE_SHADER_IR_TGSI;
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                return PIPE_SHADER_IR_NIR;
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        case PIPE_SHADER_CAP_SUPPORTED_IRS: {
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                int ir = 0;
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                if (shader == PIPE_SHADER_COMPUTE)
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                        ir = 1 << PIPE_SHADER_IR_NATIVE;
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                ir |= 1 << PIPE_SHADER_IR_TGSI;
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                if (is_nir_enabled(&rscreen->b)) {
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                        ir |= 1 << PIPE_SHADER_IR_NIR;
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                }
 
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                ir |= 1 << PIPE_SHADER_IR_NIR;
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                return ir;
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        }
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        case PIPE_SHADER_CAP_DROUND_SUPPORTED:
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        }
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        rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
731
 
        if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 
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        if (debug_get_bool_option("R600_DEBUG_COMPUTE", false))
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                rscreen->b.debug_flags |= DBG_COMPUTE;
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        if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 
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        if (debug_get_bool_option("R600_DUMP_SHADERS", false))
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                rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
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        if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 
721
        if (!debug_get_bool_option("R600_HYPERZ", true))
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                rscreen->b.debug_flags |= DBG_NO_HYPERZ;
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        if (rscreen->b.family == CHIP_UNKNOWN) {
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                return NULL;
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        }
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   if (is_nir_enabled(&rscreen->b))
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       rscreen->b.b.finalize_nir = r600_finalize_nir;
 
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        rscreen->b.b.finalize_nir = r600_finalize_nir;
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        rscreen->b.has_streamout = true;
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