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Viewing changes to src/amd/vulkan/meta/radv_meta_dcc_retile.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/amd/vulkan/meta/radv_meta_dcc_retile.c
56
56
 
57
57
   nir_ssa_def *coord = get_global_ids(&b, 2);
58
58
   nir_ssa_def *zero = nir_imm_int(&b, 0);
59
 
   coord = nir_imul(
60
 
      &b, coord,
61
 
      nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
 
59
   coord =
 
60
      nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height));
62
61
 
63
 
   nir_ssa_def *src = ac_nir_dcc_addr_from_coord(&b, &dev->physical_device->rad_info, surf->bpe,
64
 
                                                 &surf->u.gfx9.color.dcc_equation, src_dcc_pitch,
65
 
                                                 src_dcc_height, zero, nir_channel(&b, coord, 0),
66
 
                                                 nir_channel(&b, coord, 1), zero, zero, zero);
 
62
   nir_ssa_def *src = ac_nir_dcc_addr_from_coord(
 
63
      &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.dcc_equation, src_dcc_pitch, src_dcc_height,
 
64
      zero, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero, zero);
67
65
   nir_ssa_def *dst = ac_nir_dcc_addr_from_coord(
68
 
      &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation,
69
 
      dst_dcc_pitch, dst_dcc_height, zero, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1),
70
 
      zero, zero, zero);
71
 
 
72
 
   nir_ssa_def *dcc_val = nir_image_deref_load(&b, 1, 32, input_dcc_ref,
73
 
                                               nir_vec4(&b, src, src, src, src),
74
 
                                               nir_ssa_undef(&b, 1, 32), nir_imm_int(&b, 0),
75
 
                                               .image_dim = dim);
76
 
 
77
 
   nir_image_deref_store(&b, output_dcc_ref, nir_vec4(&b, dst, dst, dst, dst),
78
 
                         nir_ssa_undef(&b, 1, 32), dcc_val, nir_imm_int(&b, 0), .image_dim = dim);
 
66
      &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, dst_dcc_pitch,
 
67
      dst_dcc_height, zero, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero, zero);
 
68
 
 
69
   nir_ssa_def *dcc_val = nir_image_deref_load(&b, 1, 32, input_dcc_ref, nir_vec4(&b, src, src, src, src),
 
70
                                               nir_ssa_undef(&b, 1, 32), nir_imm_int(&b, 0), .image_dim = dim);
 
71
 
 
72
   nir_image_deref_store(&b, output_dcc_ref, nir_vec4(&b, dst, dst, dst, dst), nir_ssa_undef(&b, 1, 32), dcc_val,
 
73
                         nir_imm_int(&b, 0), .image_dim = dim);
79
74
 
80
75
   return b.shader;
81
76
}
86
81
   struct radv_meta_state *state = &device->meta_state;
87
82
 
88
83
   for (unsigned i = 0; i < ARRAY_SIZE(state->dcc_retile.pipeline); i++) {
89
 
      radv_DestroyPipeline(radv_device_to_handle(device), state->dcc_retile.pipeline[i],
90
 
                           &state->alloc);
 
84
      radv_DestroyPipeline(radv_device_to_handle(device), state->dcc_retile.pipeline[i], &state->alloc);
91
85
   }
92
 
   radv_DestroyPipelineLayout(radv_device_to_handle(device), state->dcc_retile.p_layout,
93
 
                              &state->alloc);
94
 
   device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device),
95
 
                                                        state->dcc_retile.ds_layout, &state->alloc);
 
86
   radv_DestroyPipelineLayout(radv_device_to_handle(device), state->dcc_retile.p_layout, &state->alloc);
 
87
   device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device), state->dcc_retile.ds_layout,
 
88
                                                        &state->alloc);
96
89
 
97
90
   /* Reset for next finish. */
98
91
   memset(&state->dcc_retile, 0, sizeof(state->dcc_retile));
112
105
   VkResult result = VK_SUCCESS;
113
106
   nir_shader *cs = build_dcc_retile_compute_shader(device, surf);
114
107
 
115
 
   VkDescriptorSetLayoutCreateInfo ds_create_info = {
116
 
      .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
117
 
      .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
118
 
      .bindingCount = 2,
119
 
      .pBindings = (VkDescriptorSetLayoutBinding[]){
120
 
         {.binding = 0,
121
 
          .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
122
 
          .descriptorCount = 1,
123
 
          .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
124
 
          .pImmutableSamplers = NULL},
125
 
         {.binding = 1,
126
 
          .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
127
 
          .descriptorCount = 1,
128
 
          .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
129
 
          .pImmutableSamplers = NULL},
130
 
      }};
 
108
   VkDescriptorSetLayoutCreateInfo ds_create_info = {.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
 
109
                                                     .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
 
110
                                                     .bindingCount = 2,
 
111
                                                     .pBindings = (VkDescriptorSetLayoutBinding[]){
 
112
                                                        {.binding = 0,
 
113
                                                         .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
 
114
                                                         .descriptorCount = 1,
 
115
                                                         .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
 
116
                                                         .pImmutableSamplers = NULL},
 
117
                                                        {.binding = 1,
 
118
                                                         .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
 
119
                                                         .descriptorCount = 1,
 
120
                                                         .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
 
121
                                                         .pImmutableSamplers = NULL},
 
122
                                                     }};
131
123
 
132
 
   result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
133
 
                                           &device->meta_state.alloc,
 
124
   result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
134
125
                                           &device->meta_state.dcc_retile.ds_layout);
135
126
   if (result != VK_SUCCESS)
136
127
      goto cleanup;
143
134
      .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
144
135
   };
145
136
 
146
 
   result =
147
 
      radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
148
 
                                &device->meta_state.alloc, &device->meta_state.dcc_retile.p_layout);
 
137
   result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
 
138
                                      &device->meta_state.dcc_retile.p_layout);
149
139
   if (result != VK_SUCCESS)
150
140
      goto cleanup;
151
141
 
166
156
      .layout = device->meta_state.dcc_retile.p_layout,
167
157
   };
168
158
 
169
 
   result = radv_compute_pipeline_create(
170
 
      radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info, NULL,
171
 
      &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
 
159
   result = radv_compute_pipeline_create(radv_device_to_handle(device), device->meta_state.cache, &vk_pipeline_info,
 
160
                                         NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]);
172
161
   if (result != VK_SUCCESS)
173
162
      goto cleanup;
174
163
 
185
174
   struct radv_buffer buffer;
186
175
 
187
176
   assert(image->vk.image_type == VK_IMAGE_TYPE_2D);
188
 
   assert(image->info.array_size == 1 && image->info.levels == 1);
 
177
   assert(image->vk.array_layers == 1 && image->vk.mip_levels == 1);
189
178
 
190
179
   struct radv_cmd_state *state = &cmd_buffer->state;
191
180
 
196
185
 
197
186
   /* Compile pipelines if not already done so. */
198
187
   if (!cmd_buffer->device->meta_state.dcc_retile.pipeline[swizzle_mode]) {
199
 
      VkResult ret =
200
 
         radv_device_init_meta_dcc_retile_state(cmd_buffer->device, &image->planes[0].surface);
 
188
      VkResult ret = radv_device_init_meta_dcc_retile_state(cmd_buffer->device, &image->planes[0].surface);
201
189
      if (ret != VK_SUCCESS) {
202
190
         vk_command_buffer_set_error(&cmd_buffer->vk, ret);
203
191
         return;
204
192
      }
205
193
   }
206
194
 
207
 
   radv_meta_save(
208
 
      &saved_state, cmd_buffer,
209
 
      RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
 
195
   radv_meta_save(&saved_state, cmd_buffer,
 
196
                  RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
210
197
 
211
198
   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
212
199
                        device->meta_state.dcc_retile.pipeline[swizzle_mode]);
234
221
   for (unsigned i = 0; i < 2; ++i)
235
222
      view_handles[i] = radv_buffer_view_to_handle(&views[i]);
236
223
 
237
 
   radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
238
 
                                 device->meta_state.dcc_retile.p_layout, 0, /* set */
 
224
   radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.dcc_retile.p_layout,
 
225
                                 0, /* set */
239
226
                                 2, /* descriptorWriteCount */
240
227
                                 (VkWriteDescriptorSet[]){
241
228
                                    {
256
243
                                    },
257
244
                                 });
258
245
 
259
 
   unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk.format));
260
 
   unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk.format));
 
246
   unsigned width = DIV_ROUND_UP(image->vk.extent.width, vk_format_get_blockwidth(image->vk.format));
 
247
   unsigned height = DIV_ROUND_UP(image->vk.extent.height, vk_format_get_blockheight(image->vk.format));
261
248
 
262
249
   unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
263
 
   unsigned dcc_height =
264
 
      DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
 
250
   unsigned dcc_height = DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
265
251
 
266
252
   uint32_t constants[] = {
267
253
      image->planes[0].surface.u.gfx9.color.dcc_pitch_max + 1,
269
255
      image->planes[0].surface.u.gfx9.color.display_dcc_pitch_max + 1,
270
256
      image->planes[0].surface.u.gfx9.color.display_dcc_height,
271
257
   };
272
 
   radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
273
 
                         device->meta_state.dcc_retile.p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
274
 
                         constants);
 
258
   radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.dcc_retile.p_layout,
 
259
                         VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants);
275
260
 
276
261
   radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, 1);
277
262
 
281
266
 
282
267
   radv_meta_restore(&saved_state, cmd_buffer);
283
268
 
284
 
   state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
285
 
                        radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
 
269
   state->flush_bits |=
 
270
      RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
286
271
}