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#include "virgl_encode.h"
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int virgl_debug = 0;
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static const struct debug_named_value virgl_debug_options[] = {
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{ "verbose", VIRGL_DEBUG_VERBOSE, NULL },
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{ "tgsi", VIRGL_DEBUG_TGSI, NULL },
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{ "use_tgsi", VIRGL_DEBUG_USE_TGSI, NULL },
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{ "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA, "Disable tweak to emulate BGRA as RGBA on GLES hosts"},
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{ "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" },
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{ "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" },
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{ "xfer", VIRGL_DEBUG_XFER, "Do not optimize for transfers" },
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{ "r8srgb-readback", VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" },
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{ "nocoherent", VIRGL_DEBUG_NO_COHERENT, "Disable coherent memory"},
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{ "video", VIRGL_DEBUG_VIDEO, "Video codec"},
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const struct debug_named_value virgl_debug_options[] = {
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{ "verbose", VIRGL_DEBUG_VERBOSE, NULL },
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{ "tgsi", VIRGL_DEBUG_TGSI, NULL },
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{ "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA, "Disable tweak to emulate BGRA as RGBA on GLES hosts" },
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{ "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE, "Disable tweak to swizzle emulated BGRA on GLES hosts" },
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{ "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" },
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{ "xfer", VIRGL_DEBUG_XFER, "Do not optimize for transfers" },
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{ "r8srgb-readback", VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" },
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{ "nocoherent", VIRGL_DEBUG_NO_COHERENT, "Disable coherent memory" },
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{ "video", VIRGL_DEBUG_VIDEO, "Video codec" },
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{ "shader_sync", VIRGL_DEBUG_SHADER_SYNC, "Sync after every shader link" },
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DEBUG_NAMED_VALUE_END
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DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0)
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case PIPE_CAP_OCCLUSION_QUERY:
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return vscreen->caps.caps.v1.bset.occlusion_query;
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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return vscreen->caps.caps.v1.bset.mirror_clamp &&
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vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES ? 0 : 1;
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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return vscreen->caps.caps.v1.bset.mirror_clamp;
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case PIPE_CAP_TEXTURE_SWIZZLE:
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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case PIPE_CAP_SUPPORTED_PRIM_MODES:
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return BITFIELD_MASK(PIPE_PRIM_MAX) &
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~BITFIELD_BIT(PIPE_PRIM_QUADS) &
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~BITFIELD_BIT(PIPE_PRIM_QUAD_STRIP);
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return BITFIELD_MASK(MESA_PRIM_COUNT) &
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~BITFIELD_BIT(MESA_PRIM_QUADS) &
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~BITFIELD_BIT(MESA_PRIM_QUAD_STRIP);
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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return vscreen->caps.caps.v1.bset.primitive_restart;
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case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
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return vscreen->caps.caps.v1.max_tbo_size;
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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case PIPE_CAP_ENDIANNESS:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_ENDIANNESS:
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return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_PIPELINE_STATISTICS_QUERY);
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER;
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case PIPE_CAP_SURFACE_SAMPLE_COUNT:
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return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
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case PIPE_CAP_DRAW_PARAMETERS:
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return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_DRAW_PARAMETERS);
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case PIPE_CAP_SHADER_GROUP_VOTE:
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return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_GROUP_VOTE);
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case PIPE_CAP_IMAGE_STORE_FORMATTED:
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case PIPE_CAP_GL_SPIRV:
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case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
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if (vscreen->caps.caps.v2.host_feature_check_version >= 13)
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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if ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES) &&
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(shader == PIPE_SHADER_VERTEX)) {
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case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
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return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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if (vscreen->caps.caps.v1.glsl_level < 150)
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return vscreen->caps.caps.v2.max_shader_image_frag_compute;
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return vscreen->caps.caps.v2.max_shader_image_other_stages;
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case PIPE_SHADER_CAP_PREFERRED_IR:
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return (virgl_debug & VIRGL_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
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case PIPE_SHADER_CAP_SUPPORTED_IRS:
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return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_USE_TGSI) ? 0 : (1 << PIPE_SHADER_IR_NIR));
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return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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return VIRGL_SHADER_STAGE_CAP_V2(max_atomic_counters, shader);
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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const struct util_format_description *format_desc;
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union virgl_caps *caps = &vscreen->caps.caps;
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boolean may_emulate_bgra = (caps->v2.capability_bits &
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VIRGL_CAP_APP_TWEAK_SUPPORT) &&
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vscreen->tweak_gles_emulate_bgra;
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union virgl_caps *caps = &vscreen->caps.caps;
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bool may_emulate_bgra = (caps->v2.capability_bits &
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VIRGL_CAP_APP_TWEAK_SUPPORT) &&
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vscreen->tweak_gles_emulate_bgra;
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if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
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_mesa_sha1_init(&sha1_ctx);
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_mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len);
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uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_USE_TGSI;
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_mesa_sha1_update(&sha1_ctx, &shader_debug_flags, sizeof(shader_debug_flags));
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/* When we switch the host the caps might change and then we might have to
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* apply different lowering. */
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_mesa_sha1_update(&sha1_ctx, &screen->caps, sizeof(screen->caps));
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driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
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screen->tweak_l8_srgb_readback =
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driQueryOptionb(config->options, VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK);
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screen->shader_sync = driQueryOptionb(config->options, VIRGL_SHADER_SYNC);
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screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
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screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
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screen->no_coherent = virgl_debug & VIRGL_DEBUG_NO_COHERENT;
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screen->tweak_l8_srgb_readback |= !!(virgl_debug & VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK);
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screen->shader_sync |= !!(virgl_debug & VIRGL_DEBUG_SHADER_SYNC);
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screen->vws = vws;
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screen->base.get_name = virgl_get_name;