~mmach/netext73/mesa-ryzen

« back to all changes in this revision

Viewing changes to src/gallium/drivers/virgl/virgl_screen.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

Show diffs side-by-side

added added

removed removed

Lines of Context:
35
35
#include "vl/vl_decoder.h"
36
36
#include "vl/vl_video_buffer.h"
37
37
 
38
 
#include "tgsi/tgsi_exec.h"
39
 
 
40
38
#include "virgl_screen.h"
41
39
#include "virgl_resource.h"
42
40
#include "virgl_public.h"
44
42
#include "virgl_encode.h"
45
43
 
46
44
int virgl_debug = 0;
47
 
static const struct debug_named_value virgl_debug_options[] = {
48
 
   { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
49
 
   { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
50
 
   { "use_tgsi",  VIRGL_DEBUG_USE_TGSI,            NULL },
51
 
   { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA,     "Disable tweak to emulate BGRA as RGBA on GLES hosts"},
52
 
   { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" },
53
 
   { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
54
 
   { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
55
 
   { "r8srgb-readback",   VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" },
56
 
   { "nocoherent", VIRGL_DEBUG_NO_COHERENT,        "Disable coherent memory"},
57
 
   { "video",     VIRGL_DEBUG_VIDEO,               "Video codec"},
 
45
const struct debug_named_value virgl_debug_options[] = {
 
46
   { "verbose",         VIRGL_DEBUG_VERBOSE,                 NULL },
 
47
   { "tgsi",            VIRGL_DEBUG_TGSI,                    NULL },
 
48
   { "noemubgra",       VIRGL_DEBUG_NO_EMULATE_BGRA,         "Disable tweak to emulate BGRA as RGBA on GLES hosts" },
 
49
   { "nobgraswz",       VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,    "Disable tweak to swizzle emulated BGRA on GLES hosts" },
 
50
   { "sync",            VIRGL_DEBUG_SYNC,                    "Sync after every flush" },
 
51
   { "xfer",            VIRGL_DEBUG_XFER,                    "Do not optimize for transfers" },
 
52
   { "r8srgb-readback", VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" },
 
53
   { "nocoherent",      VIRGL_DEBUG_NO_COHERENT,             "Disable coherent memory" },
 
54
   { "video",           VIRGL_DEBUG_VIDEO,                   "Video codec" },
 
55
   { "shader_sync",     VIRGL_DEBUG_SHADER_SYNC,             "Sync after every shader link" },
58
56
   DEBUG_NAMED_VALUE_END
59
57
};
60
58
DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0)
95
93
   case PIPE_CAP_OCCLUSION_QUERY:
96
94
      return vscreen->caps.caps.v1.bset.occlusion_query;
97
95
   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 
96
      return vscreen->caps.caps.v1.bset.mirror_clamp &&
 
97
      vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES ? 0 : 1;
98
98
   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
99
99
      return vscreen->caps.caps.v1.bset.mirror_clamp;
100
100
   case PIPE_CAP_TEXTURE_SWIZZLE:
133
133
   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
134
134
      return 16*4;
135
135
   case PIPE_CAP_SUPPORTED_PRIM_MODES:
136
 
      return BITFIELD_MASK(PIPE_PRIM_MAX) &
137
 
            ~BITFIELD_BIT(PIPE_PRIM_QUADS) &
138
 
            ~BITFIELD_BIT(PIPE_PRIM_QUAD_STRIP);
 
136
      return BITFIELD_MASK(MESA_PRIM_COUNT) &
 
137
            ~BITFIELD_BIT(MESA_PRIM_QUADS) &
 
138
            ~BITFIELD_BIT(MESA_PRIM_QUAD_STRIP);
139
139
   case PIPE_CAP_PRIMITIVE_RESTART:
140
140
   case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
141
141
      return vscreen->caps.caps.v1.bset.primitive_restart;
222
222
   case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
223
223
      return vscreen->caps.caps.v1.max_tbo_size;
224
224
   case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 
225
   case PIPE_CAP_ENDIANNESS:
 
226
      return 0;
225
227
   case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
226
 
   case PIPE_CAP_ENDIANNESS:
227
 
      return 0;
 
228
      return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_PIPELINE_STATISTICS_QUERY);
228
229
   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
229
230
   case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
230
231
      return 1;
318
319
   case PIPE_CAP_PCI_FUNCTION:
319
320
   case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
320
321
      return 0;
321
 
   case PIPE_CAP_CLEAR_TEXTURE:
322
 
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
323
322
   case PIPE_CAP_CLIP_HALFZ:
324
323
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
325
324
   case PIPE_CAP_MAX_GS_INVOCATIONS:
355
354
       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER;
356
355
   case PIPE_CAP_SURFACE_SAMPLE_COUNT:
357
356
       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
 
357
   case PIPE_CAP_DRAW_PARAMETERS:
 
358
      return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_DRAW_PARAMETERS);
 
359
   case PIPE_CAP_SHADER_GROUP_VOTE:
 
360
      return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_GROUP_VOTE);
358
361
   case PIPE_CAP_IMAGE_STORE_FORMATTED:
 
362
   case PIPE_CAP_GL_SPIRV:
359
363
      return 1;
360
364
   case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
361
365
      if (vscreen->caps.caps.v2.host_feature_check_version >= 13)
402
406
      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
403
407
      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
404
408
         return 1;
 
409
      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 
410
         if ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES) &&
 
411
             (shader == PIPE_SHADER_VERTEX)) {
 
412
            return 0;
 
413
         }
 
414
         FALLTHROUGH;
405
415
      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
406
 
      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
407
416
         return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
408
417
      case PIPE_SHADER_CAP_MAX_INPUTS:
409
418
         if (vscreen->caps.caps.v1.glsl_level < 150)
445
454
            return vscreen->caps.caps.v2.max_shader_image_frag_compute;
446
455
         else
447
456
            return vscreen->caps.caps.v2.max_shader_image_other_stages;
448
 
      case PIPE_SHADER_CAP_PREFERRED_IR:
449
 
         return (virgl_debug & VIRGL_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
450
457
      case PIPE_SHADER_CAP_SUPPORTED_IRS:
451
 
         return (1 << PIPE_SHADER_IR_TGSI) | ((virgl_debug & VIRGL_DEBUG_USE_TGSI) ? 0 : (1 << PIPE_SHADER_IR_NIR));
 
458
         return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
452
459
      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
453
460
         return VIRGL_SHADER_STAGE_CAP_V2(max_atomic_counters, shader);
454
461
      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
746
753
   const struct util_format_description *format_desc;
747
754
   int i;
748
755
 
749
 
   union virgl_caps *caps = &vscreen->caps.caps; 
750
 
   boolean may_emulate_bgra = (caps->v2.capability_bits &
751
 
                               VIRGL_CAP_APP_TWEAK_SUPPORT) &&
752
 
                               vscreen->tweak_gles_emulate_bgra;
 
756
   union virgl_caps *caps = &vscreen->caps.caps;
 
757
   bool may_emulate_bgra = (caps->v2.capability_bits &
 
758
                            VIRGL_CAP_APP_TWEAK_SUPPORT) &&
 
759
                            vscreen->tweak_gles_emulate_bgra;
753
760
 
754
761
   if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
755
762
      return false;
814
821
   if (bind & PIPE_BIND_RENDER_TARGET) {
815
822
      /* For ARB_framebuffer_no_attachments. */
816
823
      if (format == PIPE_FORMAT_NONE)
817
 
         return TRUE;
 
824
         return true;
818
825
 
819
826
      if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
820
827
         return false;
1037
1044
   _mesa_sha1_init(&sha1_ctx);
1038
1045
   _mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len);
1039
1046
 
1040
 
   uint32_t shader_debug_flags = virgl_debug & VIRGL_DEBUG_USE_TGSI;
1041
 
   _mesa_sha1_update(&sha1_ctx, &shader_debug_flags, sizeof(shader_debug_flags));
1042
 
 
1043
1047
   /* When we switch the host the caps might change and then we might have to
1044
1048
    * apply different lowering. */
1045
1049
   _mesa_sha1_update(&sha1_ctx, &screen->caps, sizeof(screen->caps));
1122
1126
   const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
1123
1127
   const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
1124
1128
   const char *VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK = "format_l8_srgb_enable_readback";
 
1129
   const char *VIRGL_SHADER_SYNC = "virgl_shader_sync";
1125
1130
 
1126
1131
   if (!screen)
1127
1132
      return NULL;
1140
1145
            driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
1141
1146
      screen->tweak_l8_srgb_readback =
1142
1147
            driQueryOptionb(config->options, VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK);
 
1148
      screen->shader_sync = driQueryOptionb(config->options, VIRGL_SHADER_SYNC);
1143
1149
   }
1144
1150
   screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
1145
1151
   screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
1146
1152
   screen->no_coherent = virgl_debug & VIRGL_DEBUG_NO_COHERENT;
1147
1153
   screen->tweak_l8_srgb_readback |= !!(virgl_debug & VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK);
 
1154
   screen->shader_sync |= !!(virgl_debug & VIRGL_DEBUG_SHADER_SYNC);
1148
1155
 
1149
1156
   screen->vws = vws;
1150
1157
   screen->base.get_name = virgl_get_name;