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Viewing changes to src/amd/compiler/tests/test_regalloc.cpp

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/amd/compiler/tests/test_regalloc.cpp
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   /* TODO: is this possible to do on GFX11? */
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   for (amd_gfx_level cc = GFX8; cc <= GFX10_3; cc = (amd_gfx_level)((unsigned)cc + 1)) {
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      for (bool pessimistic : { false, true }) {
 
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      for (bool pessimistic : {false, true}) {
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         const char* subvariant = pessimistic ? "/pessimistic" : "/optimistic";
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         //>> v1: %_:v[#a] = p_startpgm
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            return;
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         //! v2b: %_:v[#a][0:16], v2b: %res1:v[#a][16:32] = p_split_vector %_:v[#a]
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         Builder::Result tmp = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]);
 
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         Builder::Result tmp =
 
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            bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]);
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         //! v1: %_:v[#b] = v_cvt_f32_f16 %_:v[#a][16:32] dst_sel:dword src0_sel:uword1
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         //! v1: %_:v[#a] = v_cvt_f32_f16 %_:v[#a][0:16]
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         writeout(0, result1);
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         writeout(1, result2);
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         finish_ra_test(ra_test_policy { pessimistic });
 
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         finish_ra_test(ra_test_policy{pessimistic});
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      }
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   }
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END_TEST
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BEGIN_TEST(regalloc.32bit_partial_write)
 
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BEGIN_TEST(regalloc._32bit_partial_write)
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   //>> v1: %_:v[0] = p_startpgm
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   if (!setup_cs("v1", GFX10))
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      return;
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   /* ensure high 16 bits are occupied */
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   //! v2b: %_:v[0][0:16], v2b: %_:v[0][16:32] = p_split_vector %_:v[0]
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   Temp hi = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]).def(1).getTemp();
 
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   Temp hi =
 
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      bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]).def(1).getTemp();
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   /* This test checks if this instruction uses SDWA. */
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   //! v2b: %_:v[0][0:16] = v_not_b32 0 dst_sel:uword0 dst_preserve src0_sel:dword
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   //! v1: %tmp3_2:v[0], v1: %tmp0_2:v[1], v1: %tmp1_2:v[2], v1: %tmp2_2:v[3] = p_parallelcopy %tmp3:v[3], %tmp0:v[0], %tmp1:v[1], %tmp2:v[2]
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   //! p_unit_test %tmp3_2:v[0], %tmp0_2:v[1], %tmp1_2:v[2], %tmp2_2:v[3]
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   bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[3], PhysReg(256+0)),
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              Operand(inputs[0], PhysReg(256+1)), Operand(inputs[1], PhysReg(256+2)),
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              Operand(inputs[2], PhysReg(256+3)));
 
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   bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[3], PhysReg(256 + 0)),
 
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              Operand(inputs[0], PhysReg(256 + 1)), Operand(inputs[1], PhysReg(256 + 2)),
 
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              Operand(inputs[2], PhysReg(256 + 3)));
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   finish_ra_test(ra_test_policy());
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END_TEST
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   //! v1: %tmp1:v[1], v1: %tmp2:v[2] = p_parallelcopy %tmp0:v[0], %tmp0:v[0]
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   //! p_unit_test %tmp0:v[0], %tmp1:v[1], %tmp2:v[2]
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   bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0], PhysReg(256+0)),
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              Operand(inputs[0], PhysReg(256+1)), Operand(inputs[0], PhysReg(256+2)));
 
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   bld.pseudo(aco_opcode::p_unit_test, Operand(inputs[0], PhysReg(256 + 0)),
 
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              Operand(inputs[0], PhysReg(256 + 1)), Operand(inputs[0], PhysReg(256 + 2)));
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   finish_ra_test(ra_test_policy());
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END_TEST
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   //! s1: %scc_tmp:scc, s1: %1:s[0] = p_unit_test
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   Temp s0_tmp = bld.tmp(s1);
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   Temp scc_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(s1, scc), Definition(s0_tmp.id(), PhysReg{0}, s1));
 
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   Temp scc_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(s1, scc),
 
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                             Definition(s0_tmp.id(), PhysReg{0}, s1));
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   //! lv1: %tmp1:v[1] = p_unit_test
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   Temp tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1.as_linear(), reg_v1));
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   //>> lv1: %5:v[2] = p_parallelcopy %3:v[1] scc:1 scratch:s1
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   Pseudo_instruction& parallelcopy = program->blocks[0].instructions[3]->pseudo();
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   aco_print_instr(program->gfx_level, &parallelcopy, output);
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   fprintf(output, " scc:%u scratch:s%u\n", parallelcopy.tmp_in_scc, parallelcopy.scratch_sgpr.reg());
 
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   fprintf(output, " scc:%u scratch:s%u\n", parallelcopy.tmp_in_scc,
 
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           parallelcopy.scratch_sgpr.reg());
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END_TEST
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BEGIN_TEST(regalloc.linear_vgpr.live_range_split.get_regs_for_copies)
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   //! v1: %tmp0:v[1] = v_interp_p10_f16_f32_inreg %lo:v[3][0:16], %in1:v[1], hi(%hi:v[3][16:32])
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   //! p_unit_test %tmp0:v[1]
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   Temp tmp0 = bld.vinterp_inreg(aco_opcode::v_interp_p10_f16_f32_inreg, bld.def(v1), lo, inputs[1], hi);
 
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   Temp tmp0 =
 
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      bld.vinterp_inreg(aco_opcode::v_interp_p10_f16_f32_inreg, bld.def(v1), lo, inputs[1], hi);
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   bld.pseudo(aco_opcode::p_unit_test, tmp0);
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   //! v2b: %tmp1:v[0][16:32] = v_interp_p2_f16_f32_inreg %in0:v[0], %in2:v[2], %tmp0:v[1] opsel_hi
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   //! v1: %tmp2:v[0] = p_create_vector 0, %tmp1:v[0][16:32]
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   //! p_unit_test %tmp2:v[0]
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   Temp tmp1 = bld.vinterp_inreg(aco_opcode::v_interp_p2_f16_f32_inreg, bld.def(v2b), inputs[0], inputs[2], tmp0);
 
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   Temp tmp1 = bld.vinterp_inreg(aco_opcode::v_interp_p2_f16_f32_inreg, bld.def(v2b), inputs[0],
 
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                                 inputs[2], tmp0);
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   Temp tmp2 = bld.pseudo(aco_opcode::p_create_vector, bld.def(v1), Operand::zero(2), tmp1);
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   bld.pseudo(aco_opcode::p_unit_test, tmp2);
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