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Viewing changes to src/broadcom/compiler/v3d40_tex.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/broadcom/compiler/v3d40_tex.c
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}
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static uint32_t
 
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v3d40_image_atomic_tmu_op(nir_intrinsic_instr *instr)
 
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{
 
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        nir_atomic_op atomic_op = nir_intrinsic_atomic_op(instr);
 
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        switch (atomic_op) {
 
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        case nir_atomic_op_iadd:    return v3d_get_op_for_atomic_add(instr, 3);
 
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        case nir_atomic_op_imin:    return V3D_TMU_OP_WRITE_SMIN;
 
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        case nir_atomic_op_umin:    return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
 
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        case nir_atomic_op_imax:    return V3D_TMU_OP_WRITE_SMAX;
 
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        case nir_atomic_op_umax:    return V3D_TMU_OP_WRITE_UMAX;
 
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        case nir_atomic_op_iand:    return V3D_TMU_OP_WRITE_AND_READ_INC;
 
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        case nir_atomic_op_ior:     return V3D_TMU_OP_WRITE_OR_READ_DEC;
 
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        case nir_atomic_op_ixor:    return V3D_TMU_OP_WRITE_XOR_READ_NOT;
 
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        case nir_atomic_op_xchg:    return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
 
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        case nir_atomic_op_cmpxchg: return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
 
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        default:                    unreachable("unknown atomic op");
 
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        }
 
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}
 
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static uint32_t
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v3d40_image_load_store_tmu_op(nir_intrinsic_instr *instr)
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{
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        switch (instr->intrinsic) {
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        case nir_intrinsic_image_load:
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        case nir_intrinsic_image_store:
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                return V3D_TMU_OP_REGULAR;
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        case nir_intrinsic_image_atomic_add:
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                return v3d_get_op_for_atomic_add(instr, 3);
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        case nir_intrinsic_image_atomic_imin:
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                return V3D_TMU_OP_WRITE_SMIN;
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        case nir_intrinsic_image_atomic_umin:
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                return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
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        case nir_intrinsic_image_atomic_imax:
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                return V3D_TMU_OP_WRITE_SMAX;
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        case nir_intrinsic_image_atomic_umax:
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                return V3D_TMU_OP_WRITE_UMAX;
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        case nir_intrinsic_image_atomic_and:
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                return V3D_TMU_OP_WRITE_AND_READ_INC;
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        case nir_intrinsic_image_atomic_or:
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                return V3D_TMU_OP_WRITE_OR_READ_DEC;
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        case nir_intrinsic_image_atomic_xor:
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                return V3D_TMU_OP_WRITE_XOR_READ_NOT;
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        case nir_intrinsic_image_atomic_exchange:
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                return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
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        case nir_intrinsic_image_atomic_comp_swap:
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                return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
 
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        case nir_intrinsic_image_atomic:
 
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        case nir_intrinsic_image_atomic_swap:
 
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                return v3d40_image_atomic_tmu_op(instr);
 
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        default:
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                unreachable("unknown image intrinsic");
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        };
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                }
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                /* Second atomic argument */
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                if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap) {
 
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                if (instr->intrinsic == nir_intrinsic_image_atomic_swap &&
 
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                    nir_intrinsic_atomic_op(instr) == nir_atomic_op_cmpxchg) {
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                        struct qreg src_4_0 = ntq_get_src(c, instr->src[4], 0);
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                        vir_TMU_WRITE_or_count(c, V3D_QPU_WADDR_TMUD, src_4_0,
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                                               tmu_writes);
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         * amount to add/sub, as that is implicit.
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         */
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        bool atomic_add_replaced =
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                (instr->intrinsic == nir_intrinsic_image_atomic_add &&
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                 (p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
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                  p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC));
 
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                instr->intrinsic == nir_intrinsic_image_atomic &&
 
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                nir_intrinsic_atomic_op(instr) == nir_atomic_op_iadd &&
 
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                (p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
 
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                 p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC);
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        uint32_t p0_packed;
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        V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,