313
315
bucket_for_size(struct iris_bufmgr *bufmgr, uint64_t size,
314
316
enum iris_heap heap, unsigned flags)
317
/* Protected bo needs special handling during allocation.
318
* Exported and scanout bos also need special handling during allocation
321
if ((flags & BO_ALLOC_PROTECTED) ||
322
((flags & (BO_ALLOC_SHARED | BO_ALLOC_SCANOUT)) &&
323
bufmgr->devinfo.kmd_type == INTEL_KMD_TYPE_XE))
318
if (flags & BO_ALLOC_PROTECTED)
321
const struct intel_device_info *devinfo = &bufmgr->devinfo;
322
if (devinfo->has_set_pat_uapi &&
323
iris_pat_index_for_bo_flags(devinfo, flags) != devinfo->pat.writeback)
326
if (devinfo->kmd_type == INTEL_KMD_TYPE_XE &&
327
(flags & (BO_ALLOC_SHARED | BO_ALLOC_SCANOUT)))
326
330
/* Calculating the pages and rounding up to the page size. */
442
446
util_vma_heap_free(&bufmgr->vma_allocator[memzone], address, size);
449
/* Exports a BO's implicit synchronization state to a drm_syncobj, returning
450
* its wrapping iris_syncobj. The drm_syncobj is created new and has to be
451
* destroyed by the caller after the execbuf ioctl.
453
struct iris_syncobj *
454
iris_bo_export_sync_state(struct iris_bo *bo)
456
struct iris_bufmgr *bufmgr = bo->bufmgr;
457
int drm_fd = iris_bufmgr_get_fd(bufmgr);
459
struct iris_syncobj *iris_syncobj = iris_create_syncobj(bufmgr);
461
struct dma_buf_export_sync_file export_sync_file_ioctl = {
462
.flags = DMA_BUF_SYNC_RW, /* TODO */
465
if (intel_ioctl(bo->real.prime_fd, DMA_BUF_IOCTL_EXPORT_SYNC_FILE,
466
&export_sync_file_ioctl)) {
467
fprintf(stderr, "DMA_BUF_IOCTL_EXPORT_SYNC_FILE ioctl failed (%d)\n",
472
int sync_file_fd = export_sync_file_ioctl.fd;
473
assert(sync_file_fd >= 0);
475
struct drm_syncobj_handle syncobj_import_ioctl = {
476
.handle = iris_syncobj->handle,
477
.flags = DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE,
480
if (intel_ioctl(drm_fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE,
481
&syncobj_import_ioctl)) {
482
fprintf(stderr, "DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE ioctl failed (%d)\n",
490
iris_syncobj_destroy(bufmgr, iris_syncobj);
494
/* Import the state of a sync_file_fd (which we should have gotten from
495
* batch_syncobj_to_sync_file_fd) into a BO as its implicit synchronization
499
iris_bo_import_sync_state(struct iris_bo *bo, int sync_file_fd)
501
struct dma_buf_import_sync_file import_sync_file_ioctl = {
502
.flags = DMA_BUF_SYNC_WRITE,
505
if (intel_ioctl(bo->real.prime_fd, DMA_BUF_IOCTL_IMPORT_SYNC_FILE,
506
&import_sync_file_ioctl))
507
fprintf(stderr, "DMA_BUF_IOCTL_IMPORT_SYNC_FILE ioctl failed (%d)\n",
445
511
/* A timeout of 0 just checks for busyness. */
447
513
iris_bo_wait_syncobj(struct iris_bo *bo, int64_t timeout_ns)
450
516
struct iris_bufmgr *bufmgr = bo->bufmgr;
517
const bool is_external = iris_bo_is_real(bo) && bo->real.prime_fd != -1;
518
struct iris_syncobj *external_implicit_syncobj = NULL;
452
/* If we know it's idle, don't bother with the kernel round trip */
520
/* If we know it's idle, don't bother with the kernel round trip.
521
* Can't do that for Xe KMD with external BOs since we have to check the
522
* implicit synchronization information.
524
if (!is_external && bo->idle)
456
527
simple_mtx_lock(&bufmgr->bo_deps_lock);
458
uint32_t handles[bo->deps_size * IRIS_BATCH_COUNT * 2];
529
const int handles_len = bo->deps_size * IRIS_BATCH_COUNT * 2 + is_external;
530
uint32_t *handles = handles_len <= 32 ?
531
(uint32_t *)alloca(handles_len * sizeof(*handles)) :
532
(uint32_t *)malloc(handles_len * sizeof(*handles));
459
533
int handle_count = 0;
536
external_implicit_syncobj = iris_bo_export_sync_state(bo);
537
if (external_implicit_syncobj)
538
handles[handle_count++] = external_implicit_syncobj->handle;
461
541
for (int d = 0; d < bo->deps_size; d++) {
462
542
for (int b = 0; b < IRIS_BATCH_COUNT; b++) {
463
543
struct iris_syncobj *r = bo->deps[d].read_syncobjs[b];
1061
1146
[IRIS_HEAP_DEVICE_LOCAL_PREFERRED] = "local-preferred",
1149
static enum iris_mmap_mode
1150
iris_bo_alloc_get_mmap_mode(struct iris_bufmgr *bufmgr, enum iris_heap heap,
1153
if (bufmgr->devinfo.kmd_type == INTEL_KMD_TYPE_XE)
1154
return iris_xe_bo_flags_to_mmap_mode(bufmgr, heap, flags);
1157
const bool local = heap != IRIS_HEAP_SYSTEM_MEMORY;
1158
const bool is_coherent = bufmgr->devinfo.has_llc ||
1159
(bufmgr->vram.size > 0 && !local) ||
1160
(flags & BO_ALLOC_COHERENT);
1161
const bool is_scanout = (flags & BO_ALLOC_SCANOUT) != 0;
1162
enum iris_mmap_mode mmap_mode;
1164
if (!intel_vram_all_mappable(&bufmgr->devinfo) && heap == IRIS_HEAP_DEVICE_LOCAL)
1165
mmap_mode = IRIS_MMAP_NONE;
1166
else if (!local && is_coherent && !is_scanout)
1167
mmap_mode = IRIS_MMAP_WB;
1169
mmap_mode = IRIS_MMAP_WC;
1064
1174
struct iris_bo *
1065
1175
iris_bo_alloc(struct iris_bufmgr *bufmgr,
1066
1176
const char *name,
1089
1198
uint64_t bo_size =
1090
1199
bucket ? bucket->size : MAX2(ALIGN(size, page_size), page_size);
1092
bool is_coherent = bufmgr->devinfo.has_llc ||
1093
(bufmgr->vram.size > 0 && !local) ||
1094
(flags & BO_ALLOC_COHERENT);
1095
bool is_scanout = (flags & BO_ALLOC_SCANOUT) != 0;
1097
enum iris_mmap_mode mmap_mode;
1098
if (!intel_vram_all_mappable(&bufmgr->devinfo) && heap == IRIS_HEAP_DEVICE_LOCAL)
1099
mmap_mode = IRIS_MMAP_NONE;
1100
else if (!local && is_coherent && !is_scanout)
1101
mmap_mode = IRIS_MMAP_WB;
1103
mmap_mode = IRIS_MMAP_WC;
1200
enum iris_mmap_mode mmap_mode = iris_bo_alloc_get_mmap_mode(bufmgr, heap, flags);
1105
1202
simple_mtx_lock(&bufmgr->lock);
1368
needs_prime_fd(struct iris_bufmgr *bufmgr)
1370
return bufmgr->devinfo.kmd_type == INTEL_KMD_TYPE_XE;
1374
iris_bo_set_prime_fd(struct iris_bo *bo)
1376
struct iris_bufmgr *bufmgr = bo->bufmgr;
1378
if (needs_prime_fd(bufmgr) && bo->real.prime_fd == -1) {
1379
if (drmPrimeHandleToFD(bufmgr->fd, bo->gem_handle,
1380
DRM_CLOEXEC | DRM_RDWR, &bo->real.prime_fd)) {
1381
fprintf(stderr, "Failed to get prime fd for bo %s/%u\n",
1382
bo->name, bo->gem_handle);
1255
1391
* Returns a iris_bo wrapping the given buffer object handle.
1799
1942
/* GEM_SET_TILING is slightly broken and overwrites the input on the
1800
1943
* error path, so we have to open code intel_ioctl().
1803
struct drm_i915_gem_set_tiling set_tiling = {
1804
.handle = bo->gem_handle,
1805
.tiling_mode = tiling_mode,
1806
.stride = surf->row_pitch_B,
1808
ret = ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1809
} while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1945
struct drm_i915_gem_set_tiling set_tiling = {
1946
.handle = bo->gem_handle,
1947
.tiling_mode = tiling_mode,
1948
.stride = surf->row_pitch_B,
1951
ret = intel_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1812
1953
DBG("gem_set_tiling failed for BO %u: %s\n",
1813
1954
bo->gem_handle, strerror(errno));
1864
2006
if (INTEL_DEBUG(DEBUG_CAPTURE_ALL))
1865
2007
bo->real.kflags |= EXEC_OBJECT_CAPTURE;
1866
2008
bo->gem_handle = handle;
1868
/* From the Bspec, Memory Compression - Gfx12:
1870
* The base address for the surface has to be 64K page aligned and the
1871
* surface is expected to be padded in the virtual domain to be 4 4K
1874
* The dmabuf may contain a compressed surface. Align the BO to 64KB just
1875
* in case. We always align to 64KB even on platforms where we don't need
1876
* to, because it's a fairly reasonable thing to do anyway.
2009
bo->real.prime_fd = needs_prime_fd(bufmgr) ? dup(prime_fd) : -1;
2011
uint64_t alignment = 1;
2013
/* When an aux map will be used, there is an alignment requirement on the
2014
* main surface from the mapping granularity. Some planes of the image may
2015
* have smaller alignment requirements, but this one should work for all.
1878
bo->address = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 64 * 1024);
2017
if (bufmgr->devinfo.has_aux_map && isl_drm_modifier_has_aux(modifier))
2018
alignment = intel_aux_map_get_alignment(bufmgr->aux_map_ctx);
2020
bo->address = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, alignment);
1879
2021
if (bo->address == 0ull)
2250
static enum iris_mmap_mode
2251
iris_bo_alloc_aux_map_get_mmap_mode(struct iris_bufmgr *bufmgr,
2252
enum iris_heap heap)
2254
switch (bufmgr->devinfo.kmd_type) {
2255
case INTEL_KMD_TYPE_I915:
2256
return heap != IRIS_HEAP_SYSTEM_MEMORY ||
2257
bufmgr->devinfo.has_set_pat_uapi ?
2258
IRIS_MMAP_WC : IRIS_MMAP_WB;
2259
case INTEL_KMD_TYPE_XE:
2260
return iris_xe_bo_flags_to_mmap_mode(bufmgr, heap, 0);
2262
return IRIS_MMAP_NONE;
2104
2266
static struct intel_buffer *
2105
2267
intel_aux_map_buffer_alloc(void *driver_ctx, uint32_t size)
2172
2335
bufmgr->sys.region = &devinfo->mem.sram.mem;
2173
2336
bufmgr->sys.size = devinfo->mem.sram.mappable.size;
2338
/* When the resizable bar feature is disabled,
2339
* then vram.mappable.size is only 256MB.
2340
* The second half of the total size is in the vram.unmappable.size
2175
2343
bufmgr->vram.region = &devinfo->mem.vram.mem;
2176
bufmgr->vram.size = devinfo->mem.vram.mappable.size;
2344
bufmgr->vram.size = devinfo->mem.vram.mappable.size +
2345
devinfo->mem.vram.unmappable.size;