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Viewing changes to src/intel/vulkan/anv_nir_compute_push_layout.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/intel/vulkan/anv_nir_compute_push_layout.c
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anv_nir_compute_push_layout(nir_shader *nir,
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                            const struct anv_physical_device *pdevice,
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                            bool robust_buffer_access,
 
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                            bool fragment_dynamic,
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                            struct brw_stage_prog_data *prog_data,
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                            struct anv_pipeline_bind_map *map,
 
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                            const struct anv_pipeline_push_map *push_map,
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                            void *mem_ctx)
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{
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   const struct brw_compiler *compiler = pdevice->compiler;
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   bool has_const_ubo = false;
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   unsigned push_start = UINT_MAX, push_end = 0;
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   nir_foreach_function(function, nir) {
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      if (!function->impl)
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         continue;
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      nir_foreach_block(block, function->impl) {
 
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   nir_foreach_function_impl(impl, nir) {
 
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      nir_foreach_block(block, impl) {
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         nir_foreach_instr(instr, block) {
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            if (instr->type != nir_instr_type_intrinsic)
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               continue;
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            nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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            switch (intrin->intrinsic) {
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            case nir_intrinsic_load_ubo:
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               if (nir_src_is_const(intrin->src[0]) &&
 
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               if (brw_nir_ubo_surface_index_is_pushable(intrin->src[0]) &&
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                   nir_src_is_const(intrin->src[1]))
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                  has_const_ubo = true;
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               break;
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               break;
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            }
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            case nir_intrinsic_load_desc_set_address_intel: {
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               unsigned base = offsetof(struct anv_push_constants, desc_sets);
 
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            case nir_intrinsic_load_desc_set_address_intel:
 
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            case nir_intrinsic_load_desc_set_dynamic_index_intel: {
 
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               unsigned base = offsetof(struct anv_push_constants, desc_offsets);
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               push_start = MIN2(push_start, base);
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               push_end = MAX2(push_end, base +
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                  sizeof_field(struct anv_push_constants, desc_sets));
 
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                  sizeof_field(struct anv_push_constants, desc_offsets));
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               break;
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            }
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      push_end = MAX2(push_end, push_reg_mask_end);
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   }
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   if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
 
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      const uint32_t fs_msaa_flags_start =
 
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         offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
 
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      const uint32_t fs_msaa_flags_end = fs_msaa_flags_start + sizeof(uint32_t);
 
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      push_start = MIN2(push_start, fs_msaa_flags_start);
 
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      push_end = MAX2(push_end, fs_msaa_flags_end);
 
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   }
 
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   if (nir->info.stage == MESA_SHADER_COMPUTE && devinfo->verx10 < 125) {
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      /* For compute shaders, we always have to have the subgroup ID.  The
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       * back-end compiler will "helpfully" add it for us in the last push
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   };
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   if (has_push_intrinsic) {
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      nir_foreach_function(function, nir) {
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         if (!function->impl)
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            continue;
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         nir_builder build, *b = &build;
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         nir_builder_init(b, function->impl);
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         nir_foreach_block(block, function->impl) {
 
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      nir_foreach_function_impl(impl, nir) {
 
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         nir_builder build = nir_builder_create(impl);
 
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         nir_builder *b = &build;
 
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         nir_foreach_block(block, impl) {
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            nir_foreach_instr_safe(instr, block) {
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               if (instr->type != nir_instr_type_intrinsic)
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                  continue;
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               }
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               case nir_intrinsic_load_desc_set_address_intel: {
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                  b->cursor = nir_before_instr(&intrin->instr);
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                  nir_ssa_def *pc_load = nir_load_uniform(b, 1, 64,
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                     nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint64_t)),
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                     .base = offsetof(struct anv_push_constants, desc_sets),
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                     .range = sizeof_field(struct anv_push_constants, desc_sets),
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                     .dest_type = nir_type_uint64);
 
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                  assert(brw_shader_stage_requires_bindless_resources(nir->info.stage));
 
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                  b->cursor = nir_before_instr(&intrin->instr);
 
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                  nir_ssa_def *pc_load = nir_load_uniform(b, 1, 32,
 
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                     nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
 
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                     .base = offsetof(struct anv_push_constants, desc_offsets),
 
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                     .range = sizeof_field(struct anv_push_constants, desc_offsets),
 
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                     .dest_type = nir_type_uint32);
 
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                  pc_load = nir_iand_imm(b, pc_load, ANV_DESCRIPTOR_SET_OFFSET_MASK);
 
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                  nir_ssa_def *desc_addr =
 
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                     nir_pack_64_2x32_split(
 
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                        b, pc_load,
 
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                        nir_load_reloc_const_intel(
 
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                           b, BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
 
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                  nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc_addr);
 
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                  break;
 
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               }
 
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               case nir_intrinsic_load_desc_set_dynamic_index_intel: {
 
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                  b->cursor = nir_before_instr(&intrin->instr);
 
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                  nir_ssa_def *pc_load = nir_load_uniform(b, 1, 32,
 
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                     nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
 
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                     .base = offsetof(struct anv_push_constants, desc_offsets),
 
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                     .range = sizeof_field(struct anv_push_constants, desc_offsets),
 
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                     .dest_type = nir_type_uint32);
 
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                  pc_load = nir_iand_imm(
 
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                     b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
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                  nir_ssa_def_rewrite_uses(&intrin->dest.ssa, pc_load);
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                  break;
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               }
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         if (ubo_range->length == 0)
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            continue;
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         if (n >= 4 || (n == 3 && compiler->constant_buffer_0_is_relative)) {
 
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         if (n >= 4) {
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            memset(ubo_range, 0, sizeof(*ubo_range));
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            continue;
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         }
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         assert(ubo_range->block < push_map->block_count);
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         const struct anv_pipeline_binding *binding =
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            &map->surface_to_descriptor[ubo_range->block];
 
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            &push_map->block_to_descriptor[ubo_range->block];
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         map->push_ranges[n++] = (struct anv_push_range) {
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            .set = binding->set,
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      map->push_ranges[0] = push_constant_range;
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   }
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   if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
 
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      struct brw_wm_prog_data *wm_prog_data =
 
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         container_of(prog_data, struct brw_wm_prog_data, base);
 
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      const uint32_t fs_msaa_flags_offset =
 
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         offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
 
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      assert(fs_msaa_flags_offset >= push_start);
 
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      wm_prog_data->msaa_flags_param =
 
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         (fs_msaa_flags_offset - push_start) / 4;
 
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   }
 
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#if 0
 
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   fprintf(stderr, "stage=%s push ranges:\n", gl_shader_stage_name(nir->info.stage));
 
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   for (unsigned i = 0; i < ARRAY_SIZE(map->push_ranges); i++)
 
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      fprintf(stderr, "   range%i: %03u-%03u set=%u index=%u\n", i,
 
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              map->push_ranges[i].start,
 
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              map->push_ranges[i].length,
 
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              map->push_ranges[i].set,
 
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              map->push_ranges[i].index);
 
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#endif
 
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   /* Now that we're done computing the push constant portion of the
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    * bind map, hash it.  This lets us quickly determine if the actual
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    * mapping has changed and not just a no-op pipeline change.