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Viewing changes to src/freedreno/.gitlab-ci/reference/crash_prefetch.log

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/freedreno/.gitlab-ci/reference/crash_prefetch.log
854
854
        00000000        CP_CHICKEN_DBG: 0
855
855
        00000001        CP_ADDR_MODE_CNTL: ADDR_64B
856
856
        00000000        CP_DBG_ECO_CNTL: 0
857
 
        0000000b        CP_PROTECT_CNTL: 0xb
 
857
        0000000b        CP_PROTECT_CNTL: { LAST_SPAN_INF_RANGE | ACCESS_FAULT_ON_VIOL_EN | ACCESS_PROT_EN }
858
858
        13fc0000        CP_PROTECT[0].REG: { BASE_ADDR = 0 | MASK_LEN = 0x4ff }
859
859
        00140501        CP_PROTECT[0x1].REG: { BASE_ADDR = 0x501 | MASK_LEN = 0x5 }
860
860
        0bd0050b        CP_PROTECT[0x2].REG: { BASE_ADDR = 0x50b | MASK_LEN = 0x2f4 }
1911
1911
                event CACHE_INVALIDATE
1912
1912
0000000000000000:               0000: 70460001 00000031
1913
1913
                opcode: CP_WAIT_REG_MEM (3c) (7 dwords)
1914
 
                        { FUNCTION = WRITE_EQ }
 
1914
                        { FUNCTION = WRITE_EQ | POLL = POLL_REGISTER }
1915
1915
                        { POLL_ADDR_LO = 0x50f }
1916
1916
                        { POLL_ADDR_HI = 0 }
1917
1917
                        { REF = 0x1 }
2279
2279
00000001002232a4:                       0000: 70e30001 00000000
2280
2280
                        opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
2281
2281
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
2282
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
2282
                                        { MODE = RENDER_MODE | GMEM }
2283
2283
                                        { DWORDS = 54 }
2284
2284
0000000100227000:                               0000: 70c70002 34000000 00000036
2285
2285
                                opcode: CP_EVENT_WRITE (46) (2 dwords)
2398
2398
 +      00000003                                RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
2399
2399
00000001002270dc:                               0000: 70460001 0000001e
2400
2400
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
2401
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
 
2401
                                        { MODE = RENDER_MODE | GMEM | SYSMEM }
2402
2402
                                        { DWORDS = 4 }
2403
2403
0000000100227200:                               0000: 70c70002 3c000000 00000004
2404
2404
                                opcode: CP_REG_WRITE (6d) (4 dwords)
3012
3012
00000001002232bc:                       0000: 70bf8003 00208000 00000001 00000061
3013
3013
                        opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
3014
3014
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3015
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
3015
                                        { MODE = RENDER_MODE | GMEM }
3016
3016
                                        { DWORDS = 23 }
3017
3017
0000000100227238:                               0000: 70c70002 34000000 00000017
3018
3018
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3019
 
                                        { REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
 
3019
                                        { MODE = PRED_TEST | PRED_BIT = 0 }
3020
3020
                                        { DWORDS = 17 }
3021
3021
0000000100227250:                               0000: 70c70002 10000000 00000011
3022
3022
                                opcode: CP_EVENT_WRITE (46) (2 dwords)
3037
3037
!+      00000000                                RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
3038
3038
0000000100227298:                               0000: 70460001 0000001e
3039
3039
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3040
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
3040
                                        { MODE = RENDER_MODE | GMEM }
3041
3041
                                        { DWORDS = 20 }
3042
3042
00000001002272a0:                               0000: 70c70002 34000000 00000014
3043
3043
                                opcode: CP_EVENT_WRITE (46) (2 dwords)
3059
3059
!+      000000f2                                RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
3060
3060
00000001002272f4:                               0000: 70460001 0000001e
3061
3061
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3062
 
                                        { REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
 
3062
                                        { MODE = RENDER_MODE | SYSMEM }
3063
3063
                                        { DWORDS = 34 }
3064
3064
00000001002272fc:                               0000: 70c70002 38000000 00000022
3065
3065
                                opcode: CP_BLIT (2c) (2 dwords)
3095
3095
                                event PC_CCU_INVALIDATE_COLOR
3096
3096
0000000100227388:                               0000: 70460001 00000019
3097
3097
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3098
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
 
3098
                                        { MODE = RENDER_MODE | GMEM | SYSMEM }
3099
3099
                                        { DWORDS = 4 }
3100
3100
00000001002274ac:                               0000: 70c70002 3c000000 00000004
3101
3101
                                opcode: CP_REG_WRITE (6d) (4 dwords)
3726
3726
00000001002232dc:                       0000: 70bf8003 0020f000 00000001 00000061
3727
3727
                        opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
3728
3728
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3729
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
3729
                                        { MODE = RENDER_MODE | GMEM }
3730
3730
                                        { DWORDS = 23 }
3731
3731
000000010022750c:                               0000: 70c70002 34000000 00000017
3732
3732
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3733
 
                                        { REG0 = 0 | PRED_BIT = 0 | MODE = PRED_TEST }
 
3733
                                        { MODE = PRED_TEST | PRED_BIT = 0 }
3734
3734
                                        { DWORDS = 17 }
3735
3735
0000000100227524:                               0000: 70c70002 10000000 00000011
3736
3736
                                opcode: CP_EVENT_WRITE (46) (2 dwords)
3751
3751
!+      00000000                                RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
3752
3752
000000010022756c:                               0000: 70460001 0000001e
3753
3753
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3754
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
3754
                                        { MODE = RENDER_MODE | GMEM }
3755
3755
                                        { DWORDS = 20 }
3756
3756
0000000100227574:                               0000: 70c70002 34000000 00000014
3757
3757
                                opcode: CP_EVENT_WRITE (46) (2 dwords)
3773
3773
!+      000000f2                                RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
3774
3774
00000001002275c8:                               0000: 70460001 0000001e
3775
3775
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3776
 
                                        { REG0 = 0 | PRED_BIT = 0 | SYSMEM | MODE = RENDER_MODE }
 
3776
                                        { MODE = RENDER_MODE | SYSMEM }
3777
3777
                                        { DWORDS = 34 }
3778
3778
00000001002275d0:                               0000: 70c70002 38000000 00000022
3779
3779
                                opcode: CP_BLIT (2c) (2 dwords)
3809
3809
                                event PC_CCU_INVALIDATE_COLOR
3810
3810
000000010022765c:                               0000: 70460001 00000019
3811
3811
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
3812
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
 
3812
                                        { MODE = RENDER_MODE | GMEM | SYSMEM }
3813
3813
                                        { DWORDS = 4 }
3814
3814
0000000100227780:                               0000: 70c70002 3c000000 00000004
3815
3815
                                opcode: CP_REG_WRITE (6d) (4 dwords)
4452
4452
00000001002232fc:                       0000: 70bf8003 00216000 00000001 00000061
4453
4453
                        opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
4454
4454
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
4455
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | MODE = RENDER_MODE }
 
4455
                                        { MODE = RENDER_MODE | GMEM }
4456
4456
                                        { DWORDS = 3 }
4457
4457
00000001002277fc:                               0000: 70c70002 34000000 00000003
4458
4458
                                opcode: CP_COND_REG_EXEC (47) (3 dwords)
4459
 
                                        { REG0 = 0 | PRED_BIT = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
 
4459
                                        { MODE = RENDER_MODE | GMEM | SYSMEM }
4460
4460
                                        { DWORDS = 4 }
4461
4461
0000000100227930:                               0000: 70c70002 3c000000 00000004
4462
4462
                                opcode: CP_REG_WRITE (6d) (4 dwords)
13309
13309
        00000000        GMU_HOST2GMU_INTR_INFO_2: 0
13310
13310
        00000000        GMU_HOST2GMU_INTR_INFO_3: 0
13311
13311
        10010000        0x51c0: 10010000
13312
 
        babeface        0x51c5: babeface
 
13312
        babeface        GMU_GENERAL_0: 0xbabeface
13313
13313
        00000000        GMU_GENERAL_1: 0
13314
13314
        00000000        0x51c7: 00000000
13315
13315
        00000000        0x51c8: 00000000
13316
13316
        60005018        0x51c9: 60005018
13317
13317
        60005048        0x51ca: 60005048
13318
 
        00000000        0x51cb: 00000000
 
13318
        00000000        GMU_GENERAL_6: 0
13319
13319
        00000001        GMU_GENERAL_7: 0x1
13320
13320
        00000000        0x51e0: 00000000
13321
13321
        00000000        0x51e1: 00000000
13343
13343
        802800a0        GMU_AHB_FENCE_RANGE_0: 0x802800a0
13344
13344
        00000000        GMU_AHB_FENCE_RANGE_1: 0
13345
13345
        00000000        GMU_AHB_FENCE_STATUS: 0
13346
 
        00000000        0x9314: 00000000
 
13346
        00000000        GMU_AHB_FENCE_STATUS_CLR: 0
13347
13347
        00000001        GMU_RBBM_INT_UNMASKED_STATUS: 0x1
13348
13348
        00000000        GMU_AO_SPARE_CNTL: 0
13349
13349
        00000000        0x9400: 00000000