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Viewing changes to src/intel/vulkan/i915/anv_device.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/intel/vulkan/i915/anv_device.c
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}
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VkResult
 
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anv_i915_physical_device_init_memory_types(struct anv_physical_device *device)
 
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{
 
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   if (anv_physical_device_has_vram(device)) {
 
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      device->memory.type_count = 3;
 
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      device->memory.types[0] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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      device->memory.types[1] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
 
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         .heapIndex = 1,
 
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      };
 
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      device->memory.types[2] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
 
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         /* This memory type either comes from heaps[0] if there is only
 
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          * mappable vram region, or from heaps[2] if there is both mappable &
 
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          * non-mappable vram regions.
 
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          */
 
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         .heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0,
 
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      };
 
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   } else if (device->info.has_llc) {
 
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      /* Big core GPUs share LLC with the CPU and thus one memory type can be
 
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       * both cached and coherent at the same time.
 
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       *
 
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       * But some game engines can't handle single type well
 
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       * https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438
 
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       *
 
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       * The second memory type w/out HOST_CACHED_BIT will get write-combining.
 
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       * See anv_AllocateMemory()).
 
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       *
 
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       * The Intel Vulkan driver for Windows also advertises these memory types.
 
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       */
 
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      device->memory.type_count = 3;
 
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      device->memory.types[0] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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      device->memory.types[1] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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      device->memory.types[2] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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   } else {
 
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      /* The spec requires that we expose a host-visible, coherent memory
 
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       * type, but Atom GPUs don't share LLC. Thus we offer two memory types
 
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       * to give the application a choice between cached, but not coherent and
 
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       * coherent but uncached (WC though).
 
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       */
 
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      device->memory.type_count = 2;
 
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      device->memory.types[0] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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      device->memory.types[1] = (struct anv_memory_type) {
 
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         .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
 
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                          VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
 
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         .heapIndex = 0,
 
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      };
 
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   }
 
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   return VK_SUCCESS;
 
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}
 
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VkResult
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anv_i915_device_setup_context(struct anv_device *device,
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                              const VkDeviceCreateInfo *pCreateInfo,
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                              const uint32_t num_queues)
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         for (uint32_t j = 0; j < queueCreateInfo->queueCount; j++)
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            engine_classes[engine_count++] = queue_family->engine_class;
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      }
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      if (!intel_gem_create_context_engines(device->fd,
 
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      if (!intel_gem_create_context_engines(device->fd, 0 /* flags */,
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                                            physical_device->engine_info,
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                                            engine_count, engine_classes,
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                                            (uint32_t *)&device->context_id))