57
57
PVR_PBE_ACCUM_FORMAT_U24,
61
* Pixel related shader selector. The logic selecting the shader has to take
62
* into account the pixel related properties (controlling the conversion path in
63
* the shader) and the geometry related properties (controlling the sample
64
* position calcs). These two can be orthogonal.
66
* integer format conversions, bit depth : 8, 16, 32 per ch formats : signed,
67
* unsigned. Strategy: convert everything to U32 or S32 then USC pack. PBE just
70
* fixed point format conversions, bit depth 565, 1555, 555 etc. Strategy:
71
* fcnorm to 4 F32, then USC pack to F16F16. PBE converts to destination
73
* float/fixed format conversions
74
* strategy: fcnorm, then pack to f16 _when_ destination is not f32.
81
* non-merge type DS blit table
82
* **********************************************
83
* * * S8 D16 D24S8 D32 D32S8 *
84
* **********************************************
85
* * S8 * cpy i i i i *
86
* * D16 * i cpy i - i *
87
* * D24S8 * swiz - cpy (1) - *
88
* * D32 * i - i cpy i *
89
* * D32S8 * (2) - - cpy cpy *
90
* **********************************************
92
* merge with stencil pick type DS blit table
93
* **********************************************
94
* * * S8 D16 D24S8 D32 D32S8 *
95
* **********************************************
96
* * S8 * i i (1) i (2) *
98
* * D24S8 * i i (3) i (4) *
100
* * D32S8 * i i (5) i (6) *
101
* **********************************************
103
* merge with depth pick type DS blit table
104
* **********************************************
105
* * * S8 D16 D24S8 D32 D32S8 *
106
* **********************************************
108
* * D16 * - - - - - *
109
* * D24S8 * - - (s) - - *
110
* * D32 * - - (1) - (2) *
111
* * D32S8 * - - - - (s) *
112
* **********************************************
114
* D formats are unpacked into a single register according to their format
115
* S formats are unpacked into a single register in U8
116
* D24S8 is in a single 32 bit register (as the PBE can't read it from
119
* Swizzles are applied on the TPU not the PBE because of potential
120
* accumulation i.e. a non-iterated shader doesn't know if it writes the output
121
* buffer for PBE emit or a second pass blend.
123
enum pvr_transfer_pbe_pixel_src {
124
PVR_TRANSFER_PBE_PIXEL_SRC_UU8888 = 0,
125
PVR_TRANSFER_PBE_PIXEL_SRC_US8888 = 1,
126
PVR_TRANSFER_PBE_PIXEL_SRC_UU16U16 = 2,
127
PVR_TRANSFER_PBE_PIXEL_SRC_US16S16 = 3,
128
PVR_TRANSFER_PBE_PIXEL_SRC_SU8888 = 4,
129
PVR_TRANSFER_PBE_PIXEL_SRC_SS8888 = 5,
130
PVR_TRANSFER_PBE_PIXEL_SRC_SU16U16 = 6,
131
PVR_TRANSFER_PBE_PIXEL_SRC_SS16S16 = 7,
133
PVR_TRANSFER_PBE_PIXEL_SRC_UU1010102 = 8,
134
PVR_TRANSFER_PBE_PIXEL_SRC_SU1010102 = 9,
135
PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_UU1010102 = 10,
136
PVR_TRANSFER_PBE_PIXEL_SRC_RBSWAP_SU1010102 = 11,
138
PVR_TRANSFER_PBE_PIXEL_SRC_SU32U32 = 12,
139
PVR_TRANSFER_PBE_PIXEL_SRC_S4XU32 = 13,
140
PVR_TRANSFER_PBE_PIXEL_SRC_US32S32 = 14,
141
PVR_TRANSFER_PBE_PIXEL_SRC_U4XS32 = 15,
143
PVR_TRANSFER_PBE_PIXEL_SRC_F16F16 = 16,
144
PVR_TRANSFER_PBE_PIXEL_SRC_U16NORM = 17,
145
PVR_TRANSFER_PBE_PIXEL_SRC_S16NORM = 18,
147
PVR_TRANSFER_PBE_PIXEL_SRC_F32X4 = 19,
148
PVR_TRANSFER_PBE_PIXEL_SRC_F32X2 = 20,
149
PVR_TRANSFER_PBE_PIXEL_SRC_F32 = 21,
151
PVR_TRANSFER_PBE_PIXEL_SRC_RAW32 = 22,
152
PVR_TRANSFER_PBE_PIXEL_SRC_RAW64 = 23,
153
PVR_TRANSFER_PBE_PIXEL_SRC_RAW128 = 24,
155
/* f16 to U8 conversion in shader. */
156
PVR_TRANSFER_PBE_PIXEL_SRC_F16_U8 = 25,
158
PVR_TRANSFER_PBE_PIXEL_SRC_SWAP_LMSB = 26,
159
PVR_TRANSFER_PBE_PIXEL_SRC_MOV_BY45 = 27,
161
PVR_TRANSFER_PBE_PIXEL_SRC_D24S8 = 28,
162
PVR_TRANSFER_PBE_PIXEL_SRC_S8D24 = 29,
163
PVR_TRANSFER_PBE_PIXEL_SRC_D32S8 = 30,
166
PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D32S8 = 31,
167
PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D32S8 = 32,
168
PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D32S8_D32S8 = 33,
169
PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32S8_D32S8 = 34,
172
PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D24_D32 = 35,
173
PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32U_D32F = 36,
176
PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_S8_D24S8 = 37,
177
PVR_TRANSFER_PBE_PIXEL_SRC_SMRG_D24S8_D24S8 = 38,
178
PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D24S8_D24S8 = 39,
179
PVR_TRANSFER_PBE_PIXEL_SRC_CONV_D32_D24S8 = 40,
180
PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32_D24S8 = 41,
181
PVR_TRANSFER_PBE_PIXEL_SRC_DMRG_D32U_D24S8 = 42,
183
/* ob0 holds Y and ob0 holds U or V. */
184
PVR_TRANSFER_PBE_PIXEL_SRC_YUV_PACKED = 43,
186
/* ob0 holds Y, ob1 holds U, ob2 holds V. */
187
PVR_TRANSFER_PBE_PIXEL_SRC_Y_U_V = 44,
189
PVR_TRANSFER_PBE_PIXEL_SRC_MASK16 = 45,
190
PVR_TRANSFER_PBE_PIXEL_SRC_MASK32 = 46,
191
PVR_TRANSFER_PBE_PIXEL_SRC_MASK48 = 47,
192
PVR_TRANSFER_PBE_PIXEL_SRC_MASK64 = 48,
193
PVR_TRANSFER_PBE_PIXEL_SRC_MASK96 = 49,
194
PVR_TRANSFER_PBE_PIXEL_SRC_MASK128 = 50,
196
PVR_TRANSFER_PBE_PIXEL_SRC_CONV_S8D24_D24S8 = 51,
198
/* ob0 holds Y and ob0 holds V or U. */
199
PVR_TRANSFER_PBE_PIXEL_SRC_YVU_PACKED = 52,
201
/* ob0 holds Y, ob1 holds UV interleaved. */
202
PVR_TRANSFER_PBE_PIXEL_SRC_Y_UV_INTERLEAVED = 53,
204
/* FIXME: This changes for other BVNC's which may change the hashing logic
205
* in pvr_hash_shader.
207
PVR_TRANSFER_PBE_PIXEL_SRC_NUM = 54,
60
210
const uint8_t *pvr_get_format_swizzle(VkFormat vk_format);
61
211
uint32_t pvr_get_tex_format(VkFormat vk_format);
62
212
uint32_t pvr_get_tex_format_aspect(VkFormat vk_format,
added
removed
src/imagination/vulkan/pvr_formats.h
