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Viewing changes to src/gallium/drivers/r600/sfn/sfn_nir.cpp

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/gallium/drivers/r600/sfn/sfn_nir.cpp
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#include "nir.h"
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#include "nir_builder.h"
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#include "nir_intrinsics.h"
 
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#include "r600_asm.h"
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#include "sfn_assembler.h"
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#include "sfn_debug.h"
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#include "sfn_instr_tex.h"
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#include "sfn_ra.h"
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#include "sfn_scheduler.h"
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#include "sfn_shader.h"
 
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#include "sfn_split_address_loads.h"
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#include "util/u_prim.h"
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#include <vector>
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   }
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   nir_ssa_def *address = instr->src[address_index].ssa;
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   nir_ssa_def *new_address = nir_ishr(b, address, nir_imm_int(b, 4 * align));
 
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   nir_ssa_def *new_address = nir_ishr_imm(b, address, 4 * align);
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   nir_instr_rewrite_src(&instr->instr,
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                         &instr->src[address_index],
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r600_lower_scratch_addresses(nir_shader *shader)
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{
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   bool progress = false;
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   nir_foreach_function(function, shader)
 
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   nir_foreach_function_impl(impl, shader)
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   {
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      nir_builder build;
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      nir_builder_init(&build, function->impl);
 
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      nir_builder build = nir_builder_create(impl);
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      nir_foreach_block(block, function->impl)
 
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      nir_foreach_block(block, impl)
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      {
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         nir_foreach_instr(instr, block)
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         {
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         array_stride *= glsl_get_aoa_size(d->type);
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      offset =
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         nir_iadd(b, offset, nir_imul(b, d->arr.index.ssa, nir_imm_int(b, array_stride)));
 
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         nir_iadd(b, offset, nir_imul_imm(b, d->arr.index.ssa, array_stride));
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   }
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   /* Since the first source is a deref and the first source in the lowered
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}
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static bool
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r600_lower_shared_io_impl(nir_function *func)
 
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r600_lower_shared_io_impl(nir_function_impl *impl)
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{
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   nir_builder b;
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   nir_builder_init(&b, func->impl);
 
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   nir_builder b = nir_builder_create(impl);
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   bool progress = false;
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   nir_foreach_block(block, func->impl)
 
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   nir_foreach_block(block, impl)
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   {
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      nir_foreach_instr_safe(instr, block)
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      {
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               nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_local_shared_r600);
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            load->num_components = nir_dest_num_components(op->dest);
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            load->src[0] = nir_src_for_ssa(addr);
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            nir_ssa_dest_init(&load->instr, &load->dest, load->num_components, 32, NULL);
 
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            nir_ssa_dest_init(&load->instr, &load->dest, load->num_components,
 
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                              32);
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            nir_ssa_def_rewrite_uses(&op->dest.ssa, &load->dest.ssa);
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            nir_builder_instr_insert(&b, &load->instr);
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         } else {
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               bool start_even = (writemask & (1u << (2 * i)));
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               auto addr2 =
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                  nir_iadd(&b, addr, nir_imm_int(&b, 8 * i + (start_even ? 0 : 4)));
 
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                  nir_iadd_imm(&b, addr, 8 * i + (start_even ? 0 : 4));
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               store->src[1] = nir_src_for_ssa(addr2);
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               nir_builder_instr_insert(&b, &store->instr);
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r600_lower_shared_io(nir_shader *nir)
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{
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   bool progress = false;
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   nir_foreach_function(function, nir)
 
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   nir_foreach_function_impl(impl, nir)
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   {
590
 
      if (function->impl && r600_lower_shared_io_impl(function))
 
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      if (r600_lower_shared_io_impl(impl))
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         progress = true;
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   }
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   return progress;
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   (void)_options;
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   auto old_ir = nir_instr_as_intrinsic(instr);
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   auto load = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_input);
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   nir_ssa_dest_init(&load->instr,
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                     &load->dest,
 
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   nir_ssa_dest_init(&load->instr, &load->dest,
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                     old_ir->dest.ssa.num_components,
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                     old_ir->dest.ssa.bit_size,
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                     NULL);
 
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                     old_ir->dest.ssa.bit_size);
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   nir_intrinsic_set_io_semantics(load, nir_intrinsic_io_semantics(old_ir));
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   nir_intrinsic_set_base(load, nir_intrinsic_base(old_ir));
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   case nir_op_fddy_coarse:
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   case nir_op_fddy_fine:
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      return nir_src_bit_size(alu->src[0].src) == 64;
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   case nir_op_cube_r600:
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      return false;
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   default:
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      return true;
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   }
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   nir_shader *nir = (nir_shader *)shader;
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   NIR_PASS_V(nir, nir_lower_regs_to_ssa);
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   const int nir_lower_flrp_mask = 16 | 32 | 64;
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   NIR_PASS_V(nir, nir_lower_flrp, nir_lower_flrp_mask, false);
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       (sh->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
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      auto prim_type = sh->info.stage == MESA_SHADER_TESS_EVAL
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                          ? u_tess_prim_from_shader(sh->info.tess._primitive_mode)
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                          : (pipe_prim_type)key->tcs.prim_mode;
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      NIR_PASS_V(sh, r600_lower_tess_io, static_cast<pipe_prim_type>(prim_type));
 
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                          : (mesa_prim)key->tcs.prim_mode;
 
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      NIR_PASS_V(sh, r600_lower_tess_io, static_cast<mesa_prim>(prim_type));
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   }
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   if (sh->info.stage == MESA_SHADER_TESS_CTRL)
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      NIR_PASS_V(sh, r600_append_tcs_TF_emission, (pipe_prim_type)key->tcs.prim_mode);
 
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      NIR_PASS_V(sh, r600_append_tcs_TF_emission, (mesa_prim)key->tcs.prim_mode);
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   if (sh->info.stage == MESA_SHADER_TESS_EVAL) {
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      NIR_PASS_V(sh,
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   NIR_PASS_V(sh, nir_lower_bool_to_int32);
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   NIR_PASS_V(sh, nir_lower_locals_to_regs);
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   NIR_PASS_V(sh,
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              nir_lower_to_source_mods,
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              (nir_lower_to_source_mods_flags)(nir_lower_float_source_mods |
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                                               nir_lower_64bit_source_mods));
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   NIR_PASS_V(sh, nir_convert_from_ssa, true);
 
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   NIR_PASS_V(sh, nir_lower_locals_to_regs, 32);
 
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   NIR_PASS_V(sh, nir_convert_from_ssa, true, false);
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   NIR_PASS_V(sh, nir_opt_dce);
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   if (rctx->screen->b.debug_flags & DBG_ALL_SHADERS) {
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   r600_screen *rscreen = rctx->screen;
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   r600::Shader *shader =
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      r600::Shader::translate_from_nir(sh, &sel->so, gs_shader, *key, rctx->isa->hw_class);
 
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      r600::Shader::translate_from_nir(sh, &sel->so, gs_shader, *key,
 
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                                       rctx->isa->hw_class, rscreen->b.family);
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   assert(shader);
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   if (!shader)
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      }
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   }
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   if (!r600::sfn_log.has_debug_flag(r600::SfnLog::noaddrsplit))
 
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      split_address_loads(*shader);
 
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   if (r600::sfn_log.has_debug_flag(r600::SfnLog::steps)) {
 
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      std::cerr << "Shader after splitting address loads\n";
 
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      shader->print(std::cerr);
 
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   }
 
1006
   
 
1007
   if (!r600::sfn_log.has_debug_flag(r600::SfnLog::noopt)) {
 
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      optimize(*shader);
 
1009
 
 
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      if (r600::sfn_log.has_debug_flag(r600::SfnLog::steps)) {
 
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         std::cerr << "Shader after optimization\n";
 
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         shader->print(std::cerr);
 
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      }
 
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   }
 
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   auto scheduled_shader = r600::schedule(shader);
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   if (r600::sfn_log.has_debug_flag(r600::SfnLog::steps)) {
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      std::cerr << "Shader after scheduling\n";
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                      rscreen->b.family,
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                      rscreen->has_compressed_msaa_texturing);
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   /* We already schedule the code with this in mind, no need to handle this
 
1053
    * in the backend assembler */
 
1054
   if (!r600::sfn_log.has_debug_flag(r600::SfnLog::noaddrsplit)) {
 
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      pipeshader->shader.bc.ar_handling = AR_HANDLE_NORMAL;
 
1056
      pipeshader->shader.bc.r6xx_nop_after_rel_dst = 0;
 
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   }
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   r600::sfn_log << r600::SfnLog::shader_info << "pipeshader->shader.processor_type = "
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                 << pipeshader->shader.processor_type << "\n";
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            sh->info.vs.window_space_position;
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   }
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1081
   if (sh->info.stage == MESA_SHADER_FRAGMENT)
 
1082
      pipeshader->shader.ps_conservative_z =
 
1083
            sh->info.fs.depth_layout;
 
1084
 
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   if (sh->info.stage == MESA_SHADER_GEOMETRY) {
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      r600::sfn_log << r600::SfnLog::shader_info
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                    << "Geometry shader, create copy shader\n";