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Viewing changes to src/gallium/drivers/zink/zink_context.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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Lines of Context:
src/gallium/drivers/zink/zink_context.c
30
30
#include "zink_helpers.h"
31
31
#include "zink_inlines.h"
32
32
#include "zink_kopper.h"
 
33
#include "zink_pipeline.h"
33
34
#include "zink_program.h"
34
35
#include "zink_query.h"
35
36
#include "zink_render_pass.h"
45
46
#include "util/format/u_format.h"
46
47
#include "util/u_helpers.h"
47
48
#include "util/u_inlines.h"
 
49
#include "util/u_sample_positions.h"
48
50
#include "util/u_string.h"
49
51
#include "util/u_thread.h"
50
52
#include "util/perf/u_trace.h"
100
102
       * - if tracking will be added here, also reapply usage to avoid dangling usage once tracking is removed
101
103
       * TODO: somehow fix this for perf because it's an extra hash lookup
102
104
       */
103
 
      if (!res->obj->dt && (res->obj->bo->reads || res->obj->bo->writes))
104
 
         zink_batch_reference_resource_rw(&ctx->batch, res, !!res->obj->bo->writes);
 
105
      if (!res->obj->dt && zink_resource_has_usage(res))
 
106
         zink_batch_reference_resource_rw(&ctx->batch, res, !!res->obj->bo->writes.u);
105
107
      else
106
108
         zink_batch_reference_resource(&ctx->batch, res);
107
109
   }
129
131
      simple_mtx_lock((&ctx->program_lock[i]));
130
132
      hash_table_foreach(&ctx->program_cache[i], entry) {
131
133
         struct zink_program *pg = entry->data;
 
134
         util_queue_fence_wait(&pg->cache_fence);
132
135
         pg->removed = true;
133
136
      }
134
137
      simple_mtx_unlock((&ctx->program_lock[i]));
205
208
   _mesa_hash_table_destroy(ctx->render_pass_cache, NULL);
206
209
   slab_destroy_child(&ctx->transfer_pool_unsync);
207
210
 
 
211
   if (zink_debug & ZINK_DEBUG_DGC) {
 
212
      for (unsigned i = 0; i < ARRAY_SIZE(ctx->dgc.upload); i++)
 
213
         u_upload_destroy(ctx->dgc.upload[i]);
 
214
      for (unsigned i = 0; i < ARRAY_SIZE(ctx->dgc.buffers); i++) {
 
215
         if (!ctx->dgc.buffers[i])
 
216
            continue;
 
217
         struct pipe_resource *pres = &ctx->dgc.buffers[i]->base.b;
 
218
         pipe_resource_reference(&pres, NULL);
 
219
      }
 
220
      util_dynarray_fini(&ctx->dgc.pipelines);
 
221
   }
 
222
 
208
223
   zink_descriptors_deinit(ctx);
209
224
 
210
225
   if (!(ctx->flags & ZINK_CONTEXT_COPY_ONLY))
285
300
   }
286
301
}
287
302
 
 
303
static void
 
304
zink_set_debug_callback(struct pipe_context *pctx, const struct util_debug_callback *cb)
 
305
{
 
306
   struct zink_context *ctx = zink_context(pctx);
 
307
 
 
308
   if (cb)
 
309
      ctx->dbg = *cb;
 
310
   else
 
311
      memset(&ctx->dbg, 0, sizeof(ctx->dbg));
 
312
}
 
313
 
288
314
static VkSamplerMipmapMode
289
315
sampler_mipmap_mode(enum pipe_tex_mipfilter filter)
290
316
{
603
629
         ctx->di.db.ubos[shader][slot].address = res->obj->bda + ctx->ubos[shader][slot].buffer_offset;
604
630
      else
605
631
         ctx->di.db.ubos[shader][slot].address = 0;
606
 
      ctx->di.db.ubos[shader][slot].range = ctx->ubos[shader][slot].buffer_size;
607
 
      assert(ctx->di.db.ubos[shader][slot].range <= screen->info.props.limits.maxUniformBufferRange);
 
632
      ctx->di.db.ubos[shader][slot].range = res ? ctx->ubos[shader][slot].buffer_size : VK_WHOLE_SIZE;
 
633
      assert(ctx->di.db.ubos[shader][slot].range == VK_WHOLE_SIZE ||
 
634
             ctx->di.db.ubos[shader][slot].range <= screen->info.props.limits.maxUniformBufferRange);
608
635
   } else {
609
636
      ctx->di.t.ubos[shader][slot].offset = ctx->ubos[shader][slot].buffer_offset;
610
637
      if (res) {
638
665
         ctx->di.db.ssbos[shader][slot].address = res->obj->bda + ctx->ssbos[shader][slot].buffer_offset;
639
666
      else
640
667
         ctx->di.db.ssbos[shader][slot].address = 0;
641
 
      ctx->di.db.ssbos[shader][slot].range = ctx->ssbos[shader][slot].buffer_size;
 
668
      ctx->di.db.ssbos[shader][slot].range = res ? ctx->ssbos[shader][slot].buffer_size : VK_WHOLE_SIZE;
642
669
   } else {
643
670
      ctx->di.t.ssbos[shader][slot].offset = ctx->ssbos[shader][slot].buffer_offset;
644
671
      if (res) {
682
709
                                state->sampler_clamped :
683
710
                                state->sampler;
684
711
            if (ctx->di.textures[shader][slot].sampler != sampler) {
685
 
               zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
 
712
               ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
686
713
               ctx->di.textures[shader][slot].sampler = sampler;
687
714
            }
688
715
         }
693
720
         ctx->di.textures[shader][slot].imageLayout = VK_IMAGE_LAYOUT_UNDEFINED;
694
721
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
695
722
            ctx->di.db.tbos[shader][slot].address = 0;
 
723
            ctx->di.db.tbos[shader][slot].range = VK_WHOLE_SIZE;
696
724
         } else {
697
725
            ctx->di.t.tbos[shader][slot] = VK_NULL_HANDLE;
698
726
         }
740
768
   } else {
741
769
      if (likely(have_null_descriptors)) {
742
770
         memset(&ctx->di.images[shader][slot], 0, sizeof(ctx->di.images[shader][slot]));
743
 
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB)
 
771
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
744
772
            ctx->di.db.texel_images[shader][slot].address = 0;
745
 
         else
 
773
            ctx->di.db.texel_images[shader][slot].range = VK_WHOLE_SIZE;
 
774
         } else {
746
775
            ctx->di.t.texel_images[shader][slot] = VK_NULL_HANDLE;
 
776
         }
747
777
      } else {
748
778
         assert(zink_descriptor_mode != ZINK_DESCRIPTOR_MODE_DB);
749
779
         struct zink_surface *null_surface = zink_get_dummy_surface(ctx, 0);
781
811
   struct zink_screen *screen = zink_screen(pctx->screen);
782
812
   for (unsigned i = 0; i < num_samplers; ++i) {
783
813
      struct zink_sampler_state *state = samplers[i];
784
 
      if (ctx->sampler_states[shader][start_slot + i] != state)
785
 
         zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot, 1);
 
814
      if (samplers[i] == ctx->sampler_states[shader][start_slot + i])
 
815
         continue;
 
816
      ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot, 1);
786
817
      ctx->sampler_states[shader][start_slot + i] = state;
787
818
      if (state) {
788
819
         ctx->di.textures[shader][start_slot + i].sampler = state->sampler;
823
854
         if (surface && ctx->di.images[shader][start_slot + i].imageView != surface->image_view) {
824
855
            ctx->di.images[shader][start_slot + i].imageView = surface->image_view;
825
856
            update_descriptor_state_sampler(ctx, shader, start_slot + i, zink_resource(surface->base.texture));
826
 
            zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot + i, 1);
 
857
            ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot + i, 1);
827
858
         }
828
859
      }
829
860
   }
1015
1046
   struct zink_sampler_view *sampler_view = CALLOC_STRUCT_CL(zink_sampler_view);
1016
1047
   bool err;
1017
1048
 
 
1049
   if (!sampler_view) {
 
1050
      mesa_loge("ZINK: failed to allocate sampler_view!");
 
1051
      return NULL;
 
1052
   }
 
1053
      
1018
1054
   sampler_view->base = *state;
1019
1055
   sampler_view->base.texture = NULL;
1020
1056
   pipe_resource_reference(&sampler_view->base.texture, pres);
1045
1081
      ivci = create_ivci(screen, res, &templ, state->target);
1046
1082
      ivci.subresourceRange.levelCount = state->u.tex.last_level - state->u.tex.first_level + 1;
1047
1083
      ivci.subresourceRange.aspectMask = sampler_aspect_from_format(state->format);
1048
 
      bool shadow_needs_shader_swizzle = false;
 
1084
      bool red_depth_sampler_view = false;
1049
1085
      /* samplers for stencil aspects of packed formats need to always use stencil swizzle */
1050
1086
      if (ivci.subresourceRange.aspectMask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1051
1087
         ivci.components.r = zink_component_mapping(clamp_zs_swizzle(sampler_view->base.swizzle_r));
1052
1088
         ivci.components.g = zink_component_mapping(clamp_zs_swizzle(sampler_view->base.swizzle_g));
1053
1089
         ivci.components.b = zink_component_mapping(clamp_zs_swizzle(sampler_view->base.swizzle_b));
1054
1090
         ivci.components.a = zink_component_mapping(clamp_zs_swizzle(sampler_view->base.swizzle_a));
 
1091
 
 
1092
         /* If we're sampling depth and we might need to do shader rewrites for
 
1093
          * legacy shadow sampling, then set up an extra image view that just
 
1094
          * returns the red (depth) component, so you can always have the shadow
 
1095
          * result available in the red component for the in-shader swizzling.
 
1096
          * (Or if we have PVR's needs_zs_shader_swizzle and are sampling ONE
 
1097
          * value for stencil, which also uses that view).
 
1098
          */
1055
1099
         if (ivci.subresourceRange.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT ||
1056
1100
             zink_screen(ctx->base.screen)->driver_workarounds.needs_zs_shader_swizzle) {
1057
1101
            VkComponentSwizzle *swizzle = (VkComponentSwizzle*)&ivci.components;
1058
1102
            for (unsigned i = 0; i < 4; i++) {
1059
 
               /* these require shader rewrites to correctly emulate */
1060
1103
               if (swizzle[i] == VK_COMPONENT_SWIZZLE_ONE ||
1061
1104
                   (swizzle[i] == VK_COMPONENT_SWIZZLE_ZERO && ivci.subresourceRange.aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT))
1062
 
                  shadow_needs_shader_swizzle = true;
 
1105
                  red_depth_sampler_view = true;
1063
1106
            }
1064
1107
            /* this is the data that will be used in shader rewrites */
1065
1108
            sampler_view->swizzle.s[0] = clamp_zs_swizzle(sampler_view->base.swizzle_r);
1122
1165
      if (!screen->info.have_EXT_non_seamless_cube_map && viewtype_is_cube(&sampler_view->image_view->ivci)) {
1123
1166
         ivci.viewType = VK_IMAGE_VIEW_TYPE_2D_ARRAY;
1124
1167
         sampler_view->cube_array = (struct zink_surface*)zink_get_surface(ctx, pres, &templ, &ivci);
1125
 
      } else if (shadow_needs_shader_swizzle) {
 
1168
      } else if (red_depth_sampler_view) {
1126
1169
         /* there is only one component, and real swizzling can't be done here,
1127
1170
          * so ensure the shader gets the sampled data
1128
1171
          */
1192
1235
{
1193
1236
   /* TODO: handle this I guess */
1194
1237
   assert(zink_screen(ctx->screen)->info.props.limits.standardSampleLocations);
1195
 
   /* from 26.4. Multisampling */
1196
 
   switch (sample_count) {
1197
 
   case 0:
1198
 
   case 1: {
1199
 
      float pos[][2] = { {0.5,0.5}, };
1200
 
      out_value[0] = pos[sample_index][0];
1201
 
      out_value[1] = pos[sample_index][1];
1202
 
      break;
1203
 
   }
1204
 
   case 2: {
1205
 
      float pos[][2] = { {0.75,0.75},
1206
 
                        {0.25,0.25}, };
1207
 
      out_value[0] = pos[sample_index][0];
1208
 
      out_value[1] = pos[sample_index][1];
1209
 
      break;
1210
 
   }
1211
 
   case 4: {
1212
 
      float pos[][2] = { {0.375, 0.125},
1213
 
                        {0.875, 0.375},
1214
 
                        {0.125, 0.625},
1215
 
                        {0.625, 0.875}, };
1216
 
      out_value[0] = pos[sample_index][0];
1217
 
      out_value[1] = pos[sample_index][1];
1218
 
      break;
1219
 
   }
1220
 
   case 8: {
1221
 
      float pos[][2] = { {0.5625, 0.3125},
1222
 
                        {0.4375, 0.6875},
1223
 
                        {0.8125, 0.5625},
1224
 
                        {0.3125, 0.1875},
1225
 
                        {0.1875, 0.8125},
1226
 
                        {0.0625, 0.4375},
1227
 
                        {0.6875, 0.9375},
1228
 
                        {0.9375, 0.0625}, };
1229
 
      out_value[0] = pos[sample_index][0];
1230
 
      out_value[1] = pos[sample_index][1];
1231
 
      break;
1232
 
   }
1233
 
   case 16: {
1234
 
      float pos[][2] = { {0.5625, 0.5625},
1235
 
                        {0.4375, 0.3125},
1236
 
                        {0.3125, 0.625},
1237
 
                        {0.75, 0.4375},
1238
 
                        {0.1875, 0.375},
1239
 
                        {0.625, 0.8125},
1240
 
                        {0.8125, 0.6875},
1241
 
                        {0.6875, 0.1875},
1242
 
                        {0.375, 0.875},
1243
 
                        {0.5, 0.0625},
1244
 
                        {0.25, 0.125},
1245
 
                        {0.125, 0.75},
1246
 
                        {0.0, 0.5},
1247
 
                        {0.9375, 0.25},
1248
 
                        {0.875, 0.9375},
1249
 
                        {0.0625, 0.0}, };
1250
 
      out_value[0] = pos[sample_index][0];
1251
 
      out_value[1] = pos[sample_index][1];
1252
 
      break;
1253
 
   }
1254
 
   default:
1255
 
      unreachable("unhandled sample count!");
1256
 
   }
 
1238
   u_default_get_sample_position(ctx, sample_count, sample_index, out_value);
1257
1239
}
1258
1240
 
1259
1241
static void
1370
1352
      ctx->vp_state.viewport_states[start_slot + i] = state[i];
1371
1353
 
1372
1354
   ctx->vp_state_changed = true;
 
1355
   zink_flush_dgc_if_enabled(ctx);
1373
1356
}
1374
1357
 
1375
1358
static void
1382
1365
   for (unsigned i = 0; i < num_scissors; i++)
1383
1366
      ctx->vp_state.scissor_states[start_slot + i] = states[i];
1384
1367
   ctx->scissor_changed = true;
 
1368
   zink_flush_dgc_if_enabled(ctx);
1385
1369
}
1386
1370
 
1387
1371
static void
1454
1438
      ctx->compute_dirty = true;
1455
1439
      return;
1456
1440
   }
1457
 
   assert(!zink_screen(ctx->base.screen)->optimal_keys);
 
1441
   assert(!zink_screen(ctx->base.screen)->optimal_keys || (pstage == MESA_SHADER_GEOMETRY && ctx->is_generated_gs_bound));
1458
1442
   ctx->dirty_gfx_stages |= bit;
1459
1443
   struct zink_shader_key *key = &ctx->gfx_pipeline_state.shader_keys.key[pstage];
1460
1444
   key->inline_uniforms = false;
1535
1519
   }
1536
1520
 
1537
1521
   if (update)
1538
 
      zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, index, 1);
 
1522
      ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, index, 1);
1539
1523
}
1540
1524
 
1541
1525
ALWAYS_INLINE static void
1634
1618
   if (start_slot + count >= ctx->di.num_ssbos[p_stage])
1635
1619
      ctx->di.num_ssbos[p_stage] = max_slot + 1;
1636
1620
   if (update)
1637
 
      zink_context_invalidate_descriptor_state(ctx, p_stage, ZINK_DESCRIPTOR_TYPE_SSBO, start_slot, count);
 
1621
      ctx->invalidate_descriptor_state(ctx, p_stage, ZINK_DESCRIPTOR_TYPE_SSBO, start_slot, count);
1638
1622
}
1639
1623
 
1640
1624
static void
1645
1629
       u_foreach_bit(slot, res->sampler_binds[MESA_SHADER_COMPUTE]) {
1646
1630
          if (ctx->di.textures[MESA_SHADER_COMPUTE][slot].imageLayout != layout) {
1647
1631
             update_descriptor_state_sampler(ctx, MESA_SHADER_COMPUTE, slot, res);
1648
 
             zink_context_invalidate_descriptor_state(ctx, MESA_SHADER_COMPUTE, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
 
1632
             ctx->invalidate_descriptor_state(ctx, MESA_SHADER_COMPUTE, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
1649
1633
          }
1650
1634
       }
1651
1635
    } else {
1653
1637
          u_foreach_bit(slot, res->sampler_binds[i]) {
1654
1638
             if (ctx->di.textures[i][slot].imageLayout != layout) {
1655
1639
                update_descriptor_state_sampler(ctx, i, slot, res);
1656
 
                zink_context_invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
 
1640
                ctx->invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
1657
1641
             }
1658
1642
          }
1659
1643
       }
1793
1777
      break;
1794
1778
   default: break;
1795
1779
   }
1796
 
   if (!res->obj->dt && view->resource->format != view->format)
 
1780
   if (zink_format_needs_mutable(view->resource->format, view->format))
1797
1781
      /* mutable not set by default */
1798
1782
      zink_resource_object_init_mutable(ctx, res);
1799
1783
   VkImageViewCreateInfo ivci = create_ivci(screen, res, &tmpl, target);
1934
1918
   }
1935
1919
   ctx->di.num_images[shader_type] = start_slot + count;
1936
1920
   if (update)
1937
 
      zink_context_invalidate_descriptor_state(ctx, shader_type, ZINK_DESCRIPTOR_TYPE_IMAGE, start_slot, count);
 
1921
      ctx->invalidate_descriptor_state(ctx, shader_type, ZINK_DESCRIPTOR_TYPE_IMAGE, start_slot, count);
 
1922
}
 
1923
 
 
1924
static void
 
1925
update_feedback_loop_dynamic_state(struct zink_context *ctx)
 
1926
{
 
1927
   if (!zink_screen(ctx->base.screen)->info.have_EXT_attachment_feedback_loop_dynamic_state)
 
1928
      return;
 
1929
   VkImageAspectFlags aspects = 0;
 
1930
   if (ctx->feedback_loops & BITFIELD_MASK(PIPE_MAX_COLOR_BUFS))
 
1931
      aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
 
1932
   if (ctx->feedback_loops & BITFIELD_BIT(PIPE_MAX_COLOR_BUFS))
 
1933
      aspects |= VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
 
1934
   VKCTX(CmdSetAttachmentFeedbackLoopEnableEXT)(ctx->batch.state->cmdbuf, aspects);
1938
1935
}
1939
1936
 
1940
1937
static void
1950
1947
            ctx->gfx_pipeline_state.dirty = true;
1951
1948
         ctx->gfx_pipeline_state.feedback_loop = false;
1952
1949
      }
 
1950
      update_feedback_loop_dynamic_state(ctx);
1953
1951
   }
1954
1952
   ctx->feedback_loops = feedback_loops;
1955
1953
}
1996
1994
                       struct pipe_sampler_view **views)
1997
1995
{
1998
1996
   struct zink_context *ctx = zink_context(pctx);
1999
 
   unsigned i;
2000
1997
 
2001
1998
   const uint32_t mask = BITFIELD_RANGE(start_slot, num_views);
2002
1999
   uint32_t shadow_mask = ctx->di.zs_swizzle[shader_type].mask;
2004
2001
 
2005
2002
   bool update = false;
2006
2003
   bool shadow_update = false;
2007
 
   for (i = 0; i < num_views; ++i) {
2008
 
      struct pipe_sampler_view *pview = views ? views[i] : NULL;
2009
 
      struct zink_sampler_view *a = zink_sampler_view(ctx->sampler_views[shader_type][start_slot + i]);
2010
 
      struct zink_sampler_view *b = zink_sampler_view(pview);
2011
 
      struct zink_resource *res = b ? zink_resource(b->base.texture) : NULL;
2012
 
      if (b && b->base.texture) {
2013
 
         if (!a || zink_resource(a->base.texture) != res) {
2014
 
            if (a)
2015
 
               unbind_samplerview(ctx, shader_type, start_slot + i);
2016
 
            update_res_bind_count(ctx, res, shader_type == MESA_SHADER_COMPUTE, false);
2017
 
            res->sampler_bind_count[shader_type == MESA_SHADER_COMPUTE]++;
2018
 
            res->gfx_barrier |= zink_pipeline_flags_from_pipe_stage(shader_type);
2019
 
            res->barrier_access[shader_type == MESA_SHADER_COMPUTE] |= VK_ACCESS_SHADER_READ_BIT;
 
2004
   if (views) {
 
2005
      for (unsigned i = 0; i < num_views; ++i) {
 
2006
         struct pipe_sampler_view *pview = views[i];
 
2007
         struct zink_sampler_view *a = zink_sampler_view(ctx->sampler_views[shader_type][start_slot + i]);
 
2008
         struct zink_sampler_view *b = zink_sampler_view(pview);
 
2009
 
 
2010
         if (a == b) {
 
2011
            if (take_ownership) {
 
2012
               struct pipe_sampler_view *view = views[i];
 
2013
               pipe_sampler_view_reference(&view, NULL);
 
2014
            }
 
2015
            continue;
2020
2016
         }
2021
 
         if (res->base.b.target == PIPE_BUFFER) {
2022
 
            if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
2023
 
               if (!a || a->base.texture != b->base.texture || zink_resource(a->base.texture)->obj != res->obj ||
2024
 
                   memcmp(&a->base.u.buf, &b->base.u.buf, sizeof(b->base.u.buf)))
2025
 
                  update = true;
2026
 
            } else if (b->buffer_view->bvci.buffer != res->obj->buffer) {
2027
 
               /* if this resource has been rebound while it wasn't set here,
2028
 
                * its backing resource will have changed and thus we need to update
2029
 
                * the bufferview
2030
 
                */
2031
 
               VkBufferViewCreateInfo bvci = b->buffer_view->bvci;
2032
 
               bvci.buffer = res->obj->buffer;
2033
 
               struct zink_buffer_view *buffer_view = get_buffer_view(ctx, res, &bvci);
2034
 
               assert(buffer_view != b->buffer_view);
2035
 
               zink_buffer_view_reference(zink_screen(ctx->base.screen), &b->buffer_view, NULL);
2036
 
               b->buffer_view = buffer_view;
2037
 
               update = true;
2038
 
            } else if (!a || a->buffer_view->buffer_view != b->buffer_view->buffer_view)
2039
 
                  update = true;
2040
 
            zink_screen(ctx->base.screen)->buffer_barrier(ctx, res, VK_ACCESS_SHADER_READ_BIT,
2041
 
                                         res->gfx_barrier);
2042
 
            zink_batch_resource_usage_set(&ctx->batch, res, false, true);
2043
 
            if (!ctx->unordered_blitting)
2044
 
               res->obj->unordered_read = false;
2045
 
         } else if (!res->obj->is_buffer) {
2046
 
            if (!res->obj->dt && res->base.b.format != b->image_view->base.format)
2047
 
               /* mutable not set by default */
2048
 
               zink_resource_object_init_mutable(ctx, res);
2049
 
            if (res->obj != b->image_view->obj) {
2050
 
               struct pipe_surface *psurf = &b->image_view->base;
2051
 
               VkImageView iv = b->image_view->image_view;
2052
 
               zink_rebind_surface(ctx, &psurf);
2053
 
               b->image_view = zink_surface(psurf);
2054
 
               update |= iv != b->image_view->image_view;
2055
 
            } else  if (a != b)
2056
 
               update = true;
2057
 
            if (shader_type == MESA_SHADER_COMPUTE)
2058
 
               flush_pending_clears(ctx, res);
2059
 
            if (b->cube_array) {
2060
 
               ctx->di.cubes[shader_type] |= BITFIELD_BIT(start_slot + i);
2061
 
            }
2062
 
            if (!check_for_layout_update(ctx, res, shader_type == MESA_SHADER_COMPUTE) && !ctx->unordered_blitting) {
2063
 
               /* no deferred barrier: unset unordered usage immediately */
2064
 
               res->obj->unordered_read = false;
2065
 
               // TODO: figure out a way to link up layouts between unordered and main cmdbuf
2066
 
               res->obj->unordered_write = false;
2067
 
            }
2068
 
            if (!a)
2069
 
               update = true;
2070
 
            zink_batch_resource_usage_set(&ctx->batch, res, false, false);
2071
 
            if (b->zs_view) {
2072
 
               assert(start_slot + i < 32); //bitfield size
2073
 
               ctx->di.zs_swizzle[shader_type].mask |= BITFIELD_BIT(start_slot + i);
2074
 
               /* this is already gonna be slow, so don't bother trying to micro-optimize */
2075
 
               shadow_update |= memcmp(&ctx->di.zs_swizzle[shader_type].swizzle[start_slot + i],
2076
 
                                       &b->swizzle, sizeof(struct zink_zs_swizzle));
2077
 
               memcpy(&ctx->di.zs_swizzle[shader_type].swizzle[start_slot + i], &b->swizzle, sizeof(struct zink_zs_swizzle));
 
2017
 
 
2018
         struct zink_resource *res = b ? zink_resource(b->base.texture) : NULL;
 
2019
         if (b && b->base.texture) {
 
2020
            if (!a || zink_resource(a->base.texture) != res) {
 
2021
               if (a)
 
2022
                  unbind_samplerview(ctx, shader_type, start_slot + i);
 
2023
               update_res_bind_count(ctx, res, shader_type == MESA_SHADER_COMPUTE, false);
 
2024
               res->sampler_bind_count[shader_type == MESA_SHADER_COMPUTE]++;
 
2025
               res->gfx_barrier |= zink_pipeline_flags_from_pipe_stage(shader_type);
 
2026
               res->barrier_access[shader_type == MESA_SHADER_COMPUTE] |= VK_ACCESS_SHADER_READ_BIT;
 
2027
            }
 
2028
            if (res->base.b.target == PIPE_BUFFER) {
 
2029
               if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
 
2030
                  if (!a || a->base.texture != b->base.texture || zink_resource(a->base.texture)->obj != res->obj ||
 
2031
                     memcmp(&a->base.u.buf, &b->base.u.buf, sizeof(b->base.u.buf)))
 
2032
                     update = true;
 
2033
               } else if (b->buffer_view->bvci.buffer != res->obj->buffer) {
 
2034
                  /* if this resource has been rebound while it wasn't set here,
 
2035
                  * its backing resource will have changed and thus we need to update
 
2036
                  * the bufferview
 
2037
                  */
 
2038
                  VkBufferViewCreateInfo bvci = b->buffer_view->bvci;
 
2039
                  bvci.buffer = res->obj->buffer;
 
2040
                  struct zink_buffer_view *buffer_view = get_buffer_view(ctx, res, &bvci);
 
2041
                  assert(buffer_view != b->buffer_view);
 
2042
                  zink_buffer_view_reference(zink_screen(ctx->base.screen), &b->buffer_view, NULL);
 
2043
                  b->buffer_view = buffer_view;
 
2044
                  update = true;
 
2045
               } else if (!a || a->buffer_view->buffer_view != b->buffer_view->buffer_view)
 
2046
                     update = true;
 
2047
               zink_screen(ctx->base.screen)->buffer_barrier(ctx, res, VK_ACCESS_SHADER_READ_BIT,
 
2048
                                          res->gfx_barrier);
 
2049
               zink_batch_resource_usage_set(&ctx->batch, res, false, true);
 
2050
               if (!ctx->unordered_blitting)
 
2051
                  res->obj->unordered_read = false;
2078
2052
            } else {
2079
 
               assert(start_slot + i < 32); //bitfield size
2080
 
               ctx->di.zs_swizzle[shader_type].mask &= ~BITFIELD_BIT(start_slot + i);
 
2053
               if (zink_format_needs_mutable(res->base.b.format, b->image_view->base.format))
 
2054
                  /* mutable not set by default */
 
2055
                  zink_resource_object_init_mutable(ctx, res);
 
2056
               if (res->obj != b->image_view->obj) {
 
2057
                  struct pipe_surface *psurf = &b->image_view->base;
 
2058
                  VkImageView iv = b->image_view->image_view;
 
2059
                  zink_rebind_surface(ctx, &psurf);
 
2060
                  b->image_view = zink_surface(psurf);
 
2061
                  update |= iv != b->image_view->image_view;
 
2062
               } else  if (a != b)
 
2063
                  update = true;
 
2064
               if (shader_type == MESA_SHADER_COMPUTE)
 
2065
                  flush_pending_clears(ctx, res);
 
2066
               if (b->cube_array) {
 
2067
                  ctx->di.cubes[shader_type] |= BITFIELD_BIT(start_slot + i);
 
2068
               }
 
2069
               if (!check_for_layout_update(ctx, res, shader_type == MESA_SHADER_COMPUTE) && !ctx->unordered_blitting) {
 
2070
                  /* no deferred barrier: unset unordered usage immediately */
 
2071
                  res->obj->unordered_read = false;
 
2072
                  // TODO: figure out a way to link up layouts between unordered and main cmdbuf
 
2073
                  res->obj->unordered_write = false;
 
2074
               }
 
2075
               if (!a)
 
2076
                  update = true;
 
2077
               zink_batch_resource_usage_set(&ctx->batch, res, false, false);
 
2078
               if (b->zs_view) {
 
2079
                  assert(start_slot + i < 32); //bitfield size
 
2080
                  ctx->di.zs_swizzle[shader_type].mask |= BITFIELD_BIT(start_slot + i);
 
2081
                  /* this is already gonna be slow, so don't bother trying to micro-optimize */
 
2082
                  shadow_update |= memcmp(&ctx->di.zs_swizzle[shader_type].swizzle[start_slot + i],
 
2083
                                          &b->swizzle, sizeof(struct zink_zs_swizzle));
 
2084
                  memcpy(&ctx->di.zs_swizzle[shader_type].swizzle[start_slot + i], &b->swizzle, sizeof(struct zink_zs_swizzle));
 
2085
               } else {
 
2086
                  assert(start_slot + i < 32); //bitfield size
 
2087
                  ctx->di.zs_swizzle[shader_type].mask &= ~BITFIELD_BIT(start_slot + i);
 
2088
               }
2081
2089
            }
2082
 
         }
2083
 
         res->sampler_binds[shader_type] |= BITFIELD_BIT(start_slot + i);
2084
 
      } else if (a) {
2085
 
         unbind_samplerview(ctx, shader_type, start_slot + i);
2086
 
         update = true;
2087
 
      }
2088
 
      if (take_ownership) {
2089
 
         pipe_sampler_view_reference(&ctx->sampler_views[shader_type][start_slot + i], NULL);
2090
 
         ctx->sampler_views[shader_type][start_slot + i] = pview;
2091
 
      } else {
2092
 
         pipe_sampler_view_reference(&ctx->sampler_views[shader_type][start_slot + i], pview);
2093
 
      }
2094
 
      update_descriptor_state_sampler(ctx, shader_type, start_slot + i, res);
 
2090
            res->sampler_binds[shader_type] |= BITFIELD_BIT(start_slot + i);
 
2091
         } else if (a) {
 
2092
            unbind_samplerview(ctx, shader_type, start_slot + i);
 
2093
            update = true;
 
2094
         }
 
2095
         if (take_ownership) {
 
2096
            pipe_sampler_view_reference(&ctx->sampler_views[shader_type][start_slot + i], NULL);
 
2097
            ctx->sampler_views[shader_type][start_slot + i] = pview;
 
2098
         } else {
 
2099
            pipe_sampler_view_reference(&ctx->sampler_views[shader_type][start_slot + i], pview);
 
2100
         }
 
2101
         update_descriptor_state_sampler(ctx, shader_type, start_slot + i, res);
 
2102
      }
 
2103
   } else {
 
2104
      unbind_num_trailing_slots += num_views;
 
2105
      num_views = 0;
2095
2106
   }
2096
 
   for (; i < num_views + unbind_num_trailing_slots; ++i) {
2097
 
      update |= !!ctx->sampler_views[shader_type][start_slot + i];
2098
 
      unbind_samplerview(ctx, shader_type, start_slot + i);
 
2107
   for (unsigned i = 0; i < unbind_num_trailing_slots; ++i) {
 
2108
      unsigned slot = start_slot + num_views + i;
 
2109
      update |= !!ctx->sampler_views[shader_type][slot];
 
2110
      unbind_samplerview(ctx, shader_type, slot);
2099
2111
      pipe_sampler_view_reference(
2100
 
         &ctx->sampler_views[shader_type][start_slot + i],
 
2112
         &ctx->sampler_views[shader_type][slot],
2101
2113
         NULL);
2102
 
      update_descriptor_state_sampler(ctx, shader_type, start_slot + i, NULL);
 
2114
      update_descriptor_state_sampler(ctx, shader_type, slot, NULL);
2103
2115
   }
2104
2116
   ctx->di.num_sampler_views[shader_type] = start_slot + num_views;
2105
2117
   if (update) {
2106
2118
      struct zink_screen *screen = zink_screen(pctx->screen);
2107
 
      zink_context_invalidate_descriptor_state(ctx, shader_type, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot, num_views);
 
2119
      ctx->invalidate_descriptor_state(ctx, shader_type, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, start_slot, num_views);
2108
2120
      if (!screen->info.have_EXT_non_seamless_cube_map)
2109
2121
         update_nonseamless_shader_key(ctx, shader_type);
2110
2122
      shadow_update |= shadow_mask != ctx->di.zs_swizzle[shader_type].mask;
2277
2289
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
2278
2290
            ctx->di.bindless[0].db.buffer_infos[handle].address = res->obj->bda + ds->db.offset;
2279
2291
            ctx->di.bindless[0].db.buffer_infos[handle].range = ds->db.size;
2280
 
            ctx->di.bindless[0].db.buffer_infos[handle].format = ds->db.format;
 
2292
            ctx->di.bindless[0].db.buffer_infos[handle].format = zink_get_format(zink_screen(ctx->base.screen), ds->db.format);
2281
2293
         } else {
2282
2294
            if (ds->bufferview->bvci.buffer != res->obj->buffer)
2283
2295
               rebind_bindless_bufferview(ctx, res, ds);
2419
2431
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
2420
2432
            ctx->di.bindless[0].db.buffer_infos[handle].address = res->obj->bda + ds->db.offset;
2421
2433
            ctx->di.bindless[0].db.buffer_infos[handle].range = ds->db.size;
2422
 
            ctx->di.bindless[0].db.buffer_infos[handle].format = ds->db.format;
 
2434
            ctx->di.bindless[0].db.buffer_infos[handle].format = zink_get_format(zink_screen(ctx->base.screen), ds->db.format);
2423
2435
         } else {
2424
2436
            if (ds->bufferview->bvci.buffer != res->obj->buffer)
2425
2437
               rebind_bindless_bufferview(ctx, res, ds);
2493
2505
         VKCTX(CmdSetPatchControlPointsEXT)(ctx->batch.state->cmdbuf, patch_vertices);
2494
2506
      else
2495
2507
         ctx->gfx_pipeline_state.dirty = true;
 
2508
      zink_flush_dgc_if_enabled(ctx);
2496
2509
   }
2497
2510
}
2498
2511
 
2510
2523
      ctx->di.fbfetch.imageView = zink_screen(ctx->base.screen)->info.rb2_feats.nullDescriptor ?
2511
2524
                                  VK_NULL_HANDLE :
2512
2525
                                  zink_get_dummy_surface(ctx, 0)->image_view;
2513
 
      zink_context_invalidate_descriptor_state(ctx, MESA_SHADER_FRAGMENT, ZINK_DESCRIPTOR_TYPE_UBO, 0, 1);
 
2526
      ctx->invalidate_descriptor_state(ctx, MESA_SHADER_FRAGMENT, ZINK_DESCRIPTOR_TYPE_UBO, 0, 1);
2514
2527
      return;
2515
2528
   }
2516
2529
 
2529
2542
   }
2530
2543
   ctx->di.fbfetch.imageLayout = VK_IMAGE_LAYOUT_GENERAL;
2531
2544
   if (changed) {
2532
 
      zink_context_invalidate_descriptor_state(ctx, MESA_SHADER_FRAGMENT, ZINK_DESCRIPTOR_TYPE_UBO, 0, 1);
 
2545
      ctx->invalidate_descriptor_state(ctx, MESA_SHADER_FRAGMENT, ZINK_DESCRIPTOR_TYPE_UBO, 0, 1);
2533
2546
      if (!had_fbfetch) {
2534
2547
         ctx->rp_changed = true;
2535
2548
         zink_batch_no_rp(ctx);
2772
2785
      ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS+1].imageView = iv;
2773
2786
      ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS+1].imageLayout = zink_resource(surf->base.texture)->layout;
2774
2787
      assert(ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS+1].imageLayout != VK_IMAGE_LAYOUT_UNDEFINED);
 
2788
      if (ctx->transient_attachments & BITFIELD_BIT(PIPE_MAX_COLOR_BUFS)) {
 
2789
         ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS].resolveMode = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT;
 
2790
         ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS + 1].resolveMode = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT;
 
2791
      } else {
 
2792
         ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS].resolveMode = 0;
 
2793
         ctx->dynamic_fb.attachments[PIPE_MAX_COLOR_BUFS + 1].resolveMode = 0;
 
2794
      }
2775
2795
   }
2776
2796
   ctx->zsbuf_unused = !zsbuf_used;
2777
2797
   assert(ctx->fb_state.width >= ctx->dynamic_fb.info.renderArea.extent.width);
2786
2806
      ctx->gfx_pipeline_state.rast_samples + 1,
2787
2807
   };
2788
2808
 
2789
 
   ctx->dynamic_fb.info.pNext = ctx->transient_attachments ? &msrtss : NULL;
 
2809
   if (zink_screen(ctx->base.screen)->info.have_EXT_multisampled_render_to_single_sampled)
 
2810
      ctx->dynamic_fb.info.pNext = ctx->transient_attachments ? &msrtss : NULL;
2790
2811
   assert(!ctx->transient_attachments || msrtss.rasterizationSamples != VK_SAMPLE_COUNT_1_BIT);
2791
2812
   VKCTX(CmdBeginRendering)(ctx->batch.state->cmdbuf, &ctx->dynamic_fb.info);
2792
2813
   ctx->batch.in_rp = true;
2807
2828
         &framebffer_is_layered);
2808
2829
}
2809
2830
 
 
2831
ALWAYS_INLINE static void
 
2832
batch_ref_fb_surface(struct zink_context *ctx, struct pipe_surface *psurf)
 
2833
{
 
2834
   if (!psurf)
 
2835
      return;
 
2836
   zink_batch_reference_resource(&ctx->batch, zink_resource(psurf->texture));
 
2837
   struct zink_surface *transient = zink_transient_surface(psurf);
 
2838
   if (transient)
 
2839
      zink_batch_reference_resource(&ctx->batch, zink_resource(transient->base.texture));
 
2840
}
 
2841
 
2810
2842
void
2811
2843
zink_batch_rp(struct zink_context *ctx)
2812
2844
{
2813
2845
   assert(!(ctx->batch.in_rp && ctx->rp_changed));
 
2846
   if (!ctx->track_renderpasses && !ctx->blitting) {
 
2847
      if (ctx->rp_tc_info_updated)
 
2848
         zink_parse_tc_info(ctx);
 
2849
   }
2814
2850
   if (ctx->batch.in_rp && !ctx->rp_layout_changed)
2815
2851
      return;
2816
2852
   bool in_rp = ctx->batch.in_rp;
2861
2897
         zink_start_conditional_render(ctx);
2862
2898
      zink_clear_framebuffer(ctx, clear_buffers);
2863
2899
      if (ctx->pipeline_changed[0]) {
2864
 
         for (unsigned i = 0; i < ctx->fb_state.nr_cbufs; i++) {
2865
 
            if (ctx->fb_state.cbufs[i])
2866
 
               zink_batch_reference_resource(&ctx->batch, zink_resource(ctx->fb_state.cbufs[i]->texture));
2867
 
         }
2868
 
         if (ctx->fb_state.zsbuf)
2869
 
            zink_batch_reference_resource(&ctx->batch, zink_resource(ctx->fb_state.zsbuf->texture));
 
2900
         for (unsigned i = 0; i < ctx->fb_state.nr_cbufs; i++)
 
2901
            batch_ref_fb_surface(ctx, ctx->fb_state.cbufs[i]);
 
2902
         batch_ref_fb_surface(ctx, ctx->fb_state.zsbuf);
2870
2903
      }
2871
2904
   }
2872
2905
   /* unable to previously determine that queries didn't split renderpasses: ensure queries start inside renderpass */
2881
2914
{
2882
2915
   if (!ctx->batch.in_rp)
2883
2916
      return;
 
2917
   zink_flush_dgc_if_enabled(ctx);
2884
2918
   if (ctx->render_condition.query)
2885
2919
      zink_stop_conditional_render(ctx);
2886
2920
   /* suspend all queries that were started in a renderpass
3121
3155
               continue;
3122
3156
            bool is_buffer = res->obj->is_buffer;
3123
3157
            bool is_write = zink_resource_access_is_write(get_access_flags_for_binding(ctx, i, stage, j));
 
3158
            if (zink_is_swapchain(res)) {
 
3159
               if (!zink_kopper_acquire(ctx, res, UINT64_MAX))
 
3160
                  /* technically this is a failure condition, but there's no safe way out */
 
3161
                  continue;
 
3162
            }
3124
3163
            zink_batch_resource_usage_set(batch, res, is_write, is_buffer);
3125
3164
            if (is_write || !res->obj->is_buffer)
3126
3165
               res->obj->unordered_read = res->obj->unordered_write = false;
3189
3228
{
3190
3229
   struct zink_screen *screen = zink_screen(ctx->base.screen);
3191
3230
   sync_flush(ctx, zink_batch_state(ctx->last_fence));
3192
 
   zink_screen_timeline_wait(screen, ctx->last_fence->batch_id, PIPE_TIMEOUT_INFINITE);
 
3231
   zink_screen_timeline_wait(screen, ctx->last_fence->batch_id, OS_TIMEOUT_INFINITE);
3193
3232
   zink_batch_reset_all(ctx);
3194
3233
}
3195
3234
 
3201
3240
   if (ctx->clears_enabled)
3202
3241
      /* start rp to do all the clears */
3203
3242
      zink_batch_rp(ctx);
3204
 
   bool conditional_render_active = ctx->render_condition.active;
3205
 
   zink_stop_conditional_render(ctx);
3206
3243
   zink_batch_no_rp_safe(ctx);
3207
3244
   zink_end_batch(ctx, batch);
3208
3245
   ctx->deferred_fence = NULL;
3213
3250
   if (ctx->batch.state->is_device_lost) {
3214
3251
      check_device_lost(ctx);
3215
3252
   } else {
 
3253
      struct zink_screen *screen = zink_screen(ctx->base.screen);
3216
3254
      zink_start_batch(ctx, batch);
3217
 
      if (zink_screen(ctx->base.screen)->info.have_EXT_transform_feedback && ctx->num_so_targets)
 
3255
      if (screen->info.have_EXT_transform_feedback && ctx->num_so_targets)
3218
3256
         ctx->dirty_so_targets = true;
3219
3257
      ctx->pipeline_changed[0] = ctx->pipeline_changed[1] = true;
3220
3258
      zink_select_draw_vbo(ctx);
3222
3260
 
3223
3261
      if (ctx->oom_stall)
3224
3262
         stall(ctx);
 
3263
      if (screen->info.have_EXT_extended_dynamic_state3) {
 
3264
         if (screen->have_full_ds3)
 
3265
            ctx->ds3_states = UINT32_MAX;
 
3266
         else
 
3267
            ctx->ds3_states = BITFIELD_MASK(ZINK_DS3_BLEND_A2C);
 
3268
         if (!screen->info.dynamic_state3_feats.extendedDynamicState3AlphaToOneEnable)
 
3269
            ctx->ds3_states &= ~BITFIELD_BIT(ZINK_DS3_BLEND_A21);
 
3270
         if (!screen->info.dynamic_state3_feats.extendedDynamicState3LineStippleEnable)
 
3271
            ctx->ds3_states &= ~BITFIELD_BIT(ZINK_DS3_RAST_STIPPLE_ON);
 
3272
         if (screen->driver_workarounds.no_linestipple)
 
3273
            ctx->ds3_states &= ~BITFIELD_BIT(ZINK_DS3_RAST_STIPPLE);
 
3274
      }
3225
3275
      ctx->oom_flush = false;
3226
3276
      ctx->oom_stall = false;
3227
3277
      ctx->dd.bindless_bound = false;
3231
3281
         VKCTX(CmdSetPatchControlPointsEXT)(ctx->batch.state->cmdbuf, ctx->gfx_pipeline_state.dyn_state2.vertices_per_patch);
3232
3282
         VKCTX(CmdSetPatchControlPointsEXT)(ctx->batch.state->barrier_cmdbuf, 1);
3233
3283
      }
3234
 
      if (conditional_render_active)
3235
 
         zink_start_conditional_render(ctx);
 
3284
      update_feedback_loop_dynamic_state(ctx);
3236
3285
      reapply_color_write(ctx);
3237
3286
      update_layered_rendering_state(ctx);
3238
3287
      tc_renderpass_info_reset(&ctx->dynamic_fb.tc_info);
3416
3465
   /* renderpass changes if the number or types of attachments change */
3417
3466
   ctx->rp_changed |= ctx->fb_state.nr_cbufs != state->nr_cbufs;
3418
3467
   ctx->rp_changed |= !!ctx->fb_state.zsbuf != !!state->zsbuf;
3419
 
   if (ctx->fb_state.nr_cbufs != state->nr_cbufs)
 
3468
   if (ctx->fb_state.nr_cbufs != state->nr_cbufs) {
3420
3469
      ctx->blend_state_changed |= screen->have_full_ds3;
 
3470
      if (state->nr_cbufs && screen->have_full_ds3)
 
3471
         ctx->ds3_states |= BITFIELD_BIT(ZINK_DS3_BLEND_ON) | BITFIELD_BIT(ZINK_DS3_BLEND_WRITE) | BITFIELD_BIT(ZINK_DS3_BLEND_EQ);
 
3472
   }
3421
3473
 
3422
3474
   util_copy_framebuffer_state(&ctx->fb_state, state);
3423
3475
   zink_update_fbfetch(ctx);
3463
3515
         }
3464
3516
         res->fb_bind_count++;
3465
3517
         res->fb_binds |= BITFIELD_BIT(i);
3466
 
         zink_batch_reference_resource(&ctx->batch, res);
 
3518
         batch_ref_fb_surface(ctx, ctx->fb_state.cbufs[i]);
3467
3519
         if (util_format_has_alpha1(psurf->format)) {
3468
3520
            if (!res->valid && !zink_fb_clear_full_exists(ctx, i))
3469
3521
               ctx->void_clears |= (PIPE_CLEAR_COLOR0 << i);
3475
3527
      struct pipe_surface *psurf = ctx->fb_state.zsbuf;
3476
3528
      struct zink_surface *transient = zink_transient_surface(psurf);
3477
3529
      check_framebuffer_surface_mutable(pctx, psurf);
3478
 
      zink_batch_reference_resource(&ctx->batch, zink_resource(psurf->texture));
 
3530
      batch_ref_fb_surface(ctx, ctx->fb_state.zsbuf);
3479
3531
      if (transient || psurf->nr_samples)
3480
3532
         ctx->transient_attachments |= BITFIELD_BIT(PIPE_MAX_COLOR_BUFS);
3481
3533
      if (!samples)
3520
3572
      zink_update_fs_key_samples(ctx);
3521
3573
   if (ctx->gfx_pipeline_state.rast_samples != rast_samples) {
3522
3574
      ctx->sample_locations_changed |= ctx->gfx_pipeline_state.sample_locations_enabled;
 
3575
      zink_flush_dgc_if_enabled(ctx);
3523
3576
      if (screen->have_full_ds3)
3524
3577
         ctx->sample_mask_changed = true;
3525
3578
      else
3542
3595
{
3543
3596
   struct zink_context *ctx = zink_context(pctx);
3544
3597
   memcpy(ctx->blend_constants, color->color, sizeof(float) * 4);
 
3598
   zink_flush_dgc_if_enabled(ctx);
3545
3599
}
3546
3600
 
3547
3601
static void
3548
3602
zink_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
3549
3603
{
3550
3604
   struct zink_context *ctx = zink_context(pctx);
 
3605
   if (ctx->gfx_pipeline_state.sample_mask == sample_mask)
 
3606
      return;
3551
3607
   ctx->gfx_pipeline_state.sample_mask = sample_mask;
 
3608
   zink_flush_dgc_if_enabled(ctx);
3552
3609
   if (zink_screen(pctx->screen)->have_full_ds3)
3553
3610
      ctx->sample_mask_changed = true;
3554
3611
   else
3561
3618
   struct zink_context *ctx = zink_context(pctx);
3562
3619
   ctx->gfx_pipeline_state.min_samples = min_samples - 1;
3563
3620
   ctx->gfx_pipeline_state.dirty = true;
 
3621
   zink_flush_dgc_if_enabled(ctx);
3564
3622
}
3565
3623
 
3566
3624
static void
3575
3633
 
3576
3634
   if (locations)
3577
3635
      memcpy(ctx->sample_locations, locations, size);
 
3636
   zink_flush_dgc_if_enabled(ctx);
3578
3637
}
3579
3638
 
3580
3639
static void
3663
3722
         tc_driver_internal_flush_notify(ctx->tc);
3664
3723
   } else {
3665
3724
      fence = &batch->state->fence;
3666
 
      submit_count = batch->state->submit_count;
 
3725
      submit_count = batch->state->usage.submit_count;
3667
3726
      if (deferred && !(flags & PIPE_FLUSH_FENCE_FD) && pfence)
3668
3727
         deferred_fence = true;
3669
3728
      else
4001
4060
      /* TODO: possibly avoid rebinding on resume if resuming from same buffers? */
4002
4061
      ctx->dirty_so_targets = true;
4003
4062
   }
 
4063
   zink_flush_dgc_if_enabled(ctx);
4004
4064
}
4005
4065
 
4006
4066
void
4044
4104
      res->obj->unordered_read = false;
4045
4105
      res->obj->access |= VK_ACCESS_SHADER_READ_BIT;
4046
4106
   }
4047
 
   zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, slot, 1);
 
4107
   ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_UBO, slot, 1);
4048
4108
   return res;
4049
4109
}
4050
4110
 
4066
4126
         res->obj->access |= VK_ACCESS_SHADER_WRITE_BIT;
4067
4127
      }
4068
4128
   }
4069
 
   zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SSBO, slot, 1);
 
4129
   ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SSBO, slot, 1);
4070
4130
   return res;
4071
4131
}
4072
4132
 
4088
4148
      res->obj->unordered_read = false;
4089
4149
      res->obj->access |= VK_ACCESS_SHADER_READ_BIT;
4090
4150
   }
4091
 
   zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
 
4151
   ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, slot, 1);
4092
4152
   return res;
4093
4153
}
4094
4154
 
4124
4184
   util_range_add(&res->base.b, &res->valid_buffer_range, image_view->base.u.buf.offset,
4125
4185
                  image_view->base.u.buf.offset + image_view->base.u.buf.size);
4126
4186
   update_descriptor_state_image(ctx, shader, slot, res);
4127
 
   zink_context_invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_IMAGE, slot, 1);
 
4187
   ctx->invalidate_descriptor_state(ctx, shader, ZINK_DESCRIPTOR_TYPE_IMAGE, slot, 1);
4128
4188
   return res;
4129
4189
}
4130
4190
 
4436
4496
   struct zink_resource *src = zink_resource(psrc);
4437
4497
   struct zink_context *ctx = zink_context(pctx);
4438
4498
   if (dst->base.b.target != PIPE_BUFFER && src->base.b.target != PIPE_BUFFER) {
4439
 
      VkImageCopy region = {0};
 
4499
      VkImageCopy region;
 
4500
      /* fill struct holes */
 
4501
      memset(&region, 0, sizeof(region));
4440
4502
      if (util_format_get_num_planes(src->base.b.format) == 1 &&
4441
4503
          util_format_get_num_planes(dst->base.b.format) == 1) {
4442
4504
      /* If neither the calling command’s srcImage nor the calling command’s dstImage
4449
4511
      } else
4450
4512
         unreachable("planar formats not yet handled");
4451
4513
 
4452
 
      zink_fb_clears_apply_or_discard(ctx, pdst, (struct u_rect){dstx, dstx + src_box->width, dsty, dsty + src_box->height}, false);
4453
 
      zink_fb_clears_apply_region(ctx, psrc, zink_rect_from_box(src_box));
4454
4514
 
4455
4515
      region.srcSubresource.aspectMask = src->aspect;
4456
4516
      region.srcSubresource.mipLevel = src_level;
4519
4579
      region.extent.width = src_box->width;
4520
4580
      region.extent.height = src_box->height;
4521
4581
 
 
4582
      /* ignore no-op copies */
 
4583
      if (src == dst &&
 
4584
          !memcmp(&region.dstOffset, &region.srcOffset, sizeof(region.srcOffset)) &&
 
4585
          !memcmp(&region.dstSubresource, &region.srcSubresource, sizeof(region.srcSubresource)))
 
4586
         return;
 
4587
 
 
4588
      zink_fb_clears_apply_or_discard(ctx, pdst, (struct u_rect){dstx, dstx + src_box->width, dsty, dsty + src_box->height}, false);
 
4589
      zink_fb_clears_apply_region(ctx, psrc, zink_rect_from_box(src_box));
 
4590
 
4522
4591
      struct zink_batch *batch = &ctx->batch;
4523
4592
      zink_resource_setup_transfer_layouts(ctx, src, dst);
4524
4593
      VkCommandBuffer cmdbuf = zink_get_cmdbuf(ctx, src, dst);
4594
4663
               struct pipe_surface *psurf = &sv->image_view->base;
4595
4664
               zink_rebind_surface(ctx, &psurf);
4596
4665
               sv->image_view = zink_surface(psurf);
4597
 
               zink_context_invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, j, 1);
 
4666
               ctx->invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, j, 1);
4598
4667
               update_descriptor_state_sampler(ctx, i, j, res);
4599
4668
            }
4600
4669
         }
4603
4672
         continue;
4604
4673
      for (unsigned j = 0; j < ctx->di.num_images[i]; j++) {
4605
4674
         if (zink_resource(ctx->image_views[i][j].base.resource) == res) {
4606
 
            zink_context_invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_IMAGE, j, 1);
 
4675
            ctx->invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_IMAGE, j, 1);
4607
4676
            update_descriptor_state_image(ctx, i, j, res);
4608
4677
            _mesa_set_add(ctx->need_barriers[i == MESA_SHADER_COMPUTE], res);
4609
4678
         }
4671
4740
             struct pipe_surface *psurf = &sv->image_view->base;
4672
4741
             zink_rebind_surface(ctx, &psurf);
4673
4742
             sv->image_view = zink_surface(psurf);
4674
 
             zink_context_invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, j, 1);
 
4743
             ctx->invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW, j, 1);
4675
4744
             update_descriptor_state_sampler(ctx, i, j, res);
4676
4745
         }
4677
4746
      }
4683
4752
         if (ctx->image_views[i][j].surface->obj != res->obj) {
4684
4753
            zink_surface_reference(zink_screen(ctx->base.screen), &image_view->surface, NULL);
4685
4754
            image_view->surface = create_image_surface(ctx, &image_view->base, i == MESA_SHADER_COMPUTE);
4686
 
            zink_context_invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_IMAGE, j, 1);
 
4755
            ctx->invalidate_descriptor_state(ctx, i, ZINK_DESCRIPTOR_TYPE_IMAGE, j, 1);
4687
4756
            update_descriptor_state_image(ctx, i, j, res);
4688
4757
            _mesa_set_add(ctx->need_barriers[i == MESA_SHADER_COMPUTE], res);
4689
4758
         }
4705
4774
   assert(d->obj);
4706
4775
   assert(s->obj);
4707
4776
   util_idalloc_mt_free(&screen->buffer_ids, delete_buffer_id);
4708
 
   /* add a ref just like check_resource_for_batch_ref() would've */
4709
 
   if (zink_resource_has_binds(d) && zink_resource_has_usage(d))
4710
 
      zink_batch_reference_resource(&ctx->batch, d);
 
4777
   zink_batch_reference_resource(&ctx->batch, d);
4711
4778
   /* don't be too creative */
4712
4779
   zink_resource_object_reference(screen, &d->obj, s->obj);
4713
4780
   d->valid_buffer_range = s->valid_buffer_range;
4756
4823
   free(temp);
4757
4824
}
4758
4825
 
 
4826
VkIndirectCommandsLayoutTokenNV *
 
4827
zink_dgc_add_token(struct zink_context *ctx, VkIndirectCommandsTokenTypeNV type, void **mem)
 
4828
{
 
4829
   size_t size = 0;
 
4830
   struct zink_screen *screen = zink_screen(ctx->base.screen);
 
4831
   VkIndirectCommandsLayoutTokenNV *ret = util_dynarray_grow(&ctx->dgc.tokens, VkIndirectCommandsLayoutTokenNV, 1);
 
4832
   ret->sType = VK_STRUCTURE_TYPE_INDIRECT_COMMANDS_LAYOUT_TOKEN_NV;
 
4833
   ret->pNext = NULL;
 
4834
   ret->tokenType = type;
 
4835
   ret->vertexDynamicStride = ctx->gfx_pipeline_state.uses_dynamic_stride;
 
4836
   ret->indirectStateFlags = 0;
 
4837
   ret->indexTypeCount = 0;
 
4838
   switch (type) {
 
4839
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_VERTEX_BUFFER_NV:
 
4840
      ret->stream = ZINK_DGC_VBO;
 
4841
      size = sizeof(VkBindVertexBufferIndirectCommandNV);
 
4842
      break;
 
4843
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_INDEX_BUFFER_NV:
 
4844
      ret->stream = ZINK_DGC_IB;
 
4845
      size = sizeof(VkBindIndexBufferIndirectCommandNV);
 
4846
      break;
 
4847
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_SHADER_GROUP_NV:
 
4848
      ret->stream = ZINK_DGC_PSO;
 
4849
      size = sizeof(VkBindShaderGroupIndirectCommandNV);
 
4850
      break;
 
4851
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_PUSH_CONSTANT_NV:
 
4852
      ret->stream = ZINK_DGC_PUSH;
 
4853
      ret->pushconstantPipelineLayout = ctx->dgc.last_prog->base.layout;
 
4854
      ret->pushconstantShaderStageFlags = VK_SHADER_STAGE_ALL_GRAPHICS;
 
4855
      size = sizeof(float) * 6; //size for full tess level upload every time
 
4856
      break;
 
4857
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_DRAW_NV:
 
4858
      ret->stream = ZINK_DGC_DRAW;
 
4859
      size = sizeof(VkDrawIndirectCommand);
 
4860
      break;
 
4861
   case VK_INDIRECT_COMMANDS_TOKEN_TYPE_DRAW_INDEXED_NV:
 
4862
      ret->stream = ZINK_DGC_DRAW;
 
4863
      size = sizeof(VkDrawIndexedIndirectCommand);
 
4864
      break;
 
4865
   default:
 
4866
      unreachable("ack");
 
4867
   }
 
4868
   struct zink_resource *old = NULL;
 
4869
   unsigned stream_count = screen->info.nv_dgc_props.maxIndirectCommandsStreamCount >= ZINK_DGC_MAX ? ZINK_DGC_MAX : 1;
 
4870
   if (stream_count == 1)
 
4871
      ret->stream = 0;
 
4872
   unsigned stream = ret->stream;
 
4873
   bool max_exceeded = !ctx->dgc.max_size[stream];
 
4874
   ret->offset = ctx->dgc.cur_offsets[stream];
 
4875
   if (ctx->dgc.buffers[stream]) {
 
4876
      /* detect end of buffer */
 
4877
      if (ctx->dgc.bind_offsets[stream] + ctx->dgc.cur_offsets[stream] + size > ctx->dgc.buffers[stream]->base.b.width0) {
 
4878
         old = ctx->dgc.buffers[stream];
 
4879
         ctx->dgc.buffers[stream] = NULL;
 
4880
         max_exceeded = true;
 
4881
      }
 
4882
   }
 
4883
   if (!ctx->dgc.buffers[stream]) {
 
4884
      if (max_exceeded)
 
4885
         ctx->dgc.max_size[stream] += size * 5;
 
4886
      uint8_t *ptr;
 
4887
      unsigned offset;
 
4888
      u_upload_alloc(ctx->dgc.upload[stream], 0, ctx->dgc.max_size[stream],
 
4889
                     screen->info.props.limits.minMemoryMapAlignment, &offset,
 
4890
                     (struct pipe_resource **)&ctx->dgc.buffers[stream], (void **)&ptr);
 
4891
      size_t cur_size = old ? (ctx->dgc.cur_offsets[stream] - ctx->dgc.bind_offsets[stream]) : 0;
 
4892
      if (old) {
 
4893
         struct pipe_resource *pold = &old->base.b;
 
4894
         /* copy and delete old buffer */
 
4895
         zink_batch_reference_resource_rw(&ctx->batch, old, true);
 
4896
         memcpy(ptr + offset, ctx->dgc.maps[stream] + ctx->dgc.bind_offsets[stream], cur_size);
 
4897
         pipe_resource_reference(&pold, NULL);
 
4898
      }
 
4899
      ctx->dgc.maps[stream] = ptr;
 
4900
      ctx->dgc.bind_offsets[stream] = offset;
 
4901
      ctx->dgc.cur_offsets[stream] = cur_size;
 
4902
   }
 
4903
   *mem = ctx->dgc.maps[stream] + ctx->dgc.cur_offsets[stream];
 
4904
   ctx->dgc.cur_offsets[stream] += size;
 
4905
   return ret;
 
4906
}
 
4907
 
 
4908
void
 
4909
zink_flush_dgc(struct zink_context *ctx)
 
4910
{
 
4911
   struct zink_screen *screen = zink_screen(ctx->base.screen);
 
4912
   struct zink_batch_state *bs = ctx->batch.state;
 
4913
   if (!ctx->dgc.valid)
 
4914
      return;
 
4915
 
 
4916
   /* tokens should be created as they are used */
 
4917
   unsigned num_cmds = util_dynarray_num_elements(&ctx->dgc.tokens, VkIndirectCommandsLayoutTokenNV);
 
4918
   assert(num_cmds);
 
4919
   VkIndirectCommandsLayoutTokenNV *cmds = ctx->dgc.tokens.data;
 
4920
   uint32_t strides[ZINK_DGC_MAX] = {0};
 
4921
 
 
4922
   unsigned stream_count = screen->info.nv_dgc_props.maxIndirectCommandsStreamCount >= ZINK_DGC_MAX ? ZINK_DGC_MAX : 1;
 
4923
   VkIndirectCommandsStreamNV streams[ZINK_DGC_MAX];
 
4924
   for (unsigned i = 0; i < stream_count; i++) {
 
4925
      if (ctx->dgc.buffers[i]) {
 
4926
         streams[i].buffer = ctx->dgc.buffers[i]->obj->buffer;
 
4927
         streams[i].offset = ctx->dgc.bind_offsets[i];
 
4928
      } else {
 
4929
         streams[i].buffer = zink_resource(ctx->dummy_vertex_buffer)->obj->buffer;
 
4930
         streams[i].offset = 0;
 
4931
      }
 
4932
   }
 
4933
   /* this is a stupid pipeline that will never actually be used as anything but a container */
 
4934
   VkPipeline pipeline = VK_NULL_HANDLE;
 
4935
   if (screen->info.nv_dgc_props.maxGraphicsShaderGroupCount == 1) {
 
4936
      /* RADV doesn't support shader pipeline binds, so use this hacky path */
 
4937
      pipeline = ctx->gfx_pipeline_state.pipeline;
 
4938
   } else {
 
4939
      VkPrimitiveTopology vkmode = zink_primitive_topology(ctx->gfx_pipeline_state.gfx_prim_mode);
 
4940
      pipeline = zink_create_gfx_pipeline(screen, ctx->dgc.last_prog, ctx->dgc.last_prog->objs, &ctx->gfx_pipeline_state, ctx->gfx_pipeline_state.element_state->binding_map, vkmode, false, &ctx->dgc.pipelines);
 
4941
      assert(pipeline);
 
4942
      util_dynarray_append(&bs->dgc.pipelines, VkPipeline, pipeline);
 
4943
      VKCTX(CmdBindPipelineShaderGroupNV)(bs->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline, 0);
 
4944
   }
 
4945
   unsigned remaining = num_cmds;
 
4946
   for (unsigned i = 0; i < num_cmds; i += screen->info.nv_dgc_props.maxIndirectCommandsTokenCount, remaining -= screen->info.nv_dgc_props.maxIndirectCommandsTokenCount) {
 
4947
      VkIndirectCommandsLayoutCreateInfoNV lci = {
 
4948
         VK_STRUCTURE_TYPE_INDIRECT_COMMANDS_LAYOUT_CREATE_INFO_NV,
 
4949
         NULL,
 
4950
         0,
 
4951
         VK_PIPELINE_BIND_POINT_GRAPHICS,
 
4952
         MIN2(remaining, screen->info.nv_dgc_props.maxIndirectCommandsTokenCount),
 
4953
         cmds + i,
 
4954
         stream_count,
 
4955
         strides
 
4956
      };
 
4957
      VkIndirectCommandsLayoutNV iclayout;
 
4958
      VkResult res = VKSCR(CreateIndirectCommandsLayoutNV)(screen->dev, &lci, NULL, &iclayout);
 
4959
      assert(res == VK_SUCCESS);
 
4960
      util_dynarray_append(&bs->dgc.layouts, VkIndirectCommandsLayoutNV, iclayout);
 
4961
 
 
4962
      /* a lot of hacks to set up a preprocess buffer */
 
4963
      VkGeneratedCommandsMemoryRequirementsInfoNV info = {
 
4964
         VK_STRUCTURE_TYPE_GENERATED_COMMANDS_MEMORY_REQUIREMENTS_INFO_NV,
 
4965
         NULL,
 
4966
         VK_PIPELINE_BIND_POINT_GRAPHICS,
 
4967
         pipeline,
 
4968
         iclayout,
 
4969
         1
 
4970
      };
 
4971
      VkMemoryRequirements2 reqs = {
 
4972
         VK_STRUCTURE_TYPE_MEMORY_REQUIREMENTS_2
 
4973
      };
 
4974
      VKSCR(GetGeneratedCommandsMemoryRequirementsNV)(screen->dev, &info, &reqs);
 
4975
      struct pipe_resource templ = {0};
 
4976
      templ.target = PIPE_BUFFER;
 
4977
      templ.format = PIPE_FORMAT_R8_UNORM;
 
4978
      templ.bind = 0;
 
4979
      templ.usage = PIPE_USAGE_IMMUTABLE;
 
4980
      templ.flags = 0;
 
4981
      templ.width0 = reqs.memoryRequirements.size;
 
4982
      templ.height0 = 1;
 
4983
      templ.depth0 = 1;
 
4984
      templ.array_size = 1;
 
4985
      uint64_t params[] = {reqs.memoryRequirements.size, reqs.memoryRequirements.alignment, reqs.memoryRequirements.memoryTypeBits};
 
4986
      struct pipe_resource *pres = screen->base.resource_create_with_modifiers(&screen->base, &templ, params, 3);
 
4987
      assert(pres);
 
4988
      zink_batch_reference_resource_rw(&ctx->batch, zink_resource(pres), true);
 
4989
 
 
4990
      VkGeneratedCommandsInfoNV gen = {
 
4991
         VK_STRUCTURE_TYPE_GENERATED_COMMANDS_INFO_NV,
 
4992
         NULL,
 
4993
         VK_PIPELINE_BIND_POINT_GRAPHICS,
 
4994
         pipeline,
 
4995
         iclayout,
 
4996
         stream_count,
 
4997
         streams,
 
4998
         1,
 
4999
         zink_resource(pres)->obj->buffer,
 
5000
         0,
 
5001
         pres->width0,
 
5002
         VK_NULL_HANDLE,
 
5003
         0,
 
5004
         VK_NULL_HANDLE,
 
5005
         0
 
5006
      };
 
5007
      VKCTX(CmdExecuteGeneratedCommandsNV)(ctx->batch.state->cmdbuf, VK_FALSE, &gen);
 
5008
 
 
5009
      pipe_resource_reference(&pres, NULL);
 
5010
   }
 
5011
   util_dynarray_clear(&ctx->dgc.pipelines);
 
5012
   util_dynarray_clear(&ctx->dgc.tokens);
 
5013
   ctx->dgc.valid = false;
 
5014
   ctx->pipeline_changed[0] = true;
 
5015
   zink_select_draw_vbo(ctx);
 
5016
}
4759
5017
 
4760
5018
struct pipe_surface *
4761
5019
zink_get_dummy_pipe_surface(struct zink_context *ctx, int samples_index)
4832
5090
   ctx->compute_pipeline_state.dirty = true;
4833
5091
   ctx->fb_changed = ctx->rp_changed = true;
4834
5092
   ctx->sample_mask_changed = true;
4835
 
   ctx->gfx_pipeline_state.gfx_prim_mode = PIPE_PRIM_MAX;
 
5093
   ctx->gfx_pipeline_state.gfx_prim_mode = MESA_PRIM_COUNT;
4836
5094
 
4837
5095
   zink_init_draw_functions(ctx, screen);
4838
5096
   zink_init_grid_functions(ctx);
4841
5099
   ctx->base.priv = priv;
4842
5100
 
4843
5101
   ctx->base.destroy = zink_context_destroy;
 
5102
   ctx->base.set_debug_callback = zink_set_debug_callback;
4844
5103
   ctx->base.get_device_reset_status = zink_get_device_reset_status;
4845
5104
   ctx->base.set_device_reset_callback = zink_set_device_reset_callback;
4846
5105
 
4923
5182
   for (int i = 0; i < ARRAY_SIZE(ctx->fb_clears); i++)
4924
5183
      util_dynarray_init(&ctx->fb_clears[i].clears, ctx);
4925
5184
 
 
5185
   if (zink_debug & ZINK_DEBUG_DGC) {
 
5186
      util_dynarray_init(&ctx->dgc.pipelines, ctx);
 
5187
      util_dynarray_init(&ctx->dgc.tokens, ctx);
 
5188
      for (unsigned i = 0; i < ARRAY_SIZE(ctx->dgc.upload); i++)
 
5189
         ctx->dgc.upload[i] = u_upload_create_default(&ctx->base);
 
5190
   }
 
5191
 
4926
5192
   if (!is_copy_only) {
4927
5193
      ctx->blitter = util_blitter_create(&ctx->base);
4928
5194
      if (!ctx->blitter)
4930
5196
   }
4931
5197
 
4932
5198
   zink_set_last_vertex_key(ctx)->last_vertex_stage = true;
 
5199
   ctx->gfx_pipeline_state.shader_keys.last_vertex.key.vs_base.last_vertex_stage = true;
4933
5200
   zink_set_tcs_key_patches(ctx, 1);
4934
5201
   if (!screen->optimal_keys) {
4935
5202
      ctx->gfx_pipeline_state.shader_keys.key[MESA_SHADER_VERTEX].size = sizeof(struct zink_vs_key_base);
5006
5273
         util_idalloc_alloc(&ctx->di.bindless[i].img_slots);
5007
5274
         if (zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB) {
5008
5275
            ctx->di.bindless[i].db.buffer_infos = malloc(sizeof(VkDescriptorAddressInfoEXT) * ZINK_MAX_BINDLESS_HANDLES);
 
5276
            if (!ctx->di.bindless[i].db.buffer_infos) {
 
5277
               mesa_loge("ZINK: failed to allocate ctx->di.bindless[%d].db.buffer_infos!",i);
 
5278
               goto fail;
 
5279
            }
5009
5280
            for (unsigned j = 0; j < ZINK_MAX_BINDLESS_HANDLES; j++) {
5010
5281
               ctx->di.bindless[i].db.buffer_infos[j].sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT;
5011
5282
               ctx->di.bindless[i].db.buffer_infos[j].pNext = NULL;
5012
5283
            }
5013
5284
         } else {
5014
5285
            ctx->di.bindless[i].t.buffer_infos = malloc(sizeof(VkBufferView) * ZINK_MAX_BINDLESS_HANDLES);
 
5286
            if (!ctx->di.bindless[i].t.buffer_infos) {
 
5287
               mesa_loge("ZINK: failed to allocate ctx->di.bindless[%d].t.buffer_infos!",i);
 
5288
               goto fail;
 
5289
            }
5015
5290
         }
5016
5291
         ctx->di.bindless[i].img_infos = malloc(sizeof(VkDescriptorImageInfo) * ZINK_MAX_BINDLESS_HANDLES);
 
5292
         if (!ctx->di.bindless[i].img_infos) {
 
5293
            mesa_loge("ZINK: failed to allocate ctx->di.bindless[%d].img_infos!",i);
 
5294
            goto fail;
 
5295
         }
5017
5296
         util_dynarray_init(&ctx->di.bindless[i].updates, NULL);
5018
5297
         util_dynarray_init(&ctx->di.bindless[i].resident, NULL);
5019
5298
      }
5023
5302
   if (!ctx->batch.state)
5024
5303
      goto fail;
5025
5304
 
 
5305
   if (screen->compact_descriptors)
 
5306
      ctx->invalidate_descriptor_state = zink_context_invalidate_descriptor_state_compact;
 
5307
   else
 
5308
      ctx->invalidate_descriptor_state = zink_context_invalidate_descriptor_state;
5026
5309
   if (!is_copy_only && !is_compute_only) {
5027
5310
      pipe_buffer_write_nooverlap(&ctx->base, ctx->dummy_vertex_buffer, 0, sizeof(data), data);
5028
5311
      pipe_buffer_write_nooverlap(&ctx->base, ctx->dummy_xfb_buffer, 0, sizeof(data), data);
5100
5383
      struct pipe_depth_stencil_alpha_state dsa = {0};
5101
5384
      void *state = ctx->base.create_depth_stencil_alpha_state(&ctx->base, &dsa);
5102
5385
      ctx->base.bind_depth_stencil_alpha_state(&ctx->base, state);
 
5386
 
 
5387
      struct pipe_blend_state blend = {
 
5388
         .rt[0].colormask = 0xF
 
5389
      };
 
5390
 
 
5391
      void *blend_state = ctx->base.create_blend_state(&ctx->base, &blend);
 
5392
      ctx->base.bind_blend_state(&ctx->base, blend_state);
 
5393
 
5103
5394
      zink_batch_rp(ctx);
5104
5395
   }
5105
5396
 
5190
5481
      else
5191
5482
         ctx->dynamic_fb.attachments[idx].imageLayout = VK_IMAGE_LAYOUT_GENERAL;
5192
5483
   }
 
5484
   update_feedback_loop_dynamic_state(ctx);
5193
5485
   return true;
5194
5486
}
5195
5487