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Viewing changes to src/gallium/drivers/r600/evergreen_state.c

  • Committer: mmach
  • Date: 2023-11-02 21:31:35 UTC
  • Revision ID: netbit73@gmail.com-20231102213135-18d4tzh7tj0uz752
2023-11-02 22:11:57

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src/gallium/drivers/r600/evergreen_state.c
225
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static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
226
226
{
227
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        return r600_translate_texformat(screen, format, NULL, NULL, NULL,
228
 
                                   FALSE) != ~0U;
 
228
                                   false) != ~0U;
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}
230
230
 
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static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format)
232
232
{
233
 
        return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
234
 
                r600_translate_colorswap(format, FALSE) != ~0U;
 
233
        return r600_translate_colorformat(chip, format, false) != ~0U &&
 
234
                r600_translate_colorswap(format, false) != ~0U;
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}
236
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237
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static bool r600_is_zs_format_supported(enum pipe_format format)
671
671
        desc = util_format_description(params->pipe_format);
672
672
 
673
673
        if (params->force_swizzle)
674
 
                swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, TRUE);
 
674
                swizzle_res = r600_get_swizzle_combined(params->swizzle, NULL, true);
675
675
        else
676
 
                swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, TRUE);
 
676
                swizzle_res = r600_get_swizzle_combined(desc->swizzle, params->swizzle, true);
677
677
 
678
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        va = tmp->resource.gpu_address + params->offset;
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        *skip_mip_address_reloc = true;
755
755
        unsigned base_level, first_level, last_level;
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756
        unsigned dim, last_layer;
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757
        uint64_t va;
758
 
        bool do_endian_swap = FALSE;
 
758
        bool do_endian_swap = false;
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759
 
760
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        tile_split = tmp->surface.u.legacy.tile_split;
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        surflevel = tmp->surface.u.legacy.level;
1059
1059
        unsigned fmask;
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1060
        unsigned fmask_slice;
1061
1061
        uint64_t offset;
1062
 
        boolean export_16bpc;
 
1062
        bool export_16bpc;
1063
1063
};
1064
1064
 
1065
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static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1080
1080
 
1081
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        width_elements = last_element - first_element + 1;
1082
1082
 
1083
 
        format = r600_translate_colorformat(rctx->b.gfx_level, pformat, FALSE);
1084
 
        swap = r600_translate_colorswap(pformat, FALSE);
 
1083
        format = r600_translate_colorformat(rctx->b.gfx_level, pformat, false);
 
1084
        swap = r600_translate_colorswap(pformat, false);
1085
1085
 
1086
 
        endian = r600_colorformat_endian_swap(format, FALSE);
 
1086
        endian = r600_colorformat_endian_swap(format, false);
1087
1087
 
1088
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        desc = util_format_description(pformat);
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        i = util_format_get_first_non_void_channel(pformat);
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        unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1140
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        unsigned format, swap, ntype, endian;
1141
1141
        const struct util_format_description *desc;
1142
 
        bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
 
1142
        bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = false;
1143
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        int i;
1144
1144
 
1145
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        color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
2435
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       (util_format_is_srgb(format) ||
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        util_format_is_s3tc(format))
2437
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       ) {
2438
 
 
2439
 
      for (int i = 0; i < 4; ++i) {
2440
 
         switch (i) {
2441
 
         case 0: out->f[0] = in->f[view->swizzle_r];break;
2442
 
         case 1: out->f[1] = in->f[view->swizzle_g];break;
2443
 
         case 2: out->f[2] = in->f[view->swizzle_b];break;
2444
 
         case 3: out->f[3] = in->f[view->swizzle_a];break;
2445
 
         }
2446
 
      }
 
2438
                const float values[PIPE_SWIZZLE_MAX] = {
 
2439
                   in->f[0], in->f[1], in->f[2], in->f[3], 0.0f, 1.0f, 0.0f /* none */
 
2440
                };
 
2441
 
 
2442
                STATIC_ASSERT(PIPE_SWIZZLE_0 == 4);
 
2443
                STATIC_ASSERT(PIPE_SWIZZLE_1 == 5);
 
2444
                STATIC_ASSERT(PIPE_SWIZZLE_NONE == 6);
 
2445
                STATIC_ASSERT(PIPE_SWIZZLE_MAX == 7);
 
2446
 
 
2447
                out->f[0] = values[view->swizzle_r];
 
2448
                out->f[1] = values[view->swizzle_g];
 
2449
                out->f[2] = values[view->swizzle_b];
 
2450
                out->f[3] = values[view->swizzle_a];
2447
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   } else {
2448
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      memcpy(out->f, in->f, 4 * sizeof(float));
2449
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   }
2682
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                bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
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                bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2684
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                switch (tes_prim_mode) {
2685
 
                case PIPE_PRIM_LINES:
 
2689
                case MESA_PRIM_LINES:
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                        type = V_028B6C_TESS_ISOLINE;
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                        break;
2688
 
                case PIPE_PRIM_TRIANGLES:
 
2692
                case MESA_PRIM_TRIANGLES:
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                        type = V_028B6C_TESS_TRIANGLE;
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                        break;
2691
 
                case PIPE_PRIM_QUADS:
 
2695
                case MESA_PRIM_QUADS:
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                        type = V_028B6C_TESS_QUAD;
2693
2697
                        break;
2694
2698
                default:
2713
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2714
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                if (tes_point_mode)
2715
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                        topology = V_028B6C_OUTPUT_POINT;
2716
 
                else if (tes_prim_mode == PIPE_PRIM_LINES)
 
2720
                else if (tes_prim_mode == MESA_PRIM_LINES)
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                        topology = V_028B6C_OUTPUT_LINE;
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                else if (tes_vertex_order_cw)
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                        /* XXX follow radeonsi and invert */
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        unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control = 0;
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        int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
3400
3404
        int ninterp = 0;
3401
 
        boolean have_perspective = FALSE, have_linear = FALSE;
 
3405
        bool have_perspective = false, have_linear = false;
3402
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        static const unsigned spi_baryc_enable_bit[6] = {
3403
3407
                S_0286E0_PERSP_SAMPLE_ENA(1),
3404
3408
                S_0286E0_PERSP_CENTER_ENA(1),
3511
3515
 
3512
3516
        switch (rshader->ps_conservative_z) {
3513
3517
        default: /* fall through */
3514
 
        case TGSI_FS_DEPTH_LAYOUT_ANY:
 
3518
        case FRAG_DEPTH_LAYOUT_ANY:
3515
3519
                db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_ANY_Z);
3516
3520
                break;
3517
 
        case TGSI_FS_DEPTH_LAYOUT_GREATER:
 
3521
        case FRAG_DEPTH_LAYOUT_GREATER:
3518
3522
                db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3519
3523
                break;
3520
 
        case TGSI_FS_DEPTH_LAYOUT_LESS:
 
3524
        case FRAG_DEPTH_LAYOUT_LESS:
3521
3525
                db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3522
3526
                break;
3523
3527
        }
3541
3545
        shader->ps_color_export_mask = rshader->ps_color_export_mask;
3542
3546
        if (ninterp == 0) {
3543
3547
                ninterp = 1;
3544
 
                have_perspective = TRUE;
 
3548
                have_perspective = true;
3545
3549
        }
3546
3550
        if (!spi_baryc_cntl)
3547
3551
                spi_baryc_cntl |= spi_baryc_enable_bit[0];
3548
3552
 
3549
3553
        if (!have_perspective && !have_linear)
3550
 
                have_perspective = TRUE;
 
3554
                have_perspective = true;
3551
3555
 
3552
3556
        spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3553
3557
                              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3884
3888
                slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3885
3889
                slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3886
3890
                /* linear height must be the same as the slice tile max height, it's ok even
3887
 
                 * if the linear destination/source have smaller heigh as the size of the
 
3891
                 * if the linear destination/source have smaller height as the size of the
3888
3892
                 * dma packet will be using the copy_height which is always smaller or equal
3889
3893
                 * to the linear height
3890
3894
                 */
3909
3913
                slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
3910
3914
                slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
3911
3915
                /* linear height must be the same as the slice tile max height, it's ok even
3912
 
                 * if the linear destination/source have smaller heigh as the size of the
 
3916
                 * if the linear destination/source have smaller height as the size of the
3913
3917
                 * dma packet will be using the copy_height which is always smaller or equal
3914
3918
                 * to the linear height
3915
3919
                 */
4408
4412
        }
4409
4413
 
4410
4414
        istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46;
4411
 
        istate->dirty_buffer_constants = TRUE;
 
4415
        istate->dirty_buffer_constants = true;
4412
4416
        rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4413
4417
        rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4414
4418
                R600_CONTEXT_FLUSH_AND_INV_CB_META;