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#include "common.h"
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* ISA timer tick support
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#define mSEC_10_from_14 ((14318180 + 100) / 200)
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static unsigned long isa_gettimeoffset(void)
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#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ)
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static cycle_t pit_read(struct clocksource *cs)
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static int count_p = (mSEC_10_from_14/6); /* for the first call after boot */
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static unsigned long jiffies_p = 0;
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* cache volatile jiffies temporarily; we have IRQs turned off.
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unsigned long jiffies_t;
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/* timer count may underflow right here */
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outb_p(0x00, 0x43); /* latch the count ASAP */
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count = inb_p(0x40); /* read the latched count */
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* We do this guaranteed double memory access instead of a _p
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* postfix in the previous port access. Wheee, hackady hack
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count |= inb_p(0x40) << 8;
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/* Detect timer underflows. If we haven't had a timer tick since
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the last time we were called, and time is apparently going
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backwards, the counter must have wrapped during this routine. */
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if ((jiffies_t == jiffies_p) && (count > count_p))
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count -= (mSEC_10_from_14/6);
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jiffies_p = jiffies_t;
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count = (((mSEC_10_from_14/6)-1) - count) * (tick_nsec / 1000);
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count = (count + (mSEC_10_from_14/6)/2) / (mSEC_10_from_14/6);
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isa_timer_interrupt(int irq, void *dev_id)
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raw_local_irq_save(flags);
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outb_p(0x00, PIT_MODE); /* latch the count */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb_p(PIT_CH0) << 8;
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if (count > old_count && jifs == old_jifs)
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raw_local_irq_restore(flags);
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count = (PIT_LATCH - 1) - count;
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return (cycle_t)(jifs * PIT_LATCH) + count;
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static struct clocksource pit_cs = {
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.mask = CLOCKSOURCE_MASK(32),
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static void pit_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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raw_local_irq_save(flags);
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case CLOCK_EVT_MODE_PERIODIC:
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outb_p(0x34, PIT_MODE);
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outb_p(PIT_LATCH & 0xff, PIT_CH0);
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outb_p(PIT_LATCH >> 8, PIT_CH0);
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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outb_p(0x30, PIT_MODE);
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_RESUME:
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local_irq_restore(flags);
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static int pit_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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static struct clock_event_device pit_ce = {
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = pit_set_mode,
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.set_next_event = pit_set_next_event,
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static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *ce = dev_id;
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ce->event_handler(ce);
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return IRQ_HANDLED;
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static struct irqaction isa_timer_irq = {
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.name = "ISA timer tick",
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.handler = isa_timer_interrupt,
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static struct irqaction pit_timer_irq = {
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.handler = pit_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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static void __init isa_timer_init(void)
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/* enable PIT timer */
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/* set for periodic (4) and LSB/MSB write (0x30) */
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outb((mSEC_10_from_14/6) & 0xFF, 0x40);
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outb((mSEC_10_from_14/6) >> 8, 0x40);
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setup_irq(IRQ_ISA_TIMER, &isa_timer_irq);
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pit_ce.cpumask = cpumask_of(smp_processor_id());
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pit_ce.mult = div_sc(PIT_TICK_RATE, NSEC_PER_SEC, pit_ce.shift);
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pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce);
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pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce);
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clocksource_register_hz(&pit_cs, PIT_TICK_RATE);
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setup_irq(pit_ce.irq, &pit_timer_irq);
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clockevents_register_device(&pit_ce);
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struct sys_timer isa_timer = {
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.init = isa_timer_init,
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.offset = isa_gettimeoffset,