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* Copyright (c) 2010 Broadcom Corporation
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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/* This marks the start of a packed structure section. */
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#include <packed_section_start.h>
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#ifndef WL_RSSI_ANT_MAX
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#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
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#elif WL_RSSI_ANT_MAX != 4
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#error "WL_RSSI_ANT_MAX does not match"
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/* cpp contortions to concatenate w/arg prescan */
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#define BCN_TMPL_LEN 512 /* length of the BCN template area */
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#define RX_FIFO 0 /* data and ctl frames */
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#define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
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/* TX FIFO numbers using WME Access Classes */
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#define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
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#define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
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#define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
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#define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
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#define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
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#define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
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/* Addr is byte address used by SW; offset is word offset used by uCode */
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/* Per AC TX limit settings */
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#define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
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#define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
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/* Legacy TX FIFO numbers */
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#define TX_DATA_FIFO TX_AC_BE_FIFO
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#define TX_CTL_FIFO TX_AC_VO_FIFO
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typedef volatile struct {
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/* read: 32-bit register that can be read as 32-bit or as 2 16-bit
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* write: only low 16b-it half can be written
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typedef volatile union {
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u32 pmqhostdata; /* read only! */
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u16 pmqctrlstatus; /* read/write */
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/* pio register set 2/4 bytes union for d11 fifo */
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typedef volatile union {
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pio2regp_t b2; /* < corerev 8 */
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pio4regp_t b4; /* >= corerev 8 */
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/* dma/pio corerev < 11 */
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typedef volatile struct {
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dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */
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u_pioreg_t pioregs[8]; /* 0x300 */
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/* dma/pio corerev >= 11 */
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typedef volatile struct {
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dma64regs_t dmaxmt; /* dma tx */
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pio4regs_t piotx; /* pio tx */
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dma64regs_t dmarcv; /* dma rx */
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pio4regs_t piorx; /* pio rx */
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* Host Interface Registers
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* - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
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* - but definitely not complete
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typedef volatile struct _d11regs {
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/* Device Control ("semi-standard host registers") */
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u32 PAD[3]; /* 0x0 - 0x8 */
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u32 biststatus; /* 0xC */
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u32 biststatus2; /* 0x10 */
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u32 gptimer; /* 0x18 *//* for corerev >= 3 */
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u32 usectimer; /* 0x1c *//* for corerev >= 26 */
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/* Interrupt Control *//* 0x20 */
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intctrlregs_t intctrlregs[8];
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u32 PAD[40]; /* 0x60 - 0xFC */
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/* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
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u32 intrcvlazy[4]; /* 0x100 - 0x10C */
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u32 PAD[4]; /* 0x110 - 0x11c */
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u32 maccontrol; /* 0x120 */
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u32 maccommand; /* 0x124 */
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u32 macintstatus; /* 0x128 */
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u32 macintmask; /* 0x12C */
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/* Transmit Template Access */
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u32 tplatewrptr; /* 0x130 */
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u32 tplatewrdata; /* 0x134 */
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u32 PAD[2]; /* 0x138 - 0x13C */
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pmqreg_t pmqreg; /* 0x140 */
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u32 pmqpatl; /* 0x144 */
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u32 pmqpath; /* 0x148 */
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u32 chnstatus; /* 0x150 */
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u32 psmdebug; /* 0x154 *//* for corerev >= 3 */
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u32 phydebug; /* 0x158 *//* for corerev >= 3 */
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u32 machwcap; /* 0x15C *//* Corerev >= 13 */
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/* Extended Internal Objects */
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u32 objaddr; /* 0x160 */
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u32 objdata; /* 0x164 */
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u32 PAD[2]; /* 0x168 - 0x16c */
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/* New txstatus registers on corerev >= 5 */
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u32 frmtxstatus; /* 0x170 */
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u32 frmtxstatus2; /* 0x174 */
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u32 PAD[2]; /* 0x178 - 0x17c */
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/* New TSF host access on corerev >= 3 */
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u32 tsf_timerlow; /* 0x180 */
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u32 tsf_timerhigh; /* 0x184 */
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u32 tsf_cfprep; /* 0x188 */
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u32 tsf_cfpstart; /* 0x18c */
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u32 tsf_cfpmaxdur32; /* 0x190 */
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u32 PAD[3]; /* 0x194 - 0x19c */
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u32 maccontrol1; /* 0x1a0 */
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u32 machwcap1; /* 0x1a4 */
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u32 PAD[14]; /* 0x1a8 - 0x1dc */
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/* Clock control and hardware workarounds (corerev >= 13) */
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u32 clk_ctl_st; /* 0x1e0 */
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u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
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* moved to clk_ctl_st for corerev >= 17
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u32 PAD[5]; /* 0x1ec - 0x1fc */
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/* 0x200-0x37F dma/pio registers */
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fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
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fifo64_t f64regs[6]; /* on corerev >= 11 */
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/* FIFO diagnostic port access */
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dma32diag_t dmafifo; /* 0x380 - 0x38C */
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u32 aggfifocnt; /* 0x390 */
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u32 aggfifodata; /* 0x394 */
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u32 PAD[16]; /* 0x398 - 0x3d4 */
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u16 radioregaddr; /* 0x3d8 */
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u16 radioregdata; /* 0x3da */
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/* time delay between the change on rf disable input and radio shutdown corerev 10 */
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u32 rfdisabledly; /* 0x3DC */
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/* PHY register access */
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u16 phyversion; /* 0x3e0 - 0x0 */
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u16 phybbconfig; /* 0x3e2 - 0x1 */
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u16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
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u16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
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u16 phyrxstatus0; /* 0x3e8 - 0x4 */
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u16 phyrxstatus1; /* 0x3ea - 0x5 */
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u16 phycrsth; /* 0x3ec - 0x6 */
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u16 phytxerror; /* 0x3ee - 0x7 */
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u16 phychannel; /* 0x3f0 - 0x8 */
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u16 PAD[1]; /* 0x3f2 - 0x9 */
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u16 phytest; /* 0x3f4 - 0xa */
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u16 phy4waddr; /* 0x3f6 - 0xb */
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u16 phy4wdatahi; /* 0x3f8 - 0xc */
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u16 phy4wdatalo; /* 0x3fa - 0xd */
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u16 phyregaddr; /* 0x3fc - 0xe */
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u16 phyregdata; /* 0x3fe - 0xf */
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/* IHR *//* 0x400 - 0x7FE */
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u16 PAD[3]; /* 0x400 - 0x406 */
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u16 rcv_fifo_ctl; /* 0x406 */
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u16 PAD; /* 0x408 - 0x40a */
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u16 rcv_frm_cnt; /* 0x40a */
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u16 PAD[4]; /* 0x40a - 0x414 */
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u16 rssi; /* 0x414 */
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u16 PAD[5]; /* 0x414 - 0x420 */
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u16 rcm_ctl; /* 0x420 */
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u16 rcm_mat_data; /* 0x422 */
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u16 rcm_mat_mask; /* 0x424 */
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u16 rcm_mat_dly; /* 0x426 */
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u16 rcm_cond_mask_l; /* 0x428 */
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u16 rcm_cond_mask_h; /* 0x42A */
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u16 rcm_cond_dly; /* 0x42C */
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u16 PAD[1]; /* 0x42E */
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u16 ext_ihr_addr; /* 0x430 */
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u16 ext_ihr_data; /* 0x432 */
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u16 rxe_phyrs_2; /* 0x434 */
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u16 rxe_phyrs_3; /* 0x436 */
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u16 phy_mode; /* 0x438 */
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u16 rcmta_ctl; /* 0x43a */
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u16 rcmta_size; /* 0x43c */
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u16 rcmta_addr0; /* 0x43e */
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u16 rcmta_addr1; /* 0x440 */
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u16 rcmta_addr2; /* 0x442 */
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u16 PAD[30]; /* 0x444 - 0x480 */
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/* PSM Block *//* 0x480 - 0x500 */
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u16 psm_maccontrol_h; /* 0x482 */
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u16 psm_macintstatus_l; /* 0x484 */
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u16 psm_macintstatus_h; /* 0x486 */
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u16 psm_macintmask_l; /* 0x488 */
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u16 psm_macintmask_h; /* 0x48A */
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u16 psm_maccommand; /* 0x48E */
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u16 psm_brc; /* 0x490 */
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u16 psm_phy_hdr_param; /* 0x492 */
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u16 psm_postcard; /* 0x494 */
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u16 psm_pcard_loc_l; /* 0x496 */
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u16 psm_pcard_loc_h; /* 0x498 */
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u16 psm_gpio_in; /* 0x49A */
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u16 psm_gpio_out; /* 0x49C */
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u16 psm_gpio_oe; /* 0x49E */
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u16 psm_bred_0; /* 0x4A0 */
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u16 psm_bred_1; /* 0x4A2 */
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u16 psm_bred_2; /* 0x4A4 */
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u16 psm_bred_3; /* 0x4A6 */
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u16 psm_brcl_0; /* 0x4A8 */
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u16 psm_brcl_1; /* 0x4AA */
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u16 psm_brcl_2; /* 0x4AC */
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u16 psm_brcl_3; /* 0x4AE */
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u16 psm_brpo_0; /* 0x4B0 */
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u16 psm_brpo_1; /* 0x4B2 */
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u16 psm_brpo_2; /* 0x4B4 */
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u16 psm_brpo_3; /* 0x4B6 */
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u16 psm_brwk_0; /* 0x4B8 */
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u16 psm_brwk_1; /* 0x4BA */
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u16 psm_brwk_2; /* 0x4BC */
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u16 psm_brwk_3; /* 0x4BE */
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u16 psm_base_0; /* 0x4C0 */
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u16 psm_base_1; /* 0x4C2 */
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u16 psm_base_2; /* 0x4C4 */
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u16 psm_base_3; /* 0x4C6 */
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u16 psm_base_4; /* 0x4C8 */
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u16 psm_base_5; /* 0x4CA */
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u16 psm_base_6; /* 0x4CC */
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u16 psm_pc_reg_0; /* 0x4CE */
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u16 psm_pc_reg_1; /* 0x4D0 */
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u16 psm_pc_reg_2; /* 0x4D2 */
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u16 psm_pc_reg_3; /* 0x4D4 */
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u16 PAD[0xD]; /* 0x4D6 - 0x4DE */
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u16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
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u16 PAD[0x7]; /* 0x4f2 - 0x4fE */
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/* TXE0 Block *//* 0x500 - 0x580 */
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u16 txe_ctl; /* 0x500 */
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u16 txe_aux; /* 0x502 */
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u16 txe_ts_loc; /* 0x504 */
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u16 txe_time_out; /* 0x506 */
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u16 txe_wm_0; /* 0x508 */
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u16 txe_wm_1; /* 0x50A */
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u16 txe_phyctl; /* 0x50C */
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u16 txe_status; /* 0x50E */
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u16 txe_mmplcp0; /* 0x510 */
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u16 txe_mmplcp1; /* 0x512 */
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u16 txe_phyctl1; /* 0x514 */
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u16 PAD[0x05]; /* 0x510 - 0x51E */
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/* Transmit control */
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u16 xmtfifodef; /* 0x520 */
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u16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
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u16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
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u16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
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u16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
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u16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
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u16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
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u16 PAD[0x09]; /* 0x52E - 0x53E */
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u16 xmtfifocmd; /* 0x540 */
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u16 xmtfifoflush; /* 0x542 */
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u16 xmtfifothresh; /* 0x544 */
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u16 xmtfifordy; /* 0x546 */
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u16 xmtfifoprirdy; /* 0x548 */
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u16 xmtfiforqpri; /* 0x54A */
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u16 xmttplatetxptr; /* 0x54C */
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u16 xmttplateptr; /* 0x550 */
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u16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
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u16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
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u16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
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u16 PAD[0x04]; /* 0x558 - 0x55E */
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u16 xmttplatedatalo; /* 0x560 */
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u16 xmttplatedatahi; /* 0x562 */
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u16 PAD[2]; /* 0x564 - 0x566 */
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u16 xmtsel; /* 0x568 */
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u16 xmttxcnt; /* 0x56A */
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u16 xmttxshmaddr; /* 0x56C */
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u16 PAD[0x09]; /* 0x56E - 0x57E */
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u16 PAD[0x40]; /* 0x580 - 0x5FE */
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u16 PAD[0X02]; /* 0x600 - 0x602 */
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u16 tsf_cfpstrt_l; /* 0x604 */
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u16 tsf_cfpstrt_h; /* 0x606 */
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u16 PAD[0X05]; /* 0x608 - 0x610 */
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u16 tsf_cfppretbtt; /* 0x612 */
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u16 PAD[0XD]; /* 0x614 - 0x62C */
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u16 tsf_clk_frac_l; /* 0x62E */
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u16 tsf_clk_frac_h; /* 0x630 */
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u16 PAD[0X14]; /* 0x632 - 0x658 */
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u16 tsf_random; /* 0x65A */
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u16 PAD[0x05]; /* 0x65C - 0x664 */
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/* GPTimer 2 registers are corerev >= 3 */
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u16 tsf_gpt2_stat; /* 0x666 */
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u16 tsf_gpt2_ctr_l; /* 0x668 */
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u16 tsf_gpt2_ctr_h; /* 0x66A */
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u16 tsf_gpt2_val_l; /* 0x66C */
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u16 tsf_gpt2_val_h; /* 0x66E */
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u16 tsf_gptall_stat; /* 0x670 */
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u16 PAD[0x07]; /* 0x672 - 0x67E */
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u16 ifs_sifs_rx_tx_tx; /* 0x680 */
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u16 ifs_sifs_nav_tx; /* 0x682 */
366
u16 ifs_slot; /* 0x684 */
368
u16 ifs_ctl; /* 0x688 */
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u16 PAD[0x3]; /* 0x68a - 0x68F */
370
u16 ifsstat; /* 0x690 */
371
u16 ifsmedbusyctl; /* 0x692 */
372
u16 iftxdur; /* 0x694 */
373
u16 PAD[0x3]; /* 0x696 - 0x69b */
374
/* EDCF support in dot11macs with corerevs >= 16 */
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u16 ifs_aifsn; /* 0x69c */
376
u16 ifs_ctl1; /* 0x69e */
378
/* New slow clock registers on corerev >= 5 */
379
u16 scc_ctl; /* 0x6a0 */
380
u16 scc_timer_l; /* 0x6a2 */
381
u16 scc_timer_h; /* 0x6a4 */
382
u16 scc_frac; /* 0x6a6 */
383
u16 scc_fastpwrup_dly; /* 0x6a8 */
384
u16 scc_per; /* 0x6aa */
385
u16 scc_per_frac; /* 0x6ac */
386
u16 scc_cal_timer_l; /* 0x6ae */
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u16 scc_cal_timer_h; /* 0x6b0 */
393
u16 nav_ctl; /* 0x700 */
394
u16 navstat; /* 0x702 */
395
u16 PAD[0x3e]; /* 0x702 - 0x77E */
397
/* WEP/PMQ Block *//* 0x780 - 0x7FE */
398
u16 PAD[0x20]; /* 0x780 - 0x7BE */
400
u16 wepctl; /* 0x7C0 */
401
u16 wepivloc; /* 0x7C2 */
402
u16 wepivkey; /* 0x7C4 */
403
u16 wepwkey; /* 0x7C6 */
405
u16 PAD[4]; /* 0x7C8 - 0x7CE */
406
u16 pcmctl; /* 0X7D0 */
407
u16 pcmstat; /* 0X7D2 */
408
u16 PAD[6]; /* 0x7D4 - 0x7DE */
410
u16 pmqctl; /* 0x7E0 */
411
u16 pmqstatus; /* 0x7E2 */
412
u16 pmqpat0; /* 0x7E4 */
413
u16 pmqpat1; /* 0x7E6 */
414
u16 pmqpat2; /* 0x7E8 */
416
u16 pmqdat; /* 0x7EA */
417
u16 pmqdator; /* 0x7EC */
418
u16 pmqhst; /* 0x7EE */
419
u16 pmqpath0; /* 0x7F0 */
420
u16 pmqpath1; /* 0x7F2 */
421
u16 pmqpath2; /* 0x7F4 */
422
u16 pmqdath; /* 0x7F6 */
424
u16 PAD[0x04]; /* 0x7F8 - 0x7FE */
426
/* SHM *//* 0x800 - 0xEFE */
427
u16 PAD[0x380]; /* 0x800 - 0xEFE */
429
/* SB configuration registers: 0xF00 */
430
sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
433
#define PIHR_BASE 0x0400 /* byte address of packed IHR region */
436
#define BT_DONE (1U << 31) /* bist done */
437
#define BT_B2S (1 << 30) /* bist2 ram summary bit */
439
/* intstatus and intmask */
440
#define I_PC (1 << 10) /* pci descriptor error */
441
#define I_PD (1 << 11) /* pci data error */
442
#define I_DE (1 << 12) /* descriptor protocol error */
443
#define I_RU (1 << 13) /* receive descriptor underflow */
444
#define I_RO (1 << 14) /* receive fifo overflow */
445
#define I_XU (1 << 15) /* transmit fifo underflow */
446
#define I_RI (1 << 16) /* receive interrupt */
447
#define I_XI (1 << 24) /* transmit interrupt */
449
/* interrupt receive lazy */
450
#define IRL_TO_MASK 0x00ffffff /* timeout */
451
#define IRL_FC_MASK 0xff000000 /* frame count */
452
#define IRL_FC_SHIFT 24 /* frame count */
454
/* maccontrol register */
455
#define MCTL_GMODE (1U << 31)
456
#define MCTL_DISCARD_PMQ (1 << 30)
457
#define MCTL_WAKE (1 << 26)
458
#define MCTL_HPS (1 << 25)
459
#define MCTL_PROMISC (1 << 24)
460
#define MCTL_KEEPBADFCS (1 << 23)
461
#define MCTL_KEEPCONTROL (1 << 22)
462
#define MCTL_PHYLOCK (1 << 21)
463
#define MCTL_BCNS_PROMISC (1 << 20)
464
#define MCTL_LOCK_RADIO (1 << 19)
465
#define MCTL_AP (1 << 18)
466
#define MCTL_INFRA (1 << 17)
467
#define MCTL_BIGEND (1 << 16)
468
#define MCTL_GPOUT_SEL_MASK (3 << 14)
469
#define MCTL_GPOUT_SEL_SHIFT 14
470
#define MCTL_EN_PSMDBG (1 << 13)
471
#define MCTL_IHR_EN (1 << 10)
472
#define MCTL_SHM_UPPER (1 << 9)
473
#define MCTL_SHM_EN (1 << 8)
474
#define MCTL_PSM_JMP_0 (1 << 2)
475
#define MCTL_PSM_RUN (1 << 1)
476
#define MCTL_EN_MAC (1 << 0)
478
/* maccommand register */
479
#define MCMD_BCN0VLD (1 << 0)
480
#define MCMD_BCN1VLD (1 << 1)
481
#define MCMD_DIRFRMQVAL (1 << 2)
482
#define MCMD_CCA (1 << 3)
483
#define MCMD_BG_NOISE (1 << 4)
484
#define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
485
#define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
487
/* macintstatus/macintmask */
488
#define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
489
#define MI_BCNTPL (1 << 1) /* beacon template available */
490
#define MI_TBTT (1 << 2) /* TBTT indication */
491
#define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
492
#define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
493
#define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
494
#define MI_PMQ (1 << 6) /* PMQ entries available */
495
#define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
496
#define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
497
#define MI_MACTXERR (1 << 9) /* MAC level Tx error */
498
#define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
499
#define MI_PHYTXERR (1 << 11) /* PHY Tx error */
500
#define MI_PME (1 << 12) /* Power Management Event */
501
#define MI_GP0 (1 << 13) /* General-purpose timer0 */
502
#define MI_GP1 (1 << 14) /* General-purpose timer1 */
503
#define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
504
#define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
505
#define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
506
#define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
507
#define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
508
#define MI_PRQ (1 << 20) /* Probe response queue needs attention */
509
#define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
510
#define MI_RESERVED3 (1 << 22)
511
#define MI_RESERVED2 (1 << 23)
512
#define MI_RESERVED1 (1 << 25)
513
#define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input
516
#define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */
517
#define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
518
#define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */
520
/* Mac capabilities registers */
522
#define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
525
#define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
526
#define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
527
#define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
528
#define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
529
#define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
530
#define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
531
#define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
532
#define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
533
#define PMQH_OFLO 0x00000004 /* pmq overflow indication */
534
#define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
536
/* phydebug (corerev >= 3) */
537
#define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
538
#define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
539
#define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
540
#define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
541
#define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
542
#define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
543
#define PDBG_RXFRG (1 << 6) /* rx start not asserted */
544
#define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
545
#define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
547
/* objaddr register */
548
#define OBJADDR_SEL_MASK 0x000F0000
549
#define OBJADDR_UCM_SEL 0x00000000
550
#define OBJADDR_SHM_SEL 0x00010000
551
#define OBJADDR_SCR_SEL 0x00020000
552
#define OBJADDR_IHR_SEL 0x00030000
553
#define OBJADDR_RCMTA_SEL 0x00040000
554
#define OBJADDR_SRCHM_SEL 0x00060000
555
#define OBJADDR_WINC 0x01000000
556
#define OBJADDR_RINC 0x02000000
557
#define OBJADDR_AUTO_INC 0x03000000
559
#define WEP_PCMADDR 0x07d4
560
#define WEP_PCMDATA 0x07d6
563
#define TXS_V (1 << 0) /* valid bit */
564
#define TXS_STATUS_MASK 0xffff
565
/* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
566
#define TXS_COMPAT_MASK 0x3
567
#define TXS_COMPAT_SHIFT 1
568
#define TXS_FID_MASK 0xffff0000
569
#define TXS_FID_SHIFT 16
572
#define TXS_SEQ_MASK 0xffff
573
#define TXS_PTX_MASK 0xff0000
574
#define TXS_PTX_SHIFT 16
575
#define TXS_MU_MASK 0x01000000
576
#define TXS_MU_SHIFT 24
578
/* clk_ctl_st, corerev >= 17 */
579
#define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
580
#define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
581
#define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
582
#define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
584
/* HT Cloclk Ctrl and Clock Avail for 4313 */
585
#define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
586
#define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
588
/* d11_pwrctl, corerev16 only */
589
#define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */
590
#define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */
592
/* tsf_cfprep register */
593
#define CFPREP_CBI_MASK 0xffffffc0
594
#define CFPREP_CBI_SHIFT 6
595
#define CFPREP_CFPP 0x00000001
597
/* tx fifo sizes for corerev >= 9 */
598
/* tx fifo sizes values are in terms of 256 byte blocks */
599
#define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
600
#define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
601
#define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
603
#define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
604
#define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
605
#define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
606
#define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
608
/* phy versions, PhyVersion:Revision field */
609
#define PV_AV_MASK 0xf000 /* analog block version */
610
#define PV_AV_SHIFT 12 /* analog block version bitfield offset */
611
#define PV_PT_MASK 0x0f00 /* phy type */
612
#define PV_PT_SHIFT 8 /* phy type bitfield offset */
613
#define PV_PV_MASK 0x000f /* phy version */
614
#define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
616
/* phy types, PhyVersion:PhyType field */
617
#define PHY_TYPE_N 4 /* N-Phy value */
618
#define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
619
#define PHY_TYPE_LCN 8 /* LCN-Phy value */
620
#define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
621
#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
623
/* analog types, PhyVersion:AnalogType field */
624
#define ANA_11N_013 5
626
/* 802.11a PLCP header def */
627
typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
628
BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
629
u8 rlpt[3]; /* rate, length, parity, tail */
632
} BWL_POST_PACKED_STRUCT;
634
#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
635
#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
636
#define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
637
#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
638
#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
640
/* rate encoded per 802.11a-1999 sec 17.3.4.1 */
641
#define D11A_PHY_HDR_SRATE(phdr, rate) \
642
((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
643
/* set reserved field to zero */
644
#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
645
/* length is number of octets in PSDU */
646
#define D11A_PHY_HDR_SLENGTH(phdr, length) \
647
(*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
648
(((length) & 0x0fff) << 5))
649
/* set the tail to all zeros */
650
#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
652
#define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
653
#define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
655
#define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
657
#define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
658
#define D11A_PHY_PRE_TIME (16)
659
#define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
661
/* 802.11b PLCP header def */
662
typedef struct cck_phy_hdr cck_phy_hdr_t;
663
BWL_PRE_PACKED_STRUCT struct cck_phy_hdr {
668
} BWL_POST_PACKED_STRUCT;
670
#define D11B_PHY_HDR_LEN 6
672
#define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
674
#define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
675
#define D11B_PHY_LPRE_TIME (144)
676
#define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
678
#define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
679
#define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
680
#define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
682
#define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
683
#define D11B_PLCP_SIGNAL_LE (1 << 7)
685
#define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
686
#define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
687
#define MIMO_PLCP_AMPDU 0x08 /* ampdu */
689
#define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
690
#define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
691
#define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
693
plcp[1] = len & 0xff; \
694
plcp[2] = ((len >> 8) & 0xff); \
697
#define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
698
#define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
699
#define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
701
/* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
702
* don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
703
* padding added in the ucode.
705
#define D11_PHY_HDR_LEN 6
707
/* TX DMA buffer header */
708
typedef struct d11txh d11txh_t;
709
BWL_PRE_PACKED_STRUCT struct d11txh {
710
u16 MacTxControlLow; /* 0x0 */
711
u16 MacTxControlHigh; /* 0x1 */
712
u16 MacFrameControl; /* 0x2 */
713
u16 TxFesTimeNormal; /* 0x3 */
714
u16 PhyTxControlWord; /* 0x4 */
715
u16 PhyTxControlWord_1; /* 0x5 */
716
u16 PhyTxControlWord_1_Fbr; /* 0x6 */
717
u16 PhyTxControlWord_1_Rts; /* 0x7 */
718
u16 PhyTxControlWord_1_FbrRts; /* 0x8 */
719
u16 MainRates; /* 0x9 */
720
u16 XtraFrameTypes; /* 0xa */
721
u8 IV[16]; /* 0x0b - 0x12 */
722
u8 TxFrameRA[6]; /* 0x13 - 0x15 */
723
u16 TxFesTimeFallback; /* 0x16 */
724
u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
725
u16 RTSDurFallback; /* 0x1a */
726
u8 FragPLCPFallback[6]; /* 0x1b - 1d */
727
u16 FragDurFallback; /* 0x1e */
728
u16 MModeLen; /* 0x1f */
729
u16 MModeFbrLen; /* 0x20 */
730
u16 TstampLow; /* 0x21 */
731
u16 TstampHigh; /* 0x22 */
732
u16 ABI_MimoAntSel; /* 0x23 */
733
u16 PreloadSize; /* 0x24 */
734
u16 AmpduSeqCtl; /* 0x25 */
735
u16 TxFrameID; /* 0x26 */
736
u16 TxStatus; /* 0x27 */
737
u16 MaxNMpdus; /* 0x28 corerev >=16 */
738
u16 MaxABytes_MRT; /* 0x29 corerev >=16 */
739
u16 MaxABytes_FBR; /* 0x2a corerev >=16 */
740
u16 MinMBytes; /* 0x2b corerev >=16 */
741
u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
742
struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
744
} BWL_POST_PACKED_STRUCT;
746
#define D11_TXH_LEN 112 /* bytes */
754
/* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
755
#define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
756
#define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
757
#define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
758
#define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
759
#define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
761
/* MacTxControlLow */
762
#define TXC_AMIC 0x8000
763
#define TXC_SENDCTS 0x0800
764
#define TXC_AMPDU_MASK 0x0600
765
#define TXC_BW_40 0x0100
766
#define TXC_FREQBAND_5G 0x0080
767
#define TXC_DFCS 0x0040
768
#define TXC_IGNOREPMQ 0x0020
769
#define TXC_HWSEQ 0x0010
770
#define TXC_STARTMSDU 0x0008
771
#define TXC_SENDRTS 0x0004
772
#define TXC_LONGFRAME 0x0002
773
#define TXC_IMMEDACK 0x0001
775
/* MacTxControlHigh */
776
#define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
777
#define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
778
#define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
779
* 1 = SHORT for OFDM/GF for MIMO
780
* 0 = LONG for CCK/MM for MIMO
782
/* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
783
#define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
784
#define TXC_SECKEY_MASK 0x0FF0
785
#define TXC_SECKEY_SHIFT 4
786
#define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
787
#define TXC_SECTYPE_MASK 0x0007
788
#define TXC_SECTYPE_SHIFT 0
790
/* Null delimiter for Fallback rate */
791
#define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
793
/* PhyTxControl for Mimophy */
794
#define PHY_TXC_PWR_MASK 0xFC00
795
#define PHY_TXC_PWR_SHIFT 10
796
#define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
797
#define PHY_TXC_ANT_SHIFT 6
798
#define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
799
#define PHY_TXC_LCNPHY_ANT_LAST 0x0000
800
#define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
801
#define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
802
#define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
803
#define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
804
#define PHY_TXC_SHORT_HDR 0x0010
806
#define PHY_TXC_OLD_ANT_0 0x0000
807
#define PHY_TXC_OLD_ANT_1 0x0100
808
#define PHY_TXC_OLD_ANT_LAST 0x0300
810
/* PhyTxControl_1 for Mimophy */
811
#define PHY_TXC1_BW_MASK 0x0007
812
#define PHY_TXC1_BW_10MHZ 0
813
#define PHY_TXC1_BW_10MHZ_UP 1
814
#define PHY_TXC1_BW_20MHZ 2
815
#define PHY_TXC1_BW_20MHZ_UP 3
816
#define PHY_TXC1_BW_40MHZ 4
817
#define PHY_TXC1_BW_40MHZ_DUP 5
818
#define PHY_TXC1_MODE_SHIFT 3
819
#define PHY_TXC1_MODE_MASK 0x0038
820
#define PHY_TXC1_MODE_SISO 0
821
#define PHY_TXC1_MODE_CDD 1
822
#define PHY_TXC1_MODE_STBC 2
823
#define PHY_TXC1_MODE_SDM 3
825
/* PhyTxControl for HTphy that are different from Mimophy */
826
#define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
829
#define XFTS_RTS_FT_SHIFT 2
830
#define XFTS_FBRRTS_FT_SHIFT 4
831
#define XFTS_CHANNEL_SHIFT 8
833
/* Antenna diversity bit in ant_wr_settle */
834
#define PHY_AWS_ANTDIV 0x2000
837
#define IFS_USEEDCF (1 << 2)
840
#define IFS_CTL1_EDCRS (1 << 3)
841
#define IFS_CTL1_EDCRS_20L (1 << 4)
842
#define IFS_CTL1_EDCRS_40 (1 << 5)
845
#define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
846
#define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
847
#define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
848
#define ABI_MAS_FBR_ANT_PTN_SHIFT 4
849
#define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
851
/* tx status packet */
852
typedef struct tx_status tx_status_t;
853
BWL_PRE_PACKED_STRUCT struct tx_status {
862
} BWL_POST_PACKED_STRUCT;
864
#define TXSTATUS_LEN 16
866
/* status field bit definitions */
867
#define TX_STATUS_FRM_RTX_MASK 0xF000
868
#define TX_STATUS_FRM_RTX_SHIFT 12
869
#define TX_STATUS_RTS_RTX_MASK 0x0F00
870
#define TX_STATUS_RTS_RTX_SHIFT 8
871
#define TX_STATUS_MASK 0x00FE
872
#define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
873
#define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
874
#define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
875
#define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
876
#define TX_STATUS_SUPR_SHIFT 2
877
#define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
878
#define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */
879
#define TX_STATUS_NO_ACK 0
881
/* suppress status reason codes */
882
#define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
883
#define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
884
#define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
885
#define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
886
#define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
887
#define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
888
#define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
890
/* Unexpected tx status for rate update */
891
#define TX_STATUS_UNEXP(status) \
892
((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
893
TX_STATUS_UNEXP_AMPDU(status))
895
/* Unexpected tx status for A-MPDU rate update */
896
#define TX_STATUS_UNEXP_AMPDU(status) \
897
((((status) & TX_STATUS_SUPR_MASK) != 0) && \
898
(((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
900
#define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
901
#define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
902
#define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
903
#define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
905
/* RXE (Receive Engine) */
908
#define RCM_INC_MASK_H 0x0080
909
#define RCM_INC_MASK_L 0x0040
910
#define RCM_INC_DATA 0x0020
911
#define RCM_INDEX_MASK 0x001F
914
#define RCM_MAC_OFFSET 0 /* current MAC address */
915
#define RCM_BSSID_OFFSET 3 /* current BSSID address */
916
#define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
917
#define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
918
#define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
920
#define RCM_WEP_TA0_OFFSET 16
921
#define RCM_WEP_TA1_OFFSET 19
922
#define RCM_WEP_TA2_OFFSET 22
923
#define RCM_WEP_TA3_OFFSET 25
927
/* psm_phy_hdr_param bits */
928
#define MAC_PHY_RESET 1
929
#define MAC_PHY_CLOCK_EN 2
930
#define MAC_PHY_FORCE_CLK 4
935
#define WKEY_START (1 << 8)
936
#define WKEY_SEL_MASK 0x1F
938
/* WEP data formats */
940
/* the number of RCMTA entries */
941
#define RCMTA_SIZE 50
943
#define M_ADDR_BMP_BLK (0x37e * 2)
944
#define M_ADDR_BMP_BLK_SZ 12
946
#define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
947
#define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
948
#define ADDR_BMP_BSSID (1 << 2) /* BSSID */
949
#define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
950
#define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
951
#define ADDR_BMP_RESERVED1 (1 << 5)
952
#define ADDR_BMP_RESERVED2 (1 << 6)
953
#define ADDR_BMP_RESERVED3 (1 << 7)
954
#define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
955
#define ADDR_BMP_BSS_IDX_SHIFT 8
957
#define WSEC_MAX_RCMTA_KEYS 54
959
/* max keys in M_TKMICKEYS_BLK */
960
#define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
962
/* max RXE match registers */
963
#define WSEC_MAX_RXE_KEYS 4
965
/* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
966
/* SKL (Security Key Lookup) */
967
#define SKL_ALGO_MASK 0x0007
968
#define SKL_ALGO_SHIFT 0
969
#define SKL_KEYID_MASK 0x0008
970
#define SKL_KEYID_SHIFT 3
971
#define SKL_INDEX_MASK 0x03F0
972
#define SKL_INDEX_SHIFT 4
973
#define SKL_GRP_ALGO_MASK 0x1c00
974
#define SKL_GRP_ALGO_SHIFT 10
976
/* additional bits defined for IBSS group key support */
977
#define SKL_IBSS_INDEX_MASK 0x01F0
978
#define SKL_IBSS_INDEX_SHIFT 4
979
#define SKL_IBSS_KEYID1_MASK 0x0600
980
#define SKL_IBSS_KEYID1_SHIFT 9
981
#define SKL_IBSS_KEYID2_MASK 0x1800
982
#define SKL_IBSS_KEYID2_SHIFT 11
983
#define SKL_IBSS_KEYALGO_MASK 0xE000
984
#define SKL_IBSS_KEYALGO_SHIFT 13
986
#define WSEC_MODE_OFF 0
987
#define WSEC_MODE_HW 1
988
#define WSEC_MODE_SW 2
990
#define WSEC_ALGO_OFF 0
991
#define WSEC_ALGO_WEP1 1
992
#define WSEC_ALGO_TKIP 2
993
#define WSEC_ALGO_AES 3
994
#define WSEC_ALGO_WEP128 4
995
#define WSEC_ALGO_AES_LEGACY 5
996
#define WSEC_ALGO_NALG 6
998
#define AES_MODE_NONE 0
999
#define AES_MODE_CCM 1
1001
/* WEP_CTL (Rev 0) */
1002
#define WECR0_KEYREG_SHIFT 0
1003
#define WECR0_KEYREG_MASK 0x7
1004
#define WECR0_DECRYPT (1 << 3)
1005
#define WECR0_IVINLINE (1 << 4)
1006
#define WECR0_WEPALG_SHIFT 5
1007
#define WECR0_WEPALG_MASK (0x7 << 5)
1008
#define WECR0_WKEYSEL_SHIFT 8
1009
#define WECR0_WKEYSEL_MASK (0x7 << 8)
1010
#define WECR0_WKEYSTART (1 << 11)
1011
#define WECR0_WEPINIT (1 << 14)
1012
#define WECR0_ICVERR (1 << 15)
1014
/* Frame template map byte offsets */
1015
#define T_ACTS_TPL_BASE (0)
1016
#define T_NULL_TPL_BASE (0xc * 2)
1017
#define T_QNULL_TPL_BASE (0x1c * 2)
1018
#define T_RR_TPL_BASE (0x2c * 2)
1019
#define T_BCN0_TPL_BASE (0x34 * 2)
1020
#define T_PRS_TPL_BASE (0x134 * 2)
1021
#define T_BCN1_TPL_BASE (0x234 * 2)
1022
#define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
1024
#define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1026
#define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1028
/* Shared Mem byte offsets */
1030
/* Location where the ucode expects the corerev */
1031
#define M_MACHW_VER (0x00b * 2)
1033
/* Location where the ucode expects the MAC capabilities */
1034
#define M_MACHW_CAP_L (0x060 * 2)
1035
#define M_MACHW_CAP_H (0x061 * 2)
1037
/* WME shared memory */
1038
#define M_EDCF_STATUS_OFF (0x007 * 2)
1039
#define M_TXF_CUR_INDEX (0x018 * 2)
1040
#define M_EDCF_QINFO (0x120 * 2)
1042
/* PS-mode related parameters */
1043
#define M_DOT11_SLOT (0x008 * 2)
1044
#define M_DOT11_DTIMPERIOD (0x009 * 2)
1045
#define M_NOSLPZNATDTIM (0x026 * 2)
1047
/* Beacon-related parameters */
1048
#define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1049
#define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1050
#define M_BCN_TXTSF_OFFSET (0x00e * 2)
1051
#define M_TIMBPOS_INBEACON (0x00f * 2)
1052
#define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1053
#define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1054
#define M_BCN_PCTLWD (0x02a * 2)
1055
#define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1057
/* MAX Rx Frame len */
1058
#define M_MAXRXFRM_LEN (0x010 * 2)
1060
/* ACK/CTS related params */
1061
#define M_RSP_PCTLWD (0x011 * 2)
1063
/* Hardware Power Control */
1064
#define M_TXPWR_N (0x012 * 2)
1065
#define M_TXPWR_TARGET (0x013 * 2)
1066
#define M_TXPWR_MAX (0x014 * 2)
1067
#define M_TXPWR_CUR (0x019 * 2)
1069
/* Rx-related parameters */
1070
#define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1072
/* WEP Shared mem data */
1073
#define M_SEC_DEFIVLOC (0x01e * 2)
1074
#define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1075
#define M_PHYVER (0x028 * 2)
1076
#define M_PHYTYPE (0x029 * 2)
1077
#define M_SECRXKEYS_PTR (0x02b * 2)
1078
#define M_TKMICKEYS_PTR (0x059 * 2)
1079
#define M_SECKINDXALGO_BLK (0x2ea * 2)
1080
#define M_SECKINDXALGO_BLK_SZ 54
1081
#define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1082
#define M_TKIP_TSC_TTAK (0x18c * 2)
1083
#define D11_MAX_KEY_SIZE 16
1085
#define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1087
/* Probe response related parameters */
1088
#define M_SSIDLEN (0x024 * 2)
1089
#define M_PRB_RESP_FRM_LEN (0x025 * 2)
1090
#define M_PRS_MAXTIME (0x03a * 2)
1091
#define M_SSID (0xb0 * 2)
1092
#define M_CTXPRS_BLK (0xc0 * 2)
1093
#define C_CTX_PCTLWD_POS (0x4 * 2)
1095
/* Delta between OFDM and CCK power in CCK power boost mode */
1096
#define M_OFDM_OFFSET (0x027 * 2)
1098
/* TSSI for last 4 11b/g CCK packets transmitted */
1099
#define M_B_TSSI_0 (0x02c * 2)
1100
#define M_B_TSSI_1 (0x02d * 2)
1102
/* Host flags to turn on ucode options */
1103
#define M_HOST_FLAGS1 (0x02f * 2)
1104
#define M_HOST_FLAGS2 (0x030 * 2)
1105
#define M_HOST_FLAGS3 (0x031 * 2)
1106
#define M_HOST_FLAGS4 (0x03c * 2)
1107
#define M_HOST_FLAGS5 (0x06a * 2)
1108
#define M_HOST_FLAGS_SZ 16
1110
#define M_RADAR_REG (0x033 * 2)
1112
/* TSSI for last 4 11a OFDM packets transmitted */
1113
#define M_A_TSSI_0 (0x034 * 2)
1114
#define M_A_TSSI_1 (0x035 * 2)
1116
/* noise interference measurement */
1117
#define M_NOISE_IF_COUNT (0x034 * 2)
1118
#define M_NOISE_IF_TIMEOUT (0x035 * 2)
1120
#define M_RF_RX_SP_REG1 (0x036 * 2)
1122
/* TSSI for last 4 11g OFDM packets transmitted */
1123
#define M_G_TSSI_0 (0x038 * 2)
1124
#define M_G_TSSI_1 (0x039 * 2)
1126
/* Background noise measure */
1127
#define M_JSSI_0 (0x44 * 2)
1128
#define M_JSSI_1 (0x45 * 2)
1129
#define M_JSSI_AUX (0x46 * 2)
1131
#define M_CUR_2050_RADIOCODE (0x47 * 2)
1134
#define M_FIFOSIZE0 (0x4c * 2)
1135
#define M_FIFOSIZE1 (0x4d * 2)
1136
#define M_FIFOSIZE2 (0x4e * 2)
1137
#define M_FIFOSIZE3 (0x4f * 2)
1138
#define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1140
/* Current channel number plus upper bits */
1141
#define M_CURCHANNEL (0x50 * 2)
1142
#define D11_CURCHANNEL_5G 0x0100;
1143
#define D11_CURCHANNEL_40 0x0200;
1144
#define D11_CURCHANNEL_MAX 0x00FF;
1146
/* last posted frameid on the bcmc fifo */
1147
#define M_BCMC_FID (0x54 * 2)
1148
#define INVALIDFID 0xffff
1150
/* extended beacon phyctl bytes for 11N */
1151
#define M_BCN_PCTL1WD (0x058 * 2)
1153
/* idle busy ratio to duty_cycle requirement */
1154
#define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1155
#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1157
/* CW RSSI for LCNPHY */
1158
#define M_LCN_RSSI_0 0x1332
1159
#define M_LCN_RSSI_1 0x1338
1160
#define M_LCN_RSSI_2 0x133e
1161
#define M_LCN_RSSI_3 0x1344
1163
/* SNR for LCNPHY */
1164
#define M_LCN_SNR_A_0 0x1334
1165
#define M_LCN_SNR_B_0 0x1336
1167
#define M_LCN_SNR_A_1 0x133a
1168
#define M_LCN_SNR_B_1 0x133c
1170
#define M_LCN_SNR_A_2 0x1340
1171
#define M_LCN_SNR_B_2 0x1342
1173
#define M_LCN_SNR_A_3 0x1346
1174
#define M_LCN_SNR_B_3 0x1348
1176
#define M_LCN_LAST_RESET (81*2)
1177
#define M_LCN_LAST_LOC (63*2)
1178
#define M_LCNPHY_RESET_STATUS (4902)
1179
#define M_LCNPHY_DSC_TIME (0x98d*2)
1180
#define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1181
#define M_LCNPHY_RESET_CNT (0x98c*2)
1183
/* Rate table offsets */
1184
#define M_RT_DIRMAP_A (0xe0 * 2)
1185
#define M_RT_BBRSMAP_A (0xf0 * 2)
1186
#define M_RT_DIRMAP_B (0x100 * 2)
1187
#define M_RT_BBRSMAP_B (0x110 * 2)
1189
/* Rate table entry offsets */
1190
#define M_RT_PRS_PLCP_POS 10
1191
#define M_RT_PRS_DUR_POS 16
1192
#define M_RT_OFDM_PCTL1_POS 18
1194
#define M_20IN40_IQ (0x380 * 2)
1196
/* SHM locations where ucode stores the current power index */
1197
#define M_CURR_IDX1 (0x384 * 2)
1198
#define M_CURR_IDX2 (0x387 * 2)
1200
#define M_BSCALE_ANT0 (0x5e * 2)
1201
#define M_BSCALE_ANT1 (0x5f * 2)
1203
/* Antenna Diversity Testing */
1204
#define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1205
#define M_ANTSEL_CLKDIV (0x61 * 2)
1206
#define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1208
#define M_MIMO_MAXSYM (0x5d * 2)
1209
#define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1210
#define MIMO_MAXSYM_MAX 0xffff /* 64k */
1212
#define M_WATCHDOG_8TU (0x1e * 2)
1213
#define WATCHDOG_8TU_DEF 5
1214
#define WATCHDOG_8TU_MAX 10
1216
/* Manufacturing Test Variables */
1217
#define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1218
#define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1219
#define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1220
#define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1222
/* Index variation in vbat ripple */
1223
#define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1224
#define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1226
/* M_PKTENG_CTRL bit definitions */
1227
#define M_PKTENG_MODE_TX 0x0001
1228
#define M_PKTENG_MODE_TX_RIFS 0x0004
1229
#define M_PKTENG_MODE_TX_CTS 0x0008
1230
#define M_PKTENG_MODE_RX 0x0002
1231
#define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1232
#define M_PKTENG_MODE_MASK 0x0003
1233
#define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1235
/* Sample Collect parameters (bitmap and type) */
1236
#define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */
1237
#define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */
1239
#define ANTSEL_CLKDIV_4MHZ 6
1240
#define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1241
#define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1242
#define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1243
#define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1245
typedef struct shm_acparams shm_acparams_t;
1246
BWL_PRE_PACKED_STRUCT struct shm_acparams {
1256
} BWL_POST_PACKED_STRUCT;
1257
#define M_EDCF_QLEN (16 * 2)
1259
#define WME_STATUS_NEWAC (1 << 8)
1262
#define MHFMAX 5 /* Number of valid hostflag half-word (u16) */
1263
#define MHF1 0 /* Hostflag 1 index */
1264
#define MHF2 1 /* Hostflag 2 index */
1265
#define MHF3 2 /* Hostflag 3 index */
1266
#define MHF4 3 /* Hostflag 4 index */
1267
#define MHF5 4 /* Hostflag 5 index */
1269
/* Flags in M_HOST_FLAGS */
1270
#define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1271
#define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1272
#define MHF1_IQSWAP_WAR 0x0200
1273
#define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1275
/* Flags in M_HOST_FLAGS2 */
1276
#define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1277
#define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1278
#define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */
1279
#define MHF2_NPHY40MHZ_WAR 0x0800
1281
/* Flags in M_HOST_FLAGS3 */
1282
#define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1283
#define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1284
#define MHF3_RESERVED1 0x0004
1285
#define MHF3_RESERVED2 0x0008
1286
#define MHF3_NPHY_MLADV_WAR 0x0010
1288
/* Flags in M_HOST_FLAGS4 */
1289
#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1290
#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1292
/* Flags in M_HOST_FLAGS5 */
1293
#define MHF5_4313_GPIOCTRL 0x0001
1294
#define MHF5_RESERVED1 0x0002
1295
#define MHF5_RESERVED2 0x0004
1296
/* Radio power setting for ucode */
1297
#define M_RADIO_PWR (0x32 * 2)
1299
/* phy noise recorded by ucode right after tx */
1300
#define M_PHY_NOISE (0x037 * 2)
1301
#define PHY_NOISE_MASK 0x00ff
1303
/* Receive Frame Data Header for 802.11b DCF-only frames */
1304
typedef struct d11rxhdr d11rxhdr_t;
1305
BWL_PRE_PACKED_STRUCT struct d11rxhdr {
1306
u16 RxFrameSize; /* Actual byte length of the frame data received */
1308
u16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1309
u16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1310
u16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1311
u16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1312
u16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1313
u16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1314
u16 RxStatus1; /* MAC Rx Status */
1315
u16 RxStatus2; /* extended MAC Rx status */
1316
u16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1317
u16 RxChan; /* gain code, channel radio code, and phy type */
1318
} BWL_POST_PACKED_STRUCT;
1320
#define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
1321
#define FRAMELEN(h) ((h)->RxFrameSize)
1323
typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1324
BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
1326
u32 tsf_l; /* TSF_L reading */
1327
s8 rssi; /* computed instanteneous rssi in BMAC */
1328
s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1329
s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1330
s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1331
s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1332
} BWL_POST_PACKED_STRUCT;
1334
/* PhyRxStatus_0: */
1335
#define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1336
#define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1337
#define PRXS0_CLIP_SHIFT 2
1338
#define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1339
#define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1340
#define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1341
#define PRXS0_SHORTH 0x0080 /* Short Preamble */
1342
#define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1343
#define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1344
#define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1345
#define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1346
#define PRXS0_ANTSEL_SHIFT 0x12
1348
/* subfield PRXS0_FT_MASK */
1349
#define PRXS0_CCK 0x0000
1350
#define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1351
#define PRXS0_PREN 0x0002
1352
#define PRXS0_STDN 0x0003
1354
/* subfield PRXS0_ANTSEL_MASK */
1355
#define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1356
#define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1357
#define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1358
#define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1360
/* PhyRxStatus_1: */
1361
#define PRXS1_JSSI_MASK 0x00FF
1362
#define PRXS1_JSSI_SHIFT 0
1363
#define PRXS1_SQ_MASK 0xFF00
1364
#define PRXS1_SQ_SHIFT 8
1366
/* nphy PhyRxStatus_1: */
1367
#define PRXS1_nphy_PWR0_MASK 0x00FF
1368
#define PRXS1_nphy_PWR1_MASK 0xFF00
1370
/* HTPHY Rx Status defines */
1371
/* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1372
#define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1373
#define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1374
#define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1376
/* htphy PhyRxStatus_1: */
1377
#define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1378
#define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1379
#define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1381
/* htphy PhyRxStatus_2: */
1382
#define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1383
#define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1384
#define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1386
/* htphy PhyRxStatus_3: */
1387
#define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1388
#define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1390
/* htphy PhyRxStatus_4: */
1391
#define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1392
#define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1394
/* htphy PhyRxStatus_5: */
1395
#define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1396
#define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1398
#define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1399
(((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1400
/* Get Rx power on core 0 */
1401
#define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1402
/* Get Rx power on core 1 */
1403
#define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1404
/* Get Rx power on core 2 */
1405
#define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1407
/* ucode RxStatus1: */
1408
#define RXS_BCNSENT 0x8000
1409
#define RXS_SECKINDX_MASK 0x07e0
1410
#define RXS_SECKINDX_SHIFT 5
1411
#define RXS_DECERR (1 << 4)
1412
#define RXS_DECATMPT (1 << 3)
1413
#define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1414
#define RXS_RESPFRAMETX (1 << 1)
1415
#define RXS_FCSERR (1 << 0)
1417
/* ucode RxStatus2: */
1418
#define RXS_AMSDU_MASK 1
1419
#define RXS_AGGTYPE_MASK 0x6
1420
#define RXS_AGGTYPE_SHIFT 1
1421
#define RXS_PHYRXST_VALID (1 << 8)
1422
#define RXS_RXANT_MASK 0x3
1423
#define RXS_RXANT_SHIFT 12
1426
#define RXS_CHAN_40 0x1000
1427
#define RXS_CHAN_5G 0x0800
1428
#define RXS_CHAN_ID_MASK 0x07f8
1429
#define RXS_CHAN_ID_SHIFT 3
1430
#define RXS_CHAN_PHYTYPE_MASK 0x0007
1431
#define RXS_CHAN_PHYTYPE_SHIFT 0
1433
/* Index of attenuations used during ucode power control. */
1434
#define M_PWRIND_BLKS (0x184 * 2)
1435
#define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1436
#define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1437
#define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1438
#define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1439
/* M_PWRIND_MAP(core) macro */
1440
#define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1442
/* PSM SHM variable offsets */
1443
#define M_PSM_SOFT_REGS 0x0
1444
#define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1445
#define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1446
#define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1447
#define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1449
#define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1450
#define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1451
#define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1452
#define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1453
#define M_PRETBTT (0x4b * 2)
1455
#define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1456
#define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1457
#define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1458
#define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1460
/* PKTENG Rx Stats Block */
1461
#define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1463
/* ucode debug status codes */
1464
#define DBGST_INACTIVE 0 /* not valid really */
1465
#define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
1466
#define DBGST_ACTIVE 2 /* "normal" state */
1467
#define DBGST_SUSPENDED 3 /* suspended */
1468
#define DBGST_ASLEEP 4 /* asleep (PS mode) */
1470
/* Scratch Reg defs */
1476
/* scratch registers for Dot11-contants */
1477
S_DOT11_CWMIN, /* CW-minimum 0x03 */
1478
S_DOT11_CWMAX, /* CW-maximum 0x04 */
1479
S_DOT11_CWCUR, /* CW-current 0x05 */
1480
S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
1481
S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
1482
S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
1484
/* Tx-side scratch registers */
1485
S_SEQ_NUM, /* hardware sequence number reg 0x09 */
1486
S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
1487
S_FRMRETX_CNT, /* frame retx count 0x0B */
1488
S_SSRC, /* Station short retry count 0x0C */
1489
S_SLRC, /* Station long retry count 0x0D */
1490
S_EXP_RSP, /* Expected response frame 0x0E */
1491
S_OLD_BREM, /* Remaining backoff ctr 0x0F */
1492
S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
1493
S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
1494
S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
1496
/* Rx-side scratch registers */
1497
S_RXTST, /* Type and subtype in Rxframe 0x13 */
1499
/* Global state register */
1500
S_STREG, /* state storage actual bit maps below 0x14 */
1502
S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
1503
S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
1504
S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
1505
S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
1507
S_KEYINDX, /* 0x19 */
1508
S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
1510
/* Receive TSF time stored in SCR */
1511
S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
1512
S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
1513
S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
1514
S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
1515
S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
1516
S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
1518
/* Scratch pad regs used in microcode as temp storage */
1519
S_TMP0, /* stmp0 0x21 */
1520
S_TMP1, /* stmp1 0x22 */
1521
S_TMP2, /* stmp2 0x23 */
1522
S_TMP3, /* stmp3 0x24 */
1523
S_TMP4, /* stmp4 0x25 */
1524
S_TMP5, /* stmp5 0x26 */
1525
S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
1526
S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
1527
S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
1528
S_RXTP, /* rx frame type 0x2A */
1529
S_STREG2, /* extra state storage 0x2B */
1530
S_STREG3, /* even more extra state storage 0x2C */
1531
S_STREG4, /* ... 0x2D */
1532
S_STREG5, /* remember to initialize it to zero 0x2E */
1535
S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
1536
S_REVID4, /* 0x33 */
1545
S_KEYINDX_BU, /* Backup for Key index 0x3C */
1546
S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
1547
S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
1548
S_STREG6, /* 0x3F */
1549
} ePsmScratchPadRegDefinitions;
1551
#define S_BEACON_INDX S_OLD_BREM
1552
#define S_PRS_INDX S_OLD_CWWIN
1553
#define S_PHYTYPE S_SSRC
1554
#define S_PHYVER S_SLRC
1556
/* IHR SLOW_CTRL values */
1557
#define SLOW_CTRL_PDE (1 << 0)
1558
#define SLOW_CTRL_FD (1 << 8)
1560
/* ucode mac statistic counters in shared memory */
1561
typedef struct macstat {
1562
u16 txallfrm; /* 0x80 */
1563
u16 txrtsfrm; /* 0x82 */
1564
u16 txctsfrm; /* 0x84 */
1565
u16 txackfrm; /* 0x86 */
1566
u16 txdnlfrm; /* 0x88 */
1567
u16 txbcnfrm; /* 0x8a */
1568
u16 txfunfl[8]; /* 0x8c - 0x9b */
1569
u16 txtplunfl; /* 0x9c */
1570
u16 txphyerr; /* 0x9e */
1571
u16 pktengrxducast; /* 0xa0 */
1572
u16 pktengrxdmcast; /* 0xa2 */
1573
u16 rxfrmtoolong; /* 0xa4 */
1574
u16 rxfrmtooshrt; /* 0xa6 */
1575
u16 rxinvmachdr; /* 0xa8 */
1576
u16 rxbadfcs; /* 0xaa */
1577
u16 rxbadplcp; /* 0xac */
1578
u16 rxcrsglitch; /* 0xae */
1579
u16 rxstrt; /* 0xb0 */
1580
u16 rxdfrmucastmbss; /* 0xb2 */
1581
u16 rxmfrmucastmbss; /* 0xb4 */
1582
u16 rxcfrmucast; /* 0xb6 */
1583
u16 rxrtsucast; /* 0xb8 */
1584
u16 rxctsucast; /* 0xba */
1585
u16 rxackucast; /* 0xbc */
1586
u16 rxdfrmocast; /* 0xbe */
1587
u16 rxmfrmocast; /* 0xc0 */
1588
u16 rxcfrmocast; /* 0xc2 */
1589
u16 rxrtsocast; /* 0xc4 */
1590
u16 rxctsocast; /* 0xc6 */
1591
u16 rxdfrmmcast; /* 0xc8 */
1592
u16 rxmfrmmcast; /* 0xca */
1593
u16 rxcfrmmcast; /* 0xcc */
1594
u16 rxbeaconmbss; /* 0xce */
1595
u16 rxdfrmucastobss; /* 0xd0 */
1596
u16 rxbeaconobss; /* 0xd2 */
1597
u16 rxrsptmout; /* 0xd4 */
1598
u16 bcntxcancl; /* 0xd6 */
1600
u16 rxf0ovfl; /* 0xda */
1601
u16 rxf1ovfl; /* 0xdc */
1602
u16 rxf2ovfl; /* 0xde */
1603
u16 txsfovfl; /* 0xe0 */
1604
u16 pmqovfl; /* 0xe2 */
1605
u16 rxcgprqfrm; /* 0xe4 */
1606
u16 rxcgprsqovfl; /* 0xe6 */
1607
u16 txcgprsfail; /* 0xe8 */
1608
u16 txcgprssuc; /* 0xea */
1609
u16 prs_timeout; /* 0xec */
1614
u16 txburst; /* 0xf6 # tx bursts */
1615
u16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1616
u16 phywatchdog; /* 0xfa # of phy watchdog events */
1618
u16 bphy_badplcp; /* bphy bad plcp */
1621
/* dot11 core-specific control flags */
1622
#define SICF_PCLKE 0x0004 /* PHY clock enable */
1623
#define SICF_PRST 0x0008 /* PHY reset */
1624
#define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1625
#define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */
1626
/* NOTE: the following bw bits only apply when the core is attached
1627
* to a NPHY (and corerev >= 11 which it will always be for NPHYs).
1629
#define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1630
#define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1631
#define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1632
#define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1633
#define SICF_GMODE 0x2000 /* gmode enable */
1635
/* dot11 core-specific status flags */
1636
#define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */
1637
#define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */
1638
#define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */
1639
#define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */
1641
/* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
1643
#define BPHY_REG_OFT_BASE 0x0
1644
/* offsets for indirect access to bphy registers */
1645
#define BPHY_BB_CONFIG 0x01
1646
#define BPHY_ADCBIAS 0x02
1647
#define BPHY_ANACORE 0x03
1648
#define BPHY_PHYCRSTH 0x06
1649
#define BPHY_TEST 0x0a
1650
#define BPHY_PA_TX_TO 0x10
1651
#define BPHY_SYNTH_DC_TO 0x11
1652
#define BPHY_PA_TX_TIME_UP 0x12
1653
#define BPHY_RX_FLTR_TIME_UP 0x13
1654
#define BPHY_TX_POWER_OVERRIDE 0x14
1655
#define BPHY_RF_OVERRIDE 0x15
1656
#define BPHY_RF_TR_LOOKUP1 0x16
1657
#define BPHY_RF_TR_LOOKUP2 0x17
1658
#define BPHY_COEFFS 0x18
1659
#define BPHY_PLL_OUT 0x19
1660
#define BPHY_REFRESH_MAIN 0x1a
1661
#define BPHY_REFRESH_TO0 0x1b
1662
#define BPHY_REFRESH_TO1 0x1c
1663
#define BPHY_RSSI_TRESH 0x20
1664
#define BPHY_IQ_TRESH_HH 0x21
1665
#define BPHY_IQ_TRESH_H 0x22
1666
#define BPHY_IQ_TRESH_L 0x23
1667
#define BPHY_IQ_TRESH_LL 0x24
1668
#define BPHY_GAIN 0x25
1669
#define BPHY_LNA_GAIN_RANGE 0x26
1670
#define BPHY_JSSI 0x27
1671
#define BPHY_TSSI_CTL 0x28
1672
#define BPHY_TSSI 0x29
1673
#define BPHY_TR_LOSS_CTL 0x2a
1674
#define BPHY_LO_LEAKAGE 0x2b
1675
#define BPHY_LO_RSSI_ACC 0x2c
1676
#define BPHY_LO_IQMAG_ACC 0x2d
1677
#define BPHY_TX_DC_OFF1 0x2e
1678
#define BPHY_TX_DC_OFF2 0x2f
1679
#define BPHY_PEAK_CNT_THRESH 0x30
1680
#define BPHY_FREQ_OFFSET 0x31
1681
#define BPHY_DIVERSITY_CTL 0x32
1682
#define BPHY_PEAK_ENERGY_LO 0x33
1683
#define BPHY_PEAK_ENERGY_HI 0x34
1684
#define BPHY_SYNC_CTL 0x35
1685
#define BPHY_TX_PWR_CTRL 0x36
1686
#define BPHY_TX_EST_PWR 0x37
1687
#define BPHY_STEP 0x38
1688
#define BPHY_WARMUP 0x39
1689
#define BPHY_LMS_CFF_READ 0x3a
1690
#define BPHY_LMS_COEFF_I 0x3b
1691
#define BPHY_LMS_COEFF_Q 0x3c
1692
#define BPHY_SIG_POW 0x3d
1693
#define BPHY_RFDC_CANCEL_CTL 0x3e
1694
#define BPHY_HDR_TYPE 0x40
1695
#define BPHY_SFD_TO 0x41
1696
#define BPHY_SFD_CTL 0x42
1697
#define BPHY_DEBUG 0x43
1698
#define BPHY_RX_DELAY_COMP 0x44
1699
#define BPHY_CRS_DROP_TO 0x45
1700
#define BPHY_SHORT_SFD_NZEROS 0x46
1701
#define BPHY_DSSS_COEFF1 0x48
1702
#define BPHY_DSSS_COEFF2 0x49
1703
#define BPHY_CCK_COEFF1 0x4a
1704
#define BPHY_CCK_COEFF2 0x4b
1705
#define BPHY_TR_CORR 0x4c
1706
#define BPHY_ANGLE_SCALE 0x4d
1707
#define BPHY_TX_PWR_BASE_IDX 0x4e
1708
#define BPHY_OPTIONAL_MODES2 0x4f
1709
#define BPHY_CCK_LMS_STEP 0x50
1710
#define BPHY_BYPASS 0x51
1711
#define BPHY_CCK_DELAY_LONG 0x52
1712
#define BPHY_CCK_DELAY_SHORT 0x53
1713
#define BPHY_PPROC_CHAN_DELAY 0x54
1714
#define BPHY_DDFS_ENABLE 0x58
1715
#define BPHY_PHASE_SCALE 0x59
1716
#define BPHY_FREQ_CONTROL 0x5a
1717
#define BPHY_LNA_GAIN_RANGE_10 0x5b
1718
#define BPHY_LNA_GAIN_RANGE_32 0x5c
1719
#define BPHY_OPTIONAL_MODES 0x5d
1720
#define BPHY_RX_STATUS2 0x5e
1721
#define BPHY_RX_STATUS3 0x5f
1722
#define BPHY_DAC_CONTROL 0x60
1723
#define BPHY_ANA11G_FILT_CTRL 0x62
1724
#define BPHY_REFRESH_CTRL 0x64
1725
#define BPHY_RF_OVERRIDE2 0x65
1726
#define BPHY_SPUR_CANCEL_CTRL 0x66
1727
#define BPHY_FINE_DIGIGAIN_CTRL 0x67
1728
#define BPHY_RSSI_LUT 0x88
1729
#define BPHY_RSSI_LUT_END 0xa7
1730
#define BPHY_TSSI_LUT 0xa8
1731
#define BPHY_TSSI_LUT_END 0xc7
1732
#define BPHY_TSSI2PWR_LUT 0x380
1733
#define BPHY_TSSI2PWR_LUT_END 0x39f
1734
#define BPHY_LOCOMP_LUT 0x3a0
1735
#define BPHY_LOCOMP_LUT_END 0x3bf
1736
#define BPHY_TXGAIN_LUT 0x3c0
1737
#define BPHY_TXGAIN_LUT_END 0x3ff
1739
/* Bits in BB_CONFIG: */
1740
#define PHY_BBC_ANT_MASK 0x0180
1741
#define PHY_BBC_ANT_SHIFT 7
1742
#define BB_DARWIN 0x1000
1743
#define BBCFG_RESETCCA 0x4000
1744
#define BBCFG_RESETRX 0x8000
1746
/* Bits in phytest(0x0a): */
1747
#define TST_DDFS 0x2000
1748
#define TST_TXFILT1 0x0800
1749
#define TST_UNSCRAM 0x0400
1750
#define TST_CARR_SUPP 0x0200
1751
#define TST_DC_COMP_LOOP 0x0100
1752
#define TST_LOOPBACK 0x0080
1753
#define TST_TXFILT0 0x0040
1754
#define TST_TXTEST_ENABLE 0x0020
1755
#define TST_TXTEST_RATE 0x0018
1756
#define TST_TXTEST_PHASE 0x0007
1758
/* phytest txTestRate values */
1759
#define TST_TXTEST_RATE_1MBPS 0
1760
#define TST_TXTEST_RATE_2MBPS 1
1761
#define TST_TXTEST_RATE_5_5MBPS 2
1762
#define TST_TXTEST_RATE_11MBPS 3
1763
#define TST_TXTEST_RATE_SHIFT 3
1765
/* This marks the end of a packed structure section. */
1766
#include <packed_section_end.h>
1768
#define SHM_BYT_CNT 0x2 /* IHR location */
1769
#define MAX_BYT_CNT 0x600 /* Maximum frame len */
added
removed
drivers/staging/brcm80211/include/d11.h
