2
* Copyright (c) 2010 Broadcom Corporation
4
* Permission to use, copy, modify, and/or distribute this software for any
5
* purpose with or without fee is hereby granted, provided that the above
6
* copyright notice and this permission notice appear in all copies.
8
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20
#ifndef _LANGUAGE_ASSEMBLY
22
/* cpp contortions to concatenate w/arg prescan */
24
#define _PADLINE(line) pad ## line
25
#define _XSTR(line) _PADLINE(line)
26
#define PAD _XSTR(__LINE__)
29
/* Memcsocram core registers */
30
typedef volatile struct sbsocramregs {
38
u32 errlogstatus; /* rev 6 */
39
u32 errlogaddr; /* rev 6 */
40
/* used for patching rev 3 & 5 */
42
u32 cambankstandbyctrl;
44
u32 cambankpatchtblbaseaddr;
49
u32 bankinfo; /* corev 8 */
53
u32 extmemparityerrdata;
54
u32 extmemparityerrcnt;
55
u32 extmemwrctrlandsize;
58
u32 pwrctl; /* corerev >= 2 */
61
#endif /* _LANGUAGE_ASSEMBLY */
63
/* Register offsets */
64
#define SR_COREINFO 0x00
65
#define SR_BWALLOC 0x04
66
#define SR_BISTSTAT 0x0c
67
#define SR_BANKINDEX 0x10
68
#define SR_BANKSTBYCTL 0x14
69
#define SR_PWRCTL 0x1e8
71
/* Coreinfo register */
72
#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */
73
#define SRCI_PT_SHIFT 16
74
/* port types : SRCI_PT_<processorPT>_<backplanePT> */
75
#define SRCI_PT_OCP_OCP 0
76
#define SRCI_PT_AXI_OCP 1
77
#define SRCI_PT_ARM7AHB_OCP 2
78
#define SRCI_PT_CM3AHB_OCP 3
79
#define SRCI_PT_AXI_AXI 4
80
#define SRCI_PT_AHB_AXI 5
82
#define SRCI_LSS_MASK 0x00f00000
83
#define SRCI_LSS_SHIFT 20
84
#define SRCI_LRS_MASK 0x0f000000
85
#define SRCI_LRS_SHIFT 24
87
/* In corerev 0, the memory size is 2 to the power of the
88
* base plus 16 plus to the contents of the memsize field plus 1.
90
#define SRCI_MS0_MASK 0xf
91
#define SR_MS0_BASE 16
94
* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
95
* the memory size is number of banks times bank size.
96
* The same applies to rom size.
98
#define SRCI_ROMNB_MASK 0xf000
99
#define SRCI_ROMNB_SHIFT 12
100
#define SRCI_ROMBSZ_MASK 0xf00
101
#define SRCI_ROMBSZ_SHIFT 8
102
#define SRCI_SRNB_MASK 0xf0
103
#define SRCI_SRNB_SHIFT 4
104
#define SRCI_SRBSZ_MASK 0xf
105
#define SRCI_SRBSZ_SHIFT 0
107
#define SR_BSZ_BASE 14
109
/* Standby control register */
110
#define SRSC_SBYOVR_MASK 0x80000000
111
#define SRSC_SBYOVR_SHIFT 31
112
#define SRSC_SBYOVRVAL_MASK 0x60000000
113
#define SRSC_SBYOVRVAL_SHIFT 29
114
#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */
115
#define SRSC_SBYEN_SHIFT 24
117
/* Power control register */
118
#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */
119
#define SRPC_PMU_STBYDIS_SHIFT 4
120
#define SRPC_STBYOVRVAL_MASK 0x00000008
121
#define SRPC_STBYOVRVAL_SHIFT 3
122
#define SRPC_STBYOVR_MASK 0x00000007
123
#define SRPC_STBYOVR_SHIFT 0
125
/* Extra core capability register */
126
#define SRECC_NUM_BANKS_MASK 0x000000F0
127
#define SRECC_NUM_BANKS_SHIFT 4
128
#define SRECC_BANKSIZE_MASK 0x0000000F
129
#define SRECC_BANKSIZE_SHIFT 0
131
#define SRECC_BANKSIZE(value) (1 << (value))
133
/* CAM bank patch control */
134
#define SRCBPC_PATCHENABLE 0x80000000
136
#define SRP_ADDRESS 0x0001FFFC
137
#define SRP_VALID 0x8000
139
/* CAM bank command reg */
140
#define SRCMD_WRITE 0x00020000
141
#define SRCMD_READ 0x00010000
142
#define SRCMD_DONE 0x80000000
144
#define SRCMD_DONE_DLY 1000
146
/* bankidx and bankinfo reg defines corerev >= 8 */
147
#define SOCRAM_BANKINFO_SZMASK 0x3f
148
#define SOCRAM_BANKIDX_ROM_MASK 0x100
150
#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
151
/* socram bankinfo memtype */
152
#define SOCRAM_MEMTYPE_RAM 0
153
#define SOCRAM_MEMTYPE_R0M 1
154
#define SOCRAM_MEMTYPE_DEVRAM 2
156
#define SOCRAM_BANKINFO_REG 0x40
157
#define SOCRAM_BANKIDX_REG 0x10
158
#define SOCRAM_BANKINFO_STDBY_MASK 0x400
159
#define SOCRAM_BANKINFO_STDBY_TIMER 0x800
161
/* bankinfo rev >= 10 */
162
#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13
163
#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000
164
#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14
165
#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000
167
/* extracoreinfo register */
168
#define SOCRAM_DEVRAMBANK_MASK 0xF000
169
#define SOCRAM_DEVRAMBANK_SHIFT 12
171
/* bank info to calculate bank size */
172
#define SOCRAM_BANKINFO_SZBASE 8192
173
#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */
175
#endif /* _SBSOCRAM_H */